150 lines
5.3 KiB
C
150 lines
5.3 KiB
C
/* linux/driver/video/exynos/exynos_mipi_dsi_regs.h
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*
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* Register definition file for Samsung MIPI-DSIM driver
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*
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* Copyright (c) 2012 Samsung Electronics Co., Ltd
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*
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* InKi Dae <inki.dae@samsung.com>
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* Donghwa Lee <dh09.lee@samsung.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#ifndef _EXYNOS_MIPI_DSI_REGS_H
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#define _EXYNOS_MIPI_DSI_REGS_H
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#define EXYNOS_DSIM_STATUS 0x0 /* Status register */
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#define EXYNOS_DSIM_SWRST 0x4 /* Software reset register */
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#define EXYNOS_DSIM_CLKCTRL 0x8 /* Clock control register */
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#define EXYNOS_DSIM_TIMEOUT 0xc /* Time out register */
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#define EXYNOS_DSIM_CONFIG 0x10 /* Configuration register */
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#define EXYNOS_DSIM_ESCMODE 0x14 /* Escape mode register */
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/* Main display image resolution register */
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#define EXYNOS_DSIM_MDRESOL 0x18
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#define EXYNOS_DSIM_MVPORCH 0x1c /* Main display Vporch register */
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#define EXYNOS_DSIM_MHPORCH 0x20 /* Main display Hporch register */
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#define EXYNOS_DSIM_MSYNC 0x24 /* Main display sync area register */
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/* Sub display image resolution register */
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#define EXYNOS_DSIM_SDRESOL 0x28
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#define EXYNOS_DSIM_INTSRC 0x2c /* Interrupt source register */
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#define EXYNOS_DSIM_INTMSK 0x30 /* Interrupt mask register */
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#define EXYNOS_DSIM_PKTHDR 0x34 /* Packet Header FIFO register */
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#define EXYNOS_DSIM_PAYLOAD 0x38 /* Payload FIFO register */
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#define EXYNOS_DSIM_RXFIFO 0x3c /* Read FIFO register */
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#define EXYNOS_DSIM_FIFOTHLD 0x40 /* FIFO threshold level register */
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#define EXYNOS_DSIM_FIFOCTRL 0x44 /* FIFO status and control register */
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/* FIFO memory AC characteristic register */
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#define EXYNOS_DSIM_PLLCTRL 0x4c /* PLL control register */
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#define EXYNOS_DSIM_PLLTMR 0x50 /* PLL timer register */
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#define EXYNOS_DSIM_PHYACCHR 0x54 /* D-PHY AC characteristic register */
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#define EXYNOS_DSIM_PHYACCHR1 0x58 /* D-PHY AC characteristic register1 */
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/* DSIM_STATUS */
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#define DSIM_STOP_STATE_DAT(x) (((x) & 0xf) << 0)
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#define DSIM_STOP_STATE_CLK (1 << 8)
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#define DSIM_TX_READY_HS_CLK (1 << 10)
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/* DSIM_SWRST */
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#define DSIM_FUNCRST (1 << 16)
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#define DSIM_SWRST (1 << 0)
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/* EXYNOS_DSIM_TIMEOUT */
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#define DSIM_LPDR_TOUT_SHIFT(x) ((x) << 0)
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#define DSIM_BTA_TOUT_SHIFT(x) ((x) << 16)
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/* EXYNOS_DSIM_CLKCTRL */
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#define DSIM_LANE_ESC_CLKEN(x) (((x) & 0x1f) << 19)
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#define DSIM_BYTE_CLKEN_SHIFT(x) ((x) << 24)
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#define DSIM_BYTE_CLK_SRC_SHIFT(x) ((x) << 25)
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#define DSIM_PLL_BYPASS_SHIFT(x) ((x) << 27)
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#define DSIM_ESC_CLKEN_SHIFT(x) ((x) << 28)
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#define DSIM_TX_REQUEST_HSCLK_SHIFT(x) ((x) << 31)
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/* EXYNOS_DSIM_CONFIG */
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#define DSIM_LANE_ENx(x) (((x) & 0x1f) << 0)
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#define DSIM_NUM_OF_DATALANE_SHIFT(x) ((x) << 5)
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#define DSIM_HSA_MODE_SHIFT(x) ((x) << 20)
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#define DSIM_HBP_MODE_SHIFT(x) ((x) << 21)
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#define DSIM_HFP_MODE_SHIFT(x) ((x) << 22)
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#define DSIM_HSE_MODE_SHIFT(x) ((x) << 23)
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#define DSIM_AUTO_MODE_SHIFT(x) ((x) << 24)
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#define DSIM_EOT_DISABLE(x) ((x) << 28)
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#define DSIM_AUTO_FLUSH(x) ((x) << 29)
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#define DSIM_NUM_OF_DATA_LANE(x) ((x) << DSIM_NUM_OF_DATALANE_SHIFT)
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/* EXYNOS_DSIM_ESCMODE */
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#define DSIM_TX_LPDT_LP (1 << 6)
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#define DSIM_CMD_LPDT_LP (1 << 7)
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#define DSIM_FORCE_STOP_STATE_SHIFT(x) ((x) << 20)
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#define DSIM_STOP_STATE_CNT_SHIFT(x) ((x) << 21)
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/* EXYNOS_DSIM_MDRESOL */
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#define DSIM_MAIN_STAND_BY (1 << 31)
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#define DSIM_MAIN_VRESOL(x) (((x) & 0x7ff) << 16)
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#define DSIM_MAIN_HRESOL(x) (((x) & 0X7ff) << 0)
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/* EXYNOS_DSIM_MVPORCH */
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#define DSIM_CMD_ALLOW_SHIFT(x) ((x) << 28)
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#define DSIM_STABLE_VFP_SHIFT(x) ((x) << 16)
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#define DSIM_MAIN_VBP_SHIFT(x) ((x) << 0)
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#define DSIM_CMD_ALLOW_MASK (0xf << 28)
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#define DSIM_STABLE_VFP_MASK (0x7ff << 16)
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#define DSIM_MAIN_VBP_MASK (0x7ff << 0)
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/* EXYNOS_DSIM_MHPORCH */
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#define DSIM_MAIN_HFP_SHIFT(x) ((x) << 16)
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#define DSIM_MAIN_HBP_SHIFT(x) ((x) << 0)
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#define DSIM_MAIN_HFP_MASK ((0xffff) << 16)
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#define DSIM_MAIN_HBP_MASK ((0xffff) << 0)
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/* EXYNOS_DSIM_MSYNC */
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#define DSIM_MAIN_VSA_SHIFT(x) ((x) << 22)
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#define DSIM_MAIN_HSA_SHIFT(x) ((x) << 0)
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#define DSIM_MAIN_VSA_MASK ((0x3ff) << 22)
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#define DSIM_MAIN_HSA_MASK ((0xffff) << 0)
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/* EXYNOS_DSIM_SDRESOL */
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#define DSIM_SUB_STANDY_SHIFT(x) ((x) << 31)
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#define DSIM_SUB_VRESOL_SHIFT(x) ((x) << 16)
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#define DSIM_SUB_HRESOL_SHIFT(x) ((x) << 0)
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#define DSIM_SUB_STANDY_MASK ((0x1) << 31)
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#define DSIM_SUB_VRESOL_MASK ((0x7ff) << 16)
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#define DSIM_SUB_HRESOL_MASK ((0x7ff) << 0)
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/* EXYNOS_DSIM_INTSRC */
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#define INTSRC_PLL_STABLE (1 << 31)
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#define INTSRC_SW_RST_RELEASE (1 << 30)
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#define INTSRC_SFR_FIFO_EMPTY (1 << 29)
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#define INTSRC_FRAME_DONE (1 << 24)
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#define INTSRC_RX_DATA_DONE (1 << 18)
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/* EXYNOS_DSIM_INTMSK */
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#define INTMSK_FIFO_EMPTY (1 << 29)
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#define INTMSK_BTA (1 << 25)
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#define INTMSK_FRAME_DONE (1 << 24)
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#define INTMSK_RX_TIMEOUT (1 << 21)
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#define INTMSK_BTA_TIMEOUT (1 << 20)
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#define INTMSK_RX_DONE (1 << 18)
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#define INTMSK_RX_TE (1 << 17)
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#define INTMSK_RX_ACK (1 << 16)
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#define INTMSK_RX_ECC_ERR (1 << 15)
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#define INTMSK_RX_CRC_ERR (1 << 14)
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/* EXYNOS_DSIM_FIFOCTRL */
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#define SFR_HEADER_EMPTY (1 << 22)
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/* EXYNOS_DSIM_PHYACCHR */
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#define DSIM_AFC_CTL(x) (((x) & 0x7) << 5)
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/* EXYNOS_DSIM_PLLCTRL */
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#define DSIM_PLL_EN_SHIFT(x) ((x) << 23)
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#define DSIM_FREQ_BAND_SHIFT(x) ((x) << 24)
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#endif /* _EXYNOS_MIPI_DSI_REGS_H */
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