507 lines
13 KiB
C
507 lines
13 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* Intel Whiskey Cove PMIC GPIO Driver
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*
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* This driver is written based on gpio-crystalcove.c
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*
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* Copyright (C) 2016 Intel Corporation. All rights reserved.
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*/
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#include <linux/bitops.h>
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#include <linux/gpio/driver.h>
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#include <linux/interrupt.h>
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#include <linux/mfd/intel_soc_pmic.h>
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#include <linux/module.h>
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#include <linux/platform_device.h>
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#include <linux/regmap.h>
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#include <linux/seq_file.h>
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/*
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* Whiskey Cove PMIC has 13 physical GPIO pins divided into 3 banks:
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* Bank 0: Pin 0 - 6
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* Bank 1: Pin 7 - 10
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* Bank 2: Pin 11 - 12
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* Each pin has one output control register and one input control register.
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*/
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#define BANK0_NR_PINS 7
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#define BANK1_NR_PINS 4
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#define BANK2_NR_PINS 2
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#define WCOVE_GPIO_NUM (BANK0_NR_PINS + BANK1_NR_PINS + BANK2_NR_PINS)
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#define WCOVE_VGPIO_NUM 94
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/* GPIO output control registers (one per pin): 0x4e44 - 0x4e50 */
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#define GPIO_OUT_CTRL_BASE 0x4e44
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/* GPIO input control registers (one per pin): 0x4e51 - 0x4e5d */
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#define GPIO_IN_CTRL_BASE 0x4e51
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/*
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* GPIO interrupts are organized in two groups:
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* Group 0: Bank 0 pins (Pin 0 - 6)
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* Group 1: Bank 1 and Bank 2 pins (Pin 7 - 12)
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* Each group has two registers (one bit per pin): status and mask.
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*/
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#define GROUP0_NR_IRQS 7
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#define GROUP1_NR_IRQS 6
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#define IRQ_MASK_BASE 0x4e19
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#define IRQ_STATUS_BASE 0x4e0b
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#define GPIO_IRQ0_MASK GENMASK(6, 0)
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#define GPIO_IRQ1_MASK GENMASK(5, 0)
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#define UPDATE_IRQ_TYPE BIT(0)
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#define UPDATE_IRQ_MASK BIT(1)
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#define CTLI_INTCNT_DIS (0 << 1)
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#define CTLI_INTCNT_NE (1 << 1)
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#define CTLI_INTCNT_PE (2 << 1)
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#define CTLI_INTCNT_BE (3 << 1)
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#define CTLO_DIR_IN (0 << 5)
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#define CTLO_DIR_OUT (1 << 5)
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#define CTLO_DRV_MASK (1 << 4)
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#define CTLO_DRV_OD (0 << 4)
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#define CTLO_DRV_CMOS (1 << 4)
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#define CTLO_DRV_REN (1 << 3)
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#define CTLO_RVAL_2KDOWN (0 << 1)
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#define CTLO_RVAL_2KUP (1 << 1)
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#define CTLO_RVAL_50KDOWN (2 << 1)
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#define CTLO_RVAL_50KUP (3 << 1)
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#define CTLO_INPUT_SET (CTLO_DRV_CMOS | CTLO_DRV_REN | CTLO_RVAL_2KUP)
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#define CTLO_OUTPUT_SET (CTLO_DIR_OUT | CTLO_INPUT_SET)
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enum ctrl_register {
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CTRL_IN,
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CTRL_OUT,
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};
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/*
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* struct wcove_gpio - Whiskey Cove GPIO controller
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* @buslock: for bus lock/sync and unlock.
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* @chip: the abstract gpio_chip structure.
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* @dev: the gpio device
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* @regmap: the regmap from the parent device.
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* @regmap_irq_chip: the regmap of the gpio irq chip.
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* @update: pending IRQ setting update, to be written to the chip upon unlock.
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* @intcnt: the Interrupt Detect value to be written.
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* @set_irq_mask: true if the IRQ mask needs to be set, false to clear.
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*/
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struct wcove_gpio {
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struct mutex buslock;
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struct gpio_chip chip;
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struct device *dev;
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struct regmap *regmap;
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struct regmap_irq_chip_data *regmap_irq_chip;
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int update;
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int intcnt;
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bool set_irq_mask;
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};
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static inline int to_reg(int gpio, enum ctrl_register reg_type)
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{
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unsigned int reg;
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if (gpio >= WCOVE_GPIO_NUM)
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return -EOPNOTSUPP;
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if (reg_type == CTRL_IN)
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reg = GPIO_IN_CTRL_BASE + gpio;
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else
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reg = GPIO_OUT_CTRL_BASE + gpio;
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return reg;
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}
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static void wcove_update_irq_mask(struct wcove_gpio *wg, int gpio)
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{
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unsigned int reg, mask;
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if (gpio < GROUP0_NR_IRQS) {
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reg = IRQ_MASK_BASE;
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mask = BIT(gpio % GROUP0_NR_IRQS);
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} else {
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reg = IRQ_MASK_BASE + 1;
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mask = BIT((gpio - GROUP0_NR_IRQS) % GROUP1_NR_IRQS);
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}
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if (wg->set_irq_mask)
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regmap_update_bits(wg->regmap, reg, mask, mask);
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else
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regmap_update_bits(wg->regmap, reg, mask, 0);
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}
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static void wcove_update_irq_ctrl(struct wcove_gpio *wg, int gpio)
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{
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int reg = to_reg(gpio, CTRL_IN);
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if (reg < 0)
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return;
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regmap_update_bits(wg->regmap, reg, CTLI_INTCNT_BE, wg->intcnt);
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}
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static int wcove_gpio_dir_in(struct gpio_chip *chip, unsigned int gpio)
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{
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struct wcove_gpio *wg = gpiochip_get_data(chip);
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int reg = to_reg(gpio, CTRL_OUT);
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if (reg < 0)
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return 0;
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return regmap_write(wg->regmap, reg, CTLO_INPUT_SET);
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}
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static int wcove_gpio_dir_out(struct gpio_chip *chip, unsigned int gpio,
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int value)
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{
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struct wcove_gpio *wg = gpiochip_get_data(chip);
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int reg = to_reg(gpio, CTRL_OUT);
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if (reg < 0)
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return 0;
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return regmap_write(wg->regmap, reg, CTLO_OUTPUT_SET | value);
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}
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static int wcove_gpio_get_direction(struct gpio_chip *chip, unsigned int gpio)
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{
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struct wcove_gpio *wg = gpiochip_get_data(chip);
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unsigned int val;
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int ret, reg = to_reg(gpio, CTRL_OUT);
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if (reg < 0)
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return GPIO_LINE_DIRECTION_OUT;
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ret = regmap_read(wg->regmap, reg, &val);
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if (ret)
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return ret;
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if (val & CTLO_DIR_OUT)
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return GPIO_LINE_DIRECTION_OUT;
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return GPIO_LINE_DIRECTION_IN;
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}
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static int wcove_gpio_get(struct gpio_chip *chip, unsigned int gpio)
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{
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struct wcove_gpio *wg = gpiochip_get_data(chip);
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unsigned int val;
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int ret, reg = to_reg(gpio, CTRL_IN);
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if (reg < 0)
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return 0;
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ret = regmap_read(wg->regmap, reg, &val);
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if (ret)
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return ret;
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return val & 0x1;
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}
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static void wcove_gpio_set(struct gpio_chip *chip, unsigned int gpio, int value)
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{
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struct wcove_gpio *wg = gpiochip_get_data(chip);
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int reg = to_reg(gpio, CTRL_OUT);
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if (reg < 0)
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return;
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if (value)
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regmap_update_bits(wg->regmap, reg, 1, 1);
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else
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regmap_update_bits(wg->regmap, reg, 1, 0);
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}
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static int wcove_gpio_set_config(struct gpio_chip *chip, unsigned int gpio,
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unsigned long config)
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{
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struct wcove_gpio *wg = gpiochip_get_data(chip);
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int reg = to_reg(gpio, CTRL_OUT);
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if (reg < 0)
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return 0;
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switch (pinconf_to_config_param(config)) {
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case PIN_CONFIG_DRIVE_OPEN_DRAIN:
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return regmap_update_bits(wg->regmap, reg, CTLO_DRV_MASK,
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CTLO_DRV_OD);
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case PIN_CONFIG_DRIVE_PUSH_PULL:
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return regmap_update_bits(wg->regmap, reg, CTLO_DRV_MASK,
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CTLO_DRV_CMOS);
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default:
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break;
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}
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return -ENOTSUPP;
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}
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static int wcove_irq_type(struct irq_data *data, unsigned int type)
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{
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struct gpio_chip *chip = irq_data_get_irq_chip_data(data);
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struct wcove_gpio *wg = gpiochip_get_data(chip);
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if (data->hwirq >= WCOVE_GPIO_NUM)
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return 0;
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switch (type) {
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case IRQ_TYPE_NONE:
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wg->intcnt = CTLI_INTCNT_DIS;
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break;
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case IRQ_TYPE_EDGE_BOTH:
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wg->intcnt = CTLI_INTCNT_BE;
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break;
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case IRQ_TYPE_EDGE_RISING:
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wg->intcnt = CTLI_INTCNT_PE;
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break;
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case IRQ_TYPE_EDGE_FALLING:
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wg->intcnt = CTLI_INTCNT_NE;
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break;
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default:
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return -EINVAL;
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}
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wg->update |= UPDATE_IRQ_TYPE;
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return 0;
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}
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static void wcove_bus_lock(struct irq_data *data)
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{
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struct gpio_chip *chip = irq_data_get_irq_chip_data(data);
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struct wcove_gpio *wg = gpiochip_get_data(chip);
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mutex_lock(&wg->buslock);
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}
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static void wcove_bus_sync_unlock(struct irq_data *data)
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{
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struct gpio_chip *chip = irq_data_get_irq_chip_data(data);
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struct wcove_gpio *wg = gpiochip_get_data(chip);
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int gpio = data->hwirq;
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if (wg->update & UPDATE_IRQ_TYPE)
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wcove_update_irq_ctrl(wg, gpio);
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if (wg->update & UPDATE_IRQ_MASK)
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wcove_update_irq_mask(wg, gpio);
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wg->update = 0;
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mutex_unlock(&wg->buslock);
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}
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static void wcove_irq_unmask(struct irq_data *data)
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{
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struct gpio_chip *chip = irq_data_get_irq_chip_data(data);
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struct wcove_gpio *wg = gpiochip_get_data(chip);
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if (data->hwirq >= WCOVE_GPIO_NUM)
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return;
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wg->set_irq_mask = false;
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wg->update |= UPDATE_IRQ_MASK;
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}
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static void wcove_irq_mask(struct irq_data *data)
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{
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struct gpio_chip *chip = irq_data_get_irq_chip_data(data);
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struct wcove_gpio *wg = gpiochip_get_data(chip);
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if (data->hwirq >= WCOVE_GPIO_NUM)
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return;
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wg->set_irq_mask = true;
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wg->update |= UPDATE_IRQ_MASK;
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}
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static struct irq_chip wcove_irqchip = {
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.name = "Whiskey Cove",
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.irq_mask = wcove_irq_mask,
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.irq_unmask = wcove_irq_unmask,
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.irq_set_type = wcove_irq_type,
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.irq_bus_lock = wcove_bus_lock,
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.irq_bus_sync_unlock = wcove_bus_sync_unlock,
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};
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static irqreturn_t wcove_gpio_irq_handler(int irq, void *data)
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{
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struct wcove_gpio *wg = (struct wcove_gpio *)data;
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unsigned int pending, virq, gpio, mask, offset;
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u8 p[2];
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if (regmap_bulk_read(wg->regmap, IRQ_STATUS_BASE, p, 2)) {
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dev_err(wg->dev, "Failed to read irq status register\n");
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return IRQ_NONE;
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}
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pending = (p[0] & GPIO_IRQ0_MASK) | ((p[1] & GPIO_IRQ1_MASK) << 7);
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if (!pending)
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return IRQ_NONE;
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/* Iterate until no interrupt is pending */
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while (pending) {
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/* One iteration is for all pending bits */
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for_each_set_bit(gpio, (const unsigned long *)&pending,
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WCOVE_GPIO_NUM) {
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offset = (gpio > GROUP0_NR_IRQS) ? 1 : 0;
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mask = (offset == 1) ? BIT(gpio - GROUP0_NR_IRQS) :
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BIT(gpio);
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virq = irq_find_mapping(wg->chip.irq.domain, gpio);
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handle_nested_irq(virq);
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regmap_update_bits(wg->regmap, IRQ_STATUS_BASE + offset,
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mask, mask);
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}
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/* Next iteration */
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if (regmap_bulk_read(wg->regmap, IRQ_STATUS_BASE, p, 2)) {
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dev_err(wg->dev, "Failed to read irq status\n");
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break;
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}
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pending = (p[0] & GPIO_IRQ0_MASK) | ((p[1] & GPIO_IRQ1_MASK) << 7);
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}
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return IRQ_HANDLED;
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}
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static void wcove_gpio_dbg_show(struct seq_file *s,
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struct gpio_chip *chip)
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{
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unsigned int ctlo, ctli, irq_mask, irq_status;
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struct wcove_gpio *wg = gpiochip_get_data(chip);
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int gpio, offset, group, ret = 0;
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for (gpio = 0; gpio < WCOVE_GPIO_NUM; gpio++) {
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group = gpio < GROUP0_NR_IRQS ? 0 : 1;
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ret += regmap_read(wg->regmap, to_reg(gpio, CTRL_OUT), &ctlo);
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ret += regmap_read(wg->regmap, to_reg(gpio, CTRL_IN), &ctli);
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ret += regmap_read(wg->regmap, IRQ_MASK_BASE + group,
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&irq_mask);
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ret += regmap_read(wg->regmap, IRQ_STATUS_BASE + group,
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&irq_status);
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if (ret) {
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pr_err("Failed to read registers: ctrl out/in or irq status/mask\n");
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break;
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}
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offset = gpio % 8;
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seq_printf(s, " gpio-%-2d %s %s %s %s ctlo=%2x,%s %s\n",
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gpio, ctlo & CTLO_DIR_OUT ? "out" : "in ",
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ctli & 0x1 ? "hi" : "lo",
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ctli & CTLI_INTCNT_NE ? "fall" : " ",
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ctli & CTLI_INTCNT_PE ? "rise" : " ",
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ctlo,
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irq_mask & BIT(offset) ? "mask " : "unmask",
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irq_status & BIT(offset) ? "pending" : " ");
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}
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}
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static int wcove_gpio_probe(struct platform_device *pdev)
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{
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struct intel_soc_pmic *pmic;
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struct wcove_gpio *wg;
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int virq, ret, irq;
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struct device *dev;
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/*
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* This gpio platform device is created by a mfd device (see
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* drivers/mfd/intel_soc_pmic_bxtwc.c for details). Information
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* shared by all sub-devices created by the mfd device, the regmap
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* pointer for instance, is stored as driver data of the mfd device
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* driver.
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*/
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pmic = dev_get_drvdata(pdev->dev.parent);
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if (!pmic)
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return -ENODEV;
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irq = platform_get_irq(pdev, 0);
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if (irq < 0)
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return irq;
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dev = &pdev->dev;
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wg = devm_kzalloc(dev, sizeof(*wg), GFP_KERNEL);
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if (!wg)
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return -ENOMEM;
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wg->regmap_irq_chip = pmic->irq_chip_data;
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platform_set_drvdata(pdev, wg);
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mutex_init(&wg->buslock);
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wg->chip.label = KBUILD_MODNAME;
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wg->chip.direction_input = wcove_gpio_dir_in;
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wg->chip.direction_output = wcove_gpio_dir_out;
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wg->chip.get_direction = wcove_gpio_get_direction;
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wg->chip.get = wcove_gpio_get;
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wg->chip.set = wcove_gpio_set;
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wg->chip.set_config = wcove_gpio_set_config,
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wg->chip.base = -1;
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wg->chip.ngpio = WCOVE_VGPIO_NUM;
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wg->chip.can_sleep = true;
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wg->chip.parent = pdev->dev.parent;
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wg->chip.dbg_show = wcove_gpio_dbg_show;
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wg->dev = dev;
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wg->regmap = pmic->regmap;
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ret = devm_gpiochip_add_data(dev, &wg->chip, wg);
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if (ret) {
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dev_err(dev, "Failed to add gpiochip: %d\n", ret);
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return ret;
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}
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ret = gpiochip_irqchip_add_nested(&wg->chip, &wcove_irqchip, 0,
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handle_simple_irq, IRQ_TYPE_NONE);
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if (ret) {
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dev_err(dev, "Failed to add irqchip: %d\n", ret);
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return ret;
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}
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virq = regmap_irq_get_virq(wg->regmap_irq_chip, irq);
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if (virq < 0) {
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dev_err(dev, "Failed to get virq by irq %d\n", irq);
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return virq;
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}
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ret = devm_request_threaded_irq(dev, virq, NULL,
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wcove_gpio_irq_handler, IRQF_ONESHOT, pdev->name, wg);
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if (ret) {
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dev_err(dev, "Failed to request irq %d\n", virq);
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return ret;
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}
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gpiochip_set_nested_irqchip(&wg->chip, &wcove_irqchip, virq);
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/* Enable GPIO0 interrupts */
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ret = regmap_update_bits(wg->regmap, IRQ_MASK_BASE, GPIO_IRQ0_MASK,
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0x00);
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if (ret)
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return ret;
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/* Enable GPIO1 interrupts */
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ret = regmap_update_bits(wg->regmap, IRQ_MASK_BASE + 1, GPIO_IRQ1_MASK,
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0x00);
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if (ret)
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return ret;
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return 0;
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}
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/*
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* Whiskey Cove PMIC itself is a analog device(but with digital control
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* interface) providing power management support for other devices in
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* the accompanied SoC, so we have no .pm for Whiskey Cove GPIO driver.
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*/
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static struct platform_driver wcove_gpio_driver = {
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.driver = {
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|
.name = "bxt_wcove_gpio",
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|
},
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|
.probe = wcove_gpio_probe,
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|
};
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|
|
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module_platform_driver(wcove_gpio_driver);
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|
|
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MODULE_AUTHOR("Ajay Thomas <ajay.thomas.david.rajamanickam@intel.com>");
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MODULE_AUTHOR("Bin Gao <bin.gao@intel.com>");
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|
MODULE_DESCRIPTION("Intel Whiskey Cove GPIO Driver");
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|
MODULE_LICENSE("GPL v2");
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|
MODULE_ALIAS("platform:bxt_wcove_gpio");
|