183 lines
7.1 KiB
Plaintext
183 lines
7.1 KiB
Plaintext
* ARM System MMU Architecture Implementation
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ARM SoCs may contain an implementation of the ARM System Memory
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Management Unit Architecture, which can be used to provide 1 or 2 stages
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of address translation to bus masters external to the CPU.
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The SMMU may also raise interrupts in response to various fault
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conditions.
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** System MMU required properties:
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- compatible : Should be one of:
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"arm,smmu-v1"
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"arm,smmu-v2"
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"arm,mmu-400"
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"arm,mmu-401"
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"arm,mmu-500"
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"cavium,smmu-v2"
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"qcom,smmu-v2"
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depending on the particular implementation and/or the
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version of the architecture implemented.
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Qcom SoCs must contain, as below, SoC-specific compatibles
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along with "qcom,smmu-v2":
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"qcom,msm8996-smmu-v2", "qcom,smmu-v2",
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"qcom,sdm845-smmu-v2", "qcom,smmu-v2".
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Qcom SoCs implementing "arm,mmu-500" must also include,
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as below, SoC-specific compatibles:
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"qcom,sdm845-smmu-500", "arm,mmu-500"
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- reg : Base address and size of the SMMU.
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- #global-interrupts : The number of global interrupts exposed by the
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device.
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- interrupts : Interrupt list, with the first #global-irqs entries
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corresponding to the global interrupts and any
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following entries corresponding to context interrupts,
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specified in order of their indexing by the SMMU.
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For SMMUv2 implementations, there must be exactly one
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interrupt per context bank. In the case of a single,
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combined interrupt, it must be listed multiple times.
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- #iommu-cells : See Documentation/devicetree/bindings/iommu/iommu.txt
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for details. With a value of 1, each IOMMU specifier
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represents a distinct stream ID emitted by that device
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into the relevant SMMU.
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SMMUs with stream matching support and complex masters
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may use a value of 2, where the second cell of the
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IOMMU specifier represents an SMR mask to combine with
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the ID in the first cell. Care must be taken to ensure
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the set of matched IDs does not result in conflicts.
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** System MMU optional properties:
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- dma-coherent : Present if page table walks made by the SMMU are
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cache coherent with the CPU.
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NOTE: this only applies to the SMMU itself, not
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masters connected upstream of the SMMU.
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- calxeda,smmu-secure-config-access : Enable proper handling of buggy
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implementations that always use secure access to
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SMMU configuration registers. In this case non-secure
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aliases of secure registers have to be used during
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SMMU configuration.
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- stream-match-mask : For SMMUs supporting stream matching and using
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#iommu-cells = <1>, specifies a mask of bits to ignore
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when matching stream IDs (e.g. this may be programmed
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into the SMRn.MASK field of every stream match register
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used). For cases where it is desirable to ignore some
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portion of every Stream ID (e.g. for certain MMU-500
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configurations given globally unique input IDs). This
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property is not valid for SMMUs using stream indexing,
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or using stream matching with #iommu-cells = <2>, and
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may be ignored if present in such cases.
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- clock-names: List of the names of clocks input to the device. The
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required list depends on particular implementation and
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is as follows:
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- for "qcom,smmu-v2":
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- "bus": clock required for downstream bus access and
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for the smmu ptw,
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- "iface": clock required to access smmu's registers
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through the TCU's programming interface.
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- unspecified for other implementations.
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- clocks: Specifiers for all clocks listed in the clock-names property,
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as per generic clock bindings.
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- power-domains: Specifiers for power domains required to be powered on for
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the SMMU to operate, as per generic power domain bindings.
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** Deprecated properties:
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- mmu-masters (deprecated in favour of the generic "iommus" binding) :
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A list of phandles to device nodes representing bus
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masters for which the SMMU can provide a translation
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and their corresponding Stream IDs. Each device node
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linked from this list must have a "#stream-id-cells"
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property, indicating the number of Stream ID
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arguments associated with its phandle.
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** Examples:
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/* SMMU with stream matching or stream indexing */
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smmu1: iommu {
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compatible = "arm,smmu-v1";
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reg = <0xba5e0000 0x10000>;
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#global-interrupts = <2>;
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interrupts = <0 32 4>,
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<0 33 4>,
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<0 34 4>, /* This is the first context interrupt */
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<0 35 4>,
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<0 36 4>,
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<0 37 4>;
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#iommu-cells = <1>;
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};
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/* device with two stream IDs, 0 and 7 */
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master1 {
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iommus = <&smmu1 0>,
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<&smmu1 7>;
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};
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/* SMMU with stream matching */
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smmu2: iommu {
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...
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#iommu-cells = <2>;
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};
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/* device with stream IDs 0 and 7 */
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master2 {
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iommus = <&smmu2 0 0>,
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<&smmu2 7 0>;
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};
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/* device with stream IDs 1, 17, 33 and 49 */
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master3 {
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iommus = <&smmu2 1 0x30>;
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};
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/* ARM MMU-500 with 10-bit stream ID input configuration */
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smmu3: iommu {
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compatible = "arm,mmu-500", "arm,smmu-v2";
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...
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#iommu-cells = <1>;
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/* always ignore appended 5-bit TBU number */
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stream-match-mask = 0x7c00;
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};
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bus {
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/* bus whose child devices emit one unique 10-bit stream
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ID each, but may master through multiple SMMU TBUs */
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iommu-map = <0 &smmu3 0 0x400>;
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...
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};
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/* Qcom's arm,smmu-v2 implementation */
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smmu4: iommu@d00000 {
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compatible = "qcom,msm8996-smmu-v2", "qcom,smmu-v2";
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reg = <0xd00000 0x10000>;
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#global-interrupts = <1>;
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interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>;
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#iommu-cells = <1>;
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power-domains = <&mmcc MDSS_GDSC>;
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clocks = <&mmcc SMMU_MDP_AXI_CLK>,
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<&mmcc SMMU_MDP_AHB_CLK>;
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clock-names = "bus", "iface";
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};
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