59 lines
1.8 KiB
Plaintext
59 lines
1.8 KiB
Plaintext
Socionext UniPhier Regulator Controller
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This describes the devicetree bindings for regulator controller implemented
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on Socionext UniPhier SoCs.
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USB3 Controller
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---------------
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This regulator controls VBUS and belongs to USB3 glue layer. Before using
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the regulator, it is necessary to control the clocks and resets to enable
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this layer. These clocks and resets should be described in each property.
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Required properties:
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- compatible: Should be
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"socionext,uniphier-pro4-usb3-regulator" - for Pro4 SoC
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"socionext,uniphier-pro5-usb3-regulator" - for Pro5 SoC
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"socionext,uniphier-pxs2-usb3-regulator" - for PXs2 SoC
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"socionext,uniphier-ld20-usb3-regulator" - for LD20 SoC
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"socionext,uniphier-pxs3-usb3-regulator" - for PXs3 SoC
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- reg: Specifies offset and length of the register set for the device.
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- clocks: A list of phandles to the clock gate for USB3 glue layer.
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According to the clock-names, appropriate clocks are required.
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- clock-names: Should contain
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"gio", "link" - for Pro4 and Pro5 SoCs
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"link" - for others
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- resets: A list of phandles to the reset control for USB3 glue layer.
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According to the reset-names, appropriate resets are required.
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- reset-names: Should contain
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"gio", "link" - for Pro4 and Pro5 SoCs
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"link" - for others
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See Documentation/devicetree/bindings/regulator/regulator.txt
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for more details about the regulator properties.
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Example:
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usb-glue@65b00000 {
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compatible = "socionext,uniphier-ld20-dwc3-glue",
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"simple-mfd";
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0 0x65b00000 0x400>;
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usb_vbus0: regulators@100 {
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compatible = "socionext,uniphier-ld20-usb3-regulator";
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reg = <0x100 0x10>;
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clock-names = "link";
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clocks = <&sys_clk 14>;
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reset-names = "link";
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resets = <&sys_rst 14>;
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};
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phy {
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...
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phy-supply = <&usb_vbus0>;
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};
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...
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};
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