246 lines
6.5 KiB
C
246 lines
6.5 KiB
C
/*
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* Driver for Feature Integration Technology Inc. (aka Fintek) LPC CIR
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*
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* Copyright (C) 2011 Jarod Wilson <jarod@redhat.com>
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*
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* Special thanks to Fintek for providing hardware and spec sheets.
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* This driver is based upon the nuvoton, ite and ene drivers for
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* similar hardware.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of the
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* License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful, but
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* WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307
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* USA
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*/
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#include <linux/spinlock.h>
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#include <linux/ioctl.h>
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/* platform driver name to register */
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#define FINTEK_DRIVER_NAME "fintek-cir"
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#define FINTEK_DESCRIPTION "Fintek LPC SuperIO Consumer IR Transceiver"
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#define VENDOR_ID_FINTEK 0x1934
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/* debugging module parameter */
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static int debug;
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#define fit_pr(level, text, ...) \
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printk(level KBUILD_MODNAME ": " text, ## __VA_ARGS__)
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#define fit_dbg(text, ...) \
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if (debug) \
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printk(KERN_DEBUG \
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KBUILD_MODNAME ": " text "\n" , ## __VA_ARGS__)
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#define fit_dbg_verbose(text, ...) \
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if (debug > 1) \
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printk(KERN_DEBUG \
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KBUILD_MODNAME ": " text "\n" , ## __VA_ARGS__)
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#define fit_dbg_wake(text, ...) \
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if (debug > 2) \
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printk(KERN_DEBUG \
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KBUILD_MODNAME ": " text "\n" , ## __VA_ARGS__)
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#define TX_BUF_LEN 256
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#define RX_BUF_LEN 32
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struct fintek_dev {
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struct pnp_dev *pdev;
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struct rc_dev *rdev;
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spinlock_t fintek_lock;
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/* for rx */
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u8 buf[RX_BUF_LEN];
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unsigned int pkts;
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struct {
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spinlock_t lock;
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u8 buf[TX_BUF_LEN];
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unsigned int buf_count;
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unsigned int cur_buf_num;
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wait_queue_head_t queue;
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} tx;
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/* Config register index/data port pair */
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u32 cr_ip;
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u32 cr_dp;
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/* hardware I/O settings */
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unsigned long cir_addr;
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int cir_irq;
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int cir_port_len;
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/* hardware id */
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u8 chip_major;
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u8 chip_minor;
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u16 chip_vendor;
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u8 logical_dev_cir;
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/* hardware features */
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bool hw_learning_capable;
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bool hw_tx_capable;
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/* rx settings */
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bool learning_enabled;
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bool carrier_detect_enabled;
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enum {
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CMD_HEADER = 0,
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SUBCMD,
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CMD_DATA,
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PARSE_IRDATA,
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} parser_state;
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u8 cmd, rem;
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/* carrier period = 1 / frequency */
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u32 carrier;
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};
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/* buffer packet constants, largely identical to mceusb.c */
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#define BUF_PULSE_BIT 0x80
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#define BUF_LEN_MASK 0x1f
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#define BUF_SAMPLE_MASK 0x7f
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#define BUF_COMMAND_HEADER 0x9f
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#define BUF_COMMAND_MASK 0xe0
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#define BUF_COMMAND_NULL 0x00
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#define BUF_HW_CMD_HEADER 0xff
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#define BUF_CMD_G_REVISION 0x0b
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#define BUF_CMD_S_CARRIER 0x06
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#define BUF_CMD_S_TIMEOUT 0x0c
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#define BUF_CMD_SIG_END 0x01
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#define BUF_CMD_S_TXMASK 0x08
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#define BUF_CMD_S_RXSENSOR 0x14
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#define BUF_RSP_PULSE_COUNT 0x15
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#define CIR_SAMPLE_PERIOD 50
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/*
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* Configuration Register:
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* Index Port
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* Data Port
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*/
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#define CR_INDEX_PORT 0x2e
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#define CR_DATA_PORT 0x2f
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/* Possible alternate values, depends on how the chip is wired */
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#define CR_INDEX_PORT2 0x4e
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#define CR_DATA_PORT2 0x4f
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/*
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* GCR_CONFIG_PORT_SEL bit 4 specifies which Index Port value is
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* active. 1 = 0x4e, 0 = 0x2e
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*/
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#define PORT_SEL_PORT_4E_EN 0x10
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/* Extended Function Mode enable/disable magic values */
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#define CONFIG_REG_ENABLE 0x87
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#define CONFIG_REG_DISABLE 0xaa
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/* Chip IDs found in CR_CHIP_ID_{HI,LO} */
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#define CHIP_ID_HIGH_F71809U 0x04
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#define CHIP_ID_LOW_F71809U 0x08
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/*
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* Global control regs we need to care about:
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* Global Control def.
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* Register name addr val. */
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#define GCR_SOFTWARE_RESET 0x02 /* 0x00 */
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#define GCR_LOGICAL_DEV_NO 0x07 /* 0x00 */
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#define GCR_CHIP_ID_HI 0x20 /* 0x04 */
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#define GCR_CHIP_ID_LO 0x21 /* 0x08 */
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#define GCR_VENDOR_ID_HI 0x23 /* 0x19 */
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#define GCR_VENDOR_ID_LO 0x24 /* 0x34 */
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#define GCR_CONFIG_PORT_SEL 0x25 /* 0x01 */
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#define GCR_KBMOUSE_WAKEUP 0x27
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#define LOGICAL_DEV_DISABLE 0x00
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#define LOGICAL_DEV_ENABLE 0x01
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/* Logical device number of the CIR function */
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#define LOGICAL_DEV_CIR_REV1 0x05
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#define LOGICAL_DEV_CIR_REV2 0x08
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/* CIR Logical Device (LDN 0x08) config registers */
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#define CIR_CR_COMMAND_INDEX 0x04
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#define CIR_CR_IRCS 0x05 /* Before host writes command to IR, host
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must set to 1. When host finshes write
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command to IR, host must clear to 0. */
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#define CIR_CR_COMMAND_DATA 0x06 /* Host read or write comand data */
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#define CIR_CR_CLASS 0x07 /* 0xff = rx-only, 0x66 = rx + 2 tx,
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0x33 = rx + 1 tx */
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#define CIR_CR_DEV_EN 0x30 /* bit0 = 1 enables CIR */
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#define CIR_CR_BASE_ADDR_HI 0x60 /* MSB of CIR IO base addr */
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#define CIR_CR_BASE_ADDR_LO 0x61 /* LSB of CIR IO base addr */
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#define CIR_CR_IRQ_SEL 0x70 /* bits3-0 store CIR IRQ */
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#define CIR_CR_PSOUT_STATUS 0xf1
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#define CIR_CR_WAKE_KEY3_ADDR 0xf8
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#define CIR_CR_WAKE_KEY3_CODE 0xf9
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#define CIR_CR_WAKE_KEY3_DC 0xfa
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#define CIR_CR_WAKE_CONTROL 0xfb
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#define CIR_CR_WAKE_KEY12_ADDR 0xfc
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#define CIR_CR_WAKE_KEY4_ADDR 0xfd
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#define CIR_CR_WAKE_KEY5_ADDR 0xfe
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#define CLASS_RX_ONLY 0xff
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#define CLASS_RX_2TX 0x66
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#define CLASS_RX_1TX 0x33
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/* CIR device registers */
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#define CIR_STATUS 0x00
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#define CIR_RX_DATA 0x01
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#define CIR_TX_CONTROL 0x02
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#define CIR_TX_DATA 0x03
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#define CIR_CONTROL 0x04
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/* Bits to enable CIR wake */
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#define LOGICAL_DEV_ACPI 0x01
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#define LDEV_ACPI_WAKE_EN_REG 0xe8
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#define ACPI_WAKE_EN_CIR_BIT 0x04
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#define LDEV_ACPI_PME_EN_REG 0xf0
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#define LDEV_ACPI_PME_CLR_REG 0xf1
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#define ACPI_PME_CIR_BIT 0x02
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#define LDEV_ACPI_STATE_REG 0xf4
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#define ACPI_STATE_CIR_BIT 0x20
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/*
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* CIR status register (0x00):
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* 7 - CIR_IRQ_EN (1 = enable CIR IRQ, 0 = disable)
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* 3 - TX_FINISH (1 when TX finished, write 1 to clear)
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* 2 - TX_UNDERRUN (1 on TX underrun, write 1 to clear)
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* 1 - RX_TIMEOUT (1 on RX timeout, write 1 to clear)
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* 0 - RX_RECEIVE (1 on RX receive, write 1 to clear)
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*/
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#define CIR_STATUS_IRQ_EN 0x80
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#define CIR_STATUS_TX_FINISH 0x08
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#define CIR_STATUS_TX_UNDERRUN 0x04
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#define CIR_STATUS_RX_TIMEOUT 0x02
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#define CIR_STATUS_RX_RECEIVE 0x01
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#define CIR_STATUS_IRQ_MASK 0x0f
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/*
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* CIR TX control register (0x02):
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* 7 - TX_START (1 to indicate TX start, auto-cleared when done)
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* 6 - TX_END (1 to indicate TX data written to TX fifo)
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*/
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#define CIR_TX_CONTROL_TX_START 0x80
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#define CIR_TX_CONTROL_TX_END 0x40
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