167 lines
4.0 KiB
Plaintext
167 lines
4.0 KiB
Plaintext
Build Framework
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===============
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The perf build framework was adopted from the kernel build system, hence the
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idea and the way how objects are built is the same.
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Basically the user provides set of 'Build' files that list objects and
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directories to nest for specific target to be build.
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Unlike the kernel we don't have a single build object 'obj-y' list that where
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we setup source objects, but we support more. This allows one 'Build' file to
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carry a sources list for multiple build objects.
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Build framework makefiles
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-------------------------
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The build framework consists of 2 Makefiles:
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Build.include
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Makefile.build
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While the 'Build.include' file contains just some generic definitions, the
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'Makefile.build' file is the makefile used from the outside. It's
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interface/usage is following:
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$ make -f tools/build/Makefile.build srctree=$(KSRC) dir=$(DIR) obj=$(OBJECT)
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where:
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KSRC - is the path to kernel sources
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DIR - is the path to the project to be built
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OBJECT - is the name of the build object
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When succefully finished the $(DIR) directory contains the final object file
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called $(OBJECT)-in.o:
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$ ls $(DIR)/$(OBJECT)-in.o
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which includes all compiled sources described in 'Build' makefiles.
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Build makefiles
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---------------
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The user supplies 'Build' makefiles that contains a objects list, and connects
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the build to nested directories.
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Assume we have the following project structure:
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ex/a.c
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/b.c
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/c.c
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/d.c
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/arch/e.c
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/arch/f.c
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Out of which you build the 'ex' binary ' and the 'libex.a' library:
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'ex' - consists of 'a.o', 'b.o' and libex.a
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'libex.a' - consists of 'c.o', 'd.o', 'e.o' and 'f.o'
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The build framework does not create the 'ex' and 'libex.a' binaries for you, it
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only prepares proper objects to be compiled and grouped together.
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To follow the above example, the user provides following 'Build' files:
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ex/Build:
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ex-y += a.o
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ex-y += b.o
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ex-y += b.o # duplicates in the lists are allowed
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libex-y += c.o
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libex-y += d.o
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libex-y += arch/
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ex/arch/Build:
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libex-y += e.o
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libex-y += f.o
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and runs:
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$ make -f tools/build/Makefile.build dir=. obj=ex
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$ make -f tools/build/Makefile.build dir=. obj=libex
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which creates the following objects:
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ex/ex-in.o
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ex/libex-in.o
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that contain request objects names in Build files.
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It's only a matter of 2 single commands to create the final binaries:
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$ ar rcs libex.a libex-in.o
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$ gcc -o ex ex-in.o libex.a
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You can check the 'ex' example in 'tools/build/tests/ex' for more details.
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Makefile.include
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----------------
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The tools/build/Makefile.include makefile could be included
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via user makefiles to get usefull definitions.
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It defines following interface:
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- build macro definition:
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build := -f $(srctree)/tools/build/Makefile.build dir=. obj
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to make it easier to invoke build like:
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make $(build)=ex
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Fixdep
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------
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It is necessary to build the fixdep helper before invoking the build.
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The Makefile.include file adds the fixdep target, that could be
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invoked by the user.
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Rules
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-----
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The build framework provides standard compilation rules to handle .S and .c
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compilation.
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It's possible to include special rule if needed (like we do for flex or bison
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code generation).
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CFLAGS
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------
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It's possible to alter the standard object C flags in the following way:
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CFLAGS_perf.o += '...' - alters CFLAGS for perf.o object
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CFLAGS_gtk += '...' - alters CFLAGS for gtk build object
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This C flags changes has the scope of the Build makefile they are defined in.
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Dependencies
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------------
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For each built object file 'a.o' the '.a.cmd' is created and holds:
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- Command line used to built that object
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(for each object)
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- Dependency rules generated by 'gcc -Wp,-MD,...'
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(for compiled object)
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All existing '.cmd' files are included in the Build process to follow properly
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the dependencies and trigger a rebuild when necessary.
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Single rules
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------------
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It's possible to build single object file by choice, like:
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$ make util/map.o # objects
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$ make util/map.i # preprocessor
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$ make util/map.s # assembly
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