516 lines
14 KiB
C
516 lines
14 KiB
C
/*
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* linux/arch/alpha/kernel/core_lca.c
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*
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* Written by David Mosberger (davidm@cs.arizona.edu) with some code
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* taken from Dave Rusling's (david.rusling@reo.mts.dec.com) 32-bit
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* bios code.
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*
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* Code common to all LCA core logic chips.
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*/
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#define __EXTERN_INLINE inline
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#include <asm/io.h>
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#include <asm/core_lca.h>
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#undef __EXTERN_INLINE
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#include <linux/types.h>
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#include <linux/pci.h>
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#include <linux/init.h>
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#include <linux/tty.h>
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#include <asm/ptrace.h>
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#include <asm/irq_regs.h>
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#include <asm/smp.h>
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#include "proto.h"
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#include "pci_impl.h"
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/*
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* BIOS32-style PCI interface:
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*/
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/*
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* Machine check reasons. Defined according to PALcode sources
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* (osf.h and platform.h).
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*/
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#define MCHK_K_TPERR 0x0080
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#define MCHK_K_TCPERR 0x0082
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#define MCHK_K_HERR 0x0084
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#define MCHK_K_ECC_C 0x0086
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#define MCHK_K_ECC_NC 0x0088
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#define MCHK_K_UNKNOWN 0x008A
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#define MCHK_K_CACKSOFT 0x008C
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#define MCHK_K_BUGCHECK 0x008E
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#define MCHK_K_OS_BUGCHECK 0x0090
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#define MCHK_K_DCPERR 0x0092
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#define MCHK_K_ICPERR 0x0094
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/*
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* Platform-specific machine-check reasons:
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*/
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#define MCHK_K_SIO_SERR 0x204 /* all platforms so far */
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#define MCHK_K_SIO_IOCHK 0x206 /* all platforms so far */
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#define MCHK_K_DCSR 0x208 /* all but Noname */
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/*
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* Given a bus, device, and function number, compute resulting
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* configuration space address and setup the LCA_IOC_CONF register
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* accordingly. It is therefore not safe to have concurrent
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* invocations to configuration space access routines, but there
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* really shouldn't be any need for this.
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*
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* Type 0:
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*
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* 3 3|3 3 2 2|2 2 2 2|2 2 2 2|1 1 1 1|1 1 1 1|1 1
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* 3 2|1 0 9 8|7 6 5 4|3 2 1 0|9 8 7 6|5 4 3 2|1 0 9 8|7 6 5 4|3 2 1 0
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* +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
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* | | | | | | | | | | | | | | | | | | | | | | | |F|F|F|R|R|R|R|R|R|0|0|
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* +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
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*
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* 31:11 Device select bit.
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* 10:8 Function number
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* 7:2 Register number
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*
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* Type 1:
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*
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* 3 3|3 3 2 2|2 2 2 2|2 2 2 2|1 1 1 1|1 1 1 1|1 1
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* 3 2|1 0 9 8|7 6 5 4|3 2 1 0|9 8 7 6|5 4 3 2|1 0 9 8|7 6 5 4|3 2 1 0
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* +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
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* | | | | | | | | | | |B|B|B|B|B|B|B|B|D|D|D|D|D|F|F|F|R|R|R|R|R|R|0|1|
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* +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
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*
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* 31:24 reserved
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* 23:16 bus number (8 bits = 128 possible buses)
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* 15:11 Device number (5 bits)
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* 10:8 function number
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* 7:2 register number
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*
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* Notes:
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* The function number selects which function of a multi-function device
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* (e.g., SCSI and Ethernet).
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*
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* The register selects a DWORD (32 bit) register offset. Hence it
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* doesn't get shifted by 2 bits as we want to "drop" the bottom two
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* bits.
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*/
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static int
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mk_conf_addr(struct pci_bus *pbus, unsigned int device_fn, int where,
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unsigned long *pci_addr)
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{
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unsigned long addr;
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u8 bus = pbus->number;
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if (bus == 0) {
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int device = device_fn >> 3;
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int func = device_fn & 0x7;
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/* Type 0 configuration cycle. */
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if (device > 12) {
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return -1;
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}
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*(vulp)LCA_IOC_CONF = 0;
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addr = (1 << (11 + device)) | (func << 8) | where;
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} else {
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/* Type 1 configuration cycle. */
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*(vulp)LCA_IOC_CONF = 1;
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addr = (bus << 16) | (device_fn << 8) | where;
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}
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*pci_addr = addr;
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return 0;
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}
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static unsigned int
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conf_read(unsigned long addr)
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{
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unsigned long flags, code, stat0;
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unsigned int value;
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local_irq_save(flags);
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/* Reset status register to avoid losing errors. */
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stat0 = *(vulp)LCA_IOC_STAT0;
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*(vulp)LCA_IOC_STAT0 = stat0;
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mb();
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/* Access configuration space. */
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value = *(vuip)addr;
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draina();
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stat0 = *(vulp)LCA_IOC_STAT0;
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if (stat0 & LCA_IOC_STAT0_ERR) {
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code = ((stat0 >> LCA_IOC_STAT0_CODE_SHIFT)
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& LCA_IOC_STAT0_CODE_MASK);
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if (code != 1) {
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printk("lca.c:conf_read: got stat0=%lx\n", stat0);
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}
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/* Reset error status. */
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*(vulp)LCA_IOC_STAT0 = stat0;
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mb();
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/* Reset machine check. */
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wrmces(0x7);
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value = 0xffffffff;
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}
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local_irq_restore(flags);
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return value;
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}
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static void
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conf_write(unsigned long addr, unsigned int value)
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{
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unsigned long flags, code, stat0;
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local_irq_save(flags); /* avoid getting hit by machine check */
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/* Reset status register to avoid losing errors. */
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stat0 = *(vulp)LCA_IOC_STAT0;
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*(vulp)LCA_IOC_STAT0 = stat0;
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mb();
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/* Access configuration space. */
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*(vuip)addr = value;
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draina();
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stat0 = *(vulp)LCA_IOC_STAT0;
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if (stat0 & LCA_IOC_STAT0_ERR) {
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code = ((stat0 >> LCA_IOC_STAT0_CODE_SHIFT)
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& LCA_IOC_STAT0_CODE_MASK);
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if (code != 1) {
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printk("lca.c:conf_write: got stat0=%lx\n", stat0);
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}
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/* Reset error status. */
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*(vulp)LCA_IOC_STAT0 = stat0;
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mb();
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/* Reset machine check. */
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wrmces(0x7);
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}
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local_irq_restore(flags);
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}
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static int
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lca_read_config(struct pci_bus *bus, unsigned int devfn, int where,
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int size, u32 *value)
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{
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unsigned long addr, pci_addr;
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long mask;
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int shift;
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if (mk_conf_addr(bus, devfn, where, &pci_addr))
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return PCIBIOS_DEVICE_NOT_FOUND;
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shift = (where & 3) * 8;
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mask = (size - 1) * 8;
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addr = (pci_addr << 5) + mask + LCA_CONF;
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*value = conf_read(addr) >> (shift);
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return PCIBIOS_SUCCESSFUL;
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}
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static int
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lca_write_config(struct pci_bus *bus, unsigned int devfn, int where, int size,
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u32 value)
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{
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unsigned long addr, pci_addr;
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long mask;
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if (mk_conf_addr(bus, devfn, where, &pci_addr))
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return PCIBIOS_DEVICE_NOT_FOUND;
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mask = (size - 1) * 8;
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addr = (pci_addr << 5) + mask + LCA_CONF;
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conf_write(addr, value << ((where & 3) * 8));
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return PCIBIOS_SUCCESSFUL;
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}
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struct pci_ops lca_pci_ops =
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{
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.read = lca_read_config,
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.write = lca_write_config,
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};
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void
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lca_pci_tbi(struct pci_controller *hose, dma_addr_t start, dma_addr_t end)
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{
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wmb();
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*(vulp)LCA_IOC_TBIA = 0;
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mb();
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}
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void __init
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lca_init_arch(void)
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{
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struct pci_controller *hose;
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/*
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* Create our single hose.
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*/
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pci_isa_hose = hose = alloc_pci_controller();
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hose->io_space = &ioport_resource;
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hose->mem_space = &iomem_resource;
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hose->index = 0;
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hose->sparse_mem_base = LCA_SPARSE_MEM - IDENT_ADDR;
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hose->dense_mem_base = LCA_DENSE_MEM - IDENT_ADDR;
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hose->sparse_io_base = LCA_IO - IDENT_ADDR;
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hose->dense_io_base = 0;
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/*
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* Set up the PCI to main memory translation windows.
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*
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* Mimic the SRM settings for the direct-map window.
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* Window 0 is scatter-gather 8MB at 8MB (for isa).
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* Window 1 is direct access 1GB at 1GB.
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*
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* Note that we do not try to save any of the DMA window CSRs
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* before setting them, since we cannot read those CSRs on LCA.
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*/
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hose->sg_isa = iommu_arena_new(hose, 0x00800000, 0x00800000, 0);
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hose->sg_pci = NULL;
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__direct_map_base = 0x40000000;
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__direct_map_size = 0x40000000;
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*(vulp)LCA_IOC_W_BASE0 = hose->sg_isa->dma_base | (3UL << 32);
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*(vulp)LCA_IOC_W_MASK0 = (hose->sg_isa->size - 1) & 0xfff00000;
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*(vulp)LCA_IOC_T_BASE0 = virt_to_phys(hose->sg_isa->ptes);
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*(vulp)LCA_IOC_W_BASE1 = __direct_map_base | (2UL << 32);
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*(vulp)LCA_IOC_W_MASK1 = (__direct_map_size - 1) & 0xfff00000;
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*(vulp)LCA_IOC_T_BASE1 = 0;
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*(vulp)LCA_IOC_TB_ENA = 0x80;
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lca_pci_tbi(hose, 0, -1);
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/*
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* Disable PCI parity for now. The NCR53c810 chip has
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* troubles meeting the PCI spec which results in
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* data parity errors.
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*/
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*(vulp)LCA_IOC_PAR_DIS = 1UL<<5;
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/*
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* Finally, set up for restoring the correct HAE if using SRM.
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* Again, since we cannot read many of the CSRs on the LCA,
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* one of which happens to be the HAE, we save the value that
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* the SRM will expect...
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*/
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if (alpha_using_srm)
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srm_hae = 0x80000000UL;
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}
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/*
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* Constants used during machine-check handling. I suppose these
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* could be moved into lca.h but I don't see much reason why anybody
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* else would want to use them.
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*/
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#define ESR_EAV (1UL<< 0) /* error address valid */
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#define ESR_CEE (1UL<< 1) /* correctable error */
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#define ESR_UEE (1UL<< 2) /* uncorrectable error */
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#define ESR_WRE (1UL<< 3) /* write-error */
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#define ESR_SOR (1UL<< 4) /* error source */
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#define ESR_CTE (1UL<< 7) /* cache-tag error */
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#define ESR_MSE (1UL<< 9) /* multiple soft errors */
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#define ESR_MHE (1UL<<10) /* multiple hard errors */
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#define ESR_NXM (1UL<<12) /* non-existent memory */
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#define IOC_ERR ( 1<<4) /* ioc logs an error */
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#define IOC_CMD_SHIFT 0
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#define IOC_CMD (0xf<<IOC_CMD_SHIFT)
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#define IOC_CODE_SHIFT 8
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#define IOC_CODE (0xf<<IOC_CODE_SHIFT)
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#define IOC_LOST ( 1<<5)
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#define IOC_P_NBR ((__u32) ~((1<<13) - 1))
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static void
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mem_error(unsigned long esr, unsigned long ear)
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{
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printk(" %s %s error to %s occurred at address %x\n",
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((esr & ESR_CEE) ? "Correctable" :
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(esr & ESR_UEE) ? "Uncorrectable" : "A"),
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(esr & ESR_WRE) ? "write" : "read",
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(esr & ESR_SOR) ? "memory" : "b-cache",
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(unsigned) (ear & 0x1ffffff8));
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if (esr & ESR_CTE) {
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printk(" A b-cache tag parity error was detected.\n");
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}
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if (esr & ESR_MSE) {
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printk(" Several other correctable errors occurred.\n");
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}
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if (esr & ESR_MHE) {
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printk(" Several other uncorrectable errors occurred.\n");
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}
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if (esr & ESR_NXM) {
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printk(" Attempted to access non-existent memory.\n");
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}
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}
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static void
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ioc_error(__u32 stat0, __u32 stat1)
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{
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static const char * const pci_cmd[] = {
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"Interrupt Acknowledge", "Special", "I/O Read", "I/O Write",
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"Rsvd 1", "Rsvd 2", "Memory Read", "Memory Write", "Rsvd3",
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"Rsvd4", "Configuration Read", "Configuration Write",
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"Memory Read Multiple", "Dual Address", "Memory Read Line",
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"Memory Write and Invalidate"
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};
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static const char * const err_name[] = {
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"exceeded retry limit", "no device", "bad data parity",
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"target abort", "bad address parity", "page table read error",
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"invalid page", "data error"
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};
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unsigned code = (stat0 & IOC_CODE) >> IOC_CODE_SHIFT;
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unsigned cmd = (stat0 & IOC_CMD) >> IOC_CMD_SHIFT;
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printk(" %s initiated PCI %s cycle to address %x"
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" failed due to %s.\n",
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code > 3 ? "PCI" : "CPU", pci_cmd[cmd], stat1, err_name[code]);
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if (code == 5 || code == 6) {
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printk(" (Error occurred at PCI memory address %x.)\n",
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(stat0 & ~IOC_P_NBR));
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}
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if (stat0 & IOC_LOST) {
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printk(" Other PCI errors occurred simultaneously.\n");
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}
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}
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void
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lca_machine_check(unsigned long vector, unsigned long la_ptr)
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{
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const char * reason;
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union el_lca el;
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el.c = (struct el_common *) la_ptr;
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wrmces(rdmces()); /* reset machine check pending flag */
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printk(KERN_CRIT "LCA machine check: vector=%#lx pc=%#lx code=%#x\n",
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vector, get_irq_regs()->pc, (unsigned int) el.c->code);
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/*
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* The first quadword after the common header always seems to
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* be the machine check reason---don't know why this isn't
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* part of the common header instead. In the case of a long
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* logout frame, the upper 32 bits is the machine check
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* revision level, which we ignore for now.
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*/
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switch ((unsigned int) el.c->code) {
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case MCHK_K_TPERR: reason = "tag parity error"; break;
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case MCHK_K_TCPERR: reason = "tag control parity error"; break;
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case MCHK_K_HERR: reason = "access to non-existent memory"; break;
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case MCHK_K_ECC_C: reason = "correctable ECC error"; break;
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case MCHK_K_ECC_NC: reason = "non-correctable ECC error"; break;
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case MCHK_K_CACKSOFT: reason = "MCHK_K_CACKSOFT"; break;
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case MCHK_K_BUGCHECK: reason = "illegal exception in PAL mode"; break;
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case MCHK_K_OS_BUGCHECK: reason = "callsys in kernel mode"; break;
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case MCHK_K_DCPERR: reason = "d-cache parity error"; break;
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case MCHK_K_ICPERR: reason = "i-cache parity error"; break;
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case MCHK_K_SIO_SERR: reason = "SIO SERR occurred on PCI bus"; break;
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case MCHK_K_SIO_IOCHK: reason = "SIO IOCHK occurred on ISA bus"; break;
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case MCHK_K_DCSR: reason = "MCHK_K_DCSR"; break;
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case MCHK_K_UNKNOWN:
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default: reason = "unknown"; break;
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}
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switch (el.c->size) {
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case sizeof(struct el_lca_mcheck_short):
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printk(KERN_CRIT
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" Reason: %s (short frame%s, dc_stat=%#lx):\n",
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reason, el.c->retry ? ", retryable" : "",
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el.s->dc_stat);
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if (el.s->esr & ESR_EAV) {
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mem_error(el.s->esr, el.s->ear);
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}
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if (el.s->ioc_stat0 & IOC_ERR) {
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ioc_error(el.s->ioc_stat0, el.s->ioc_stat1);
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}
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break;
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case sizeof(struct el_lca_mcheck_long):
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printk(KERN_CRIT " Reason: %s (long frame%s):\n",
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reason, el.c->retry ? ", retryable" : "");
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printk(KERN_CRIT
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" reason: %#lx exc_addr: %#lx dc_stat: %#lx\n",
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el.l->pt[0], el.l->exc_addr, el.l->dc_stat);
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printk(KERN_CRIT " car: %#lx\n", el.l->car);
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if (el.l->esr & ESR_EAV) {
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mem_error(el.l->esr, el.l->ear);
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}
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if (el.l->ioc_stat0 & IOC_ERR) {
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ioc_error(el.l->ioc_stat0, el.l->ioc_stat1);
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}
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break;
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default:
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printk(KERN_CRIT " Unknown errorlog size %d\n", el.c->size);
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}
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/* Dump the logout area to give all info. */
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#ifdef CONFIG_VERBOSE_MCHECK
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if (alpha_verbose_mcheck > 1) {
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unsigned long * ptr = (unsigned long *) la_ptr;
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long i;
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for (i = 0; i < el.c->size / sizeof(long); i += 2) {
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printk(KERN_CRIT " +%8lx %016lx %016lx\n",
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i*sizeof(long), ptr[i], ptr[i+1]);
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}
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}
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#endif /* CONFIG_VERBOSE_MCHECK */
|
||
}
|
||
|
||
/*
|
||
* The following routines are needed to support the SPEED changing
|
||
* necessary to successfully manage the thermal problem on the AlphaBook1.
|
||
*/
|
||
|
||
void
|
||
lca_clock_print(void)
|
||
{
|
||
long pmr_reg;
|
||
|
||
pmr_reg = LCA_READ_PMR;
|
||
|
||
printk("Status of clock control:\n");
|
||
printk("\tPrimary clock divisor\t0x%lx\n", LCA_GET_PRIMARY(pmr_reg));
|
||
printk("\tOverride clock divisor\t0x%lx\n", LCA_GET_OVERRIDE(pmr_reg));
|
||
printk("\tInterrupt override is %s\n",
|
||
(pmr_reg & LCA_PMR_INTO) ? "on" : "off");
|
||
printk("\tDMA override is %s\n",
|
||
(pmr_reg & LCA_PMR_DMAO) ? "on" : "off");
|
||
|
||
}
|
||
|
||
int
|
||
lca_get_clock(void)
|
||
{
|
||
long pmr_reg;
|
||
|
||
pmr_reg = LCA_READ_PMR;
|
||
return(LCA_GET_PRIMARY(pmr_reg));
|
||
|
||
}
|
||
|
||
void
|
||
lca_clock_fiddle(int divisor)
|
||
{
|
||
long pmr_reg;
|
||
|
||
pmr_reg = LCA_READ_PMR;
|
||
LCA_SET_PRIMARY_CLOCK(pmr_reg, divisor);
|
||
/* lca_norm_clock = divisor; */
|
||
LCA_WRITE_PMR(pmr_reg);
|
||
mb();
|
||
}
|