384 lines
20 KiB
C
384 lines
20 KiB
C
/*
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* DO NOT EDIT THIS FILE
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* This file is under version control at
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* svn://sources.blackfin.uclinux.org/toolchain/trunk/proc-defs/header-frags/
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* and can be replaced with that version at any time
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* DO NOT EDIT THIS FILE
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*
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* Copyright 2004-2011 Analog Devices Inc.
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* Licensed under the Clear BSD license.
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*/
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/* This file should be up to date with:
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* - Revision G, 05/23/2011; ADSP-BF531/BF532/BF533 Blackfin Processor Anomaly List
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*/
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#ifndef _MACH_ANOMALY_H_
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#define _MACH_ANOMALY_H_
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/* We do not support 0.1 or 0.2 silicon - sorry */
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#if __SILICON_REVISION__ < 3
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# error will not work on BF533 silicon version 0.0, 0.1, or 0.2
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#endif
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#if defined(__ADSPBF531__)
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# define ANOMALY_BF531 1
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#else
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# define ANOMALY_BF531 0
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#endif
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#if defined(__ADSPBF532__)
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# define ANOMALY_BF532 1
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#else
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# define ANOMALY_BF532 0
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#endif
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#if defined(__ADSPBF533__)
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# define ANOMALY_BF533 1
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#else
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# define ANOMALY_BF533 0
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#endif
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/* Multi-Issue Instruction with dsp32shiftimm in slot1 and P-reg Store in slot2 Not Supported */
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#define ANOMALY_05000074 (1)
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/* UART Line Status Register (UART_LSR) Bits Are Not Updated at the Same Time */
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#define ANOMALY_05000099 (__SILICON_REVISION__ < 5)
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/* Watchpoint Status Register (WPSTAT) Bits Are Set on Every Corresponding Match */
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#define ANOMALY_05000105 (__SILICON_REVISION__ > 2)
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/* DMA_RUN Bit Is Not Valid after a Peripheral Receive Channel DMA Stops */
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#define ANOMALY_05000119 (1)
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/* Rx.H Cannot Be Used to Access 16-bit System MMR Registers */
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#define ANOMALY_05000122 (1)
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/* Instruction DMA Can Cause Data Cache Fills to Fail (Boot Implications) */
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#define ANOMALY_05000158 (__SILICON_REVISION__ < 5)
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/* PPI Data Lengths between 8 and 16 Do Not Zero Out Upper Bits */
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#define ANOMALY_05000166 (1)
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/* Turning SPORTs on while External Frame Sync Is Active May Corrupt Data */
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#define ANOMALY_05000167 (1)
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/* PPI_COUNT Cannot Be Programmed to 0 in General Purpose TX or RX Modes */
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#define ANOMALY_05000179 (__SILICON_REVISION__ < 5)
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/* PPI_DELAY Not Functional in PPI Modes with 0 Frame Syncs */
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#define ANOMALY_05000180 (1)
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/* Timer Pin Limitations for PPI TX Modes with External Frame Syncs */
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#define ANOMALY_05000183 (__SILICON_REVISION__ < 4)
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/* False Protection Exceptions when Speculative Fetch Is Cancelled */
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#define ANOMALY_05000189 (__SILICON_REVISION__ < 4)
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/* False I/O Pin Interrupts on Edge-Sensitive Inputs When Polarity Setting Is Changed */
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#define ANOMALY_05000193 (__SILICON_REVISION__ < 4)
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/* Restarting SPORT in Specific Modes May Cause Data Corruption */
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#define ANOMALY_05000194 (__SILICON_REVISION__ < 4)
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/* Failing MMR Accesses when Preceding Memory Read Stalls */
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#define ANOMALY_05000198 (__SILICON_REVISION__ < 5)
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/* Current DMA Address Shows Wrong Value During Carry Fix */
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#define ANOMALY_05000199 (__SILICON_REVISION__ < 4)
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/* SPORT TFS and DT Are Incorrectly Driven During Inactive Channels in Certain Conditions */
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#define ANOMALY_05000200 (__SILICON_REVISION__ == 3 || __SILICON_REVISION__ == 4)
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/* Receive Frame Sync Not Ignored During Active Frames in SPORT Multi-Channel Mode */
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#define ANOMALY_05000201 (__SILICON_REVISION__ == 3)
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/* Possible Infinite Stall with Specific Dual-DAG Situation */
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#define ANOMALY_05000202 (__SILICON_REVISION__ < 5)
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/* Specific Sequence That Can Cause DMA Error or DMA Stopping */
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#define ANOMALY_05000203 (__SILICON_REVISION__ < 4)
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/* Incorrect Data Read with Writethrough "Allocate Cache Lines on Reads Only" Cache Mode */
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#define ANOMALY_05000204 (__SILICON_REVISION__ < 4 && ANOMALY_BF533)
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/* Recovery from "Brown-Out" Condition */
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#define ANOMALY_05000207 (__SILICON_REVISION__ < 4)
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/* VSTAT Status Bit in PLL_STAT Register Is Not Functional */
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#define ANOMALY_05000208 (1)
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/* Speed Path in Computational Unit Affects Certain Instructions */
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#define ANOMALY_05000209 (__SILICON_REVISION__ < 4)
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/* UART TX Interrupt Masked Erroneously */
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#define ANOMALY_05000215 (__SILICON_REVISION__ < 5)
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/* NMI Event at Boot Time Results in Unpredictable State */
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#define ANOMALY_05000219 (1)
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/* Incorrect Pulse-Width of UART Start Bit */
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#define ANOMALY_05000225 (__SILICON_REVISION__ < 5)
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/* Scratchpad Memory Bank Reads May Return Incorrect Data */
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#define ANOMALY_05000227 (__SILICON_REVISION__ < 5)
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/* SPI Slave Boot Mode Modifies Registers from Reset Value */
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#define ANOMALY_05000229 (1)
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/* UART Receiver is Less Robust Against Baudrate Differences in Certain Conditions */
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#define ANOMALY_05000230 (__SILICON_REVISION__ < 5)
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/* UART STB Bit Incorrectly Affects Receiver Setting */
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#define ANOMALY_05000231 (__SILICON_REVISION__ < 5)
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/* PPI_FS3 Is Not Driven in 2 or 3 Internal Frame Sync Transmit Modes */
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#define ANOMALY_05000233 (__SILICON_REVISION__ < 6)
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/* Incorrect Revision Number in DSPID Register */
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#define ANOMALY_05000234 (__SILICON_REVISION__ == 4)
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/* DF Bit in PLL_CTL Register Does Not Respond to Hardware Reset */
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#define ANOMALY_05000242 (__SILICON_REVISION__ < 5)
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/* If I-Cache Is On, CSYNC/SSYNC/IDLE Around Change of Control Causes Failures */
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#define ANOMALY_05000244 (__SILICON_REVISION__ < 5)
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/* False Hardware Error from an Access in the Shadow of a Conditional Branch */
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#define ANOMALY_05000245 (1)
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/* Data CPLBs Should Prevent False Hardware Errors */
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#define ANOMALY_05000246 (__SILICON_REVISION__ < 5)
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/* Incorrect Bit Shift of Data Word in Multichannel (TDM) Mode in Certain Conditions */
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#define ANOMALY_05000250 (__SILICON_REVISION__ == 4)
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/* Maximum External Clock Speed for Timers */
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#define ANOMALY_05000253 (__SILICON_REVISION__ < 5)
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/* Incorrect Timer Pulse Width in Single-Shot PWM_OUT Mode with External Clock */
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#define ANOMALY_05000254 (__SILICON_REVISION__ > 4)
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/* Entering Hibernate State with RTC Seconds Interrupt Not Functional */
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#define ANOMALY_05000255 (__SILICON_REVISION__ < 5)
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/* Interrupt/Exception During Short Hardware Loop May Cause Bad Instruction Fetches */
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#define ANOMALY_05000257 (__SILICON_REVISION__ < 5)
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/* Instruction Cache Is Corrupted When Bits 9 and 12 of the ICPLB Data Registers Differ */
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#define ANOMALY_05000258 (__SILICON_REVISION__ < 5)
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/* ICPLB_STATUS MMR Register May Be Corrupted */
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#define ANOMALY_05000260 (__SILICON_REVISION__ < 5)
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/* DCPLB_FAULT_ADDR MMR Register May Be Corrupted */
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#define ANOMALY_05000261 (__SILICON_REVISION__ < 5)
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/* Stores To Data Cache May Be Lost */
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#define ANOMALY_05000262 (__SILICON_REVISION__ < 5)
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/* Hardware Loop Corrupted When Taking an ICPLB Exception */
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#define ANOMALY_05000263 (__SILICON_REVISION__ < 5)
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/* CSYNC/SSYNC/IDLE Causes Infinite Stall in Penultimate Instruction in Hardware Loop */
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#define ANOMALY_05000264 (__SILICON_REVISION__ < 5)
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/* Sensitivity To Noise with Slow Input Edge Rates on External SPORT TX and RX Clocks */
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#define ANOMALY_05000265 (1)
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/* High I/O Activity Causes Output Voltage of Internal Voltage Regulator (Vddint) to Increase */
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#define ANOMALY_05000269 (__SILICON_REVISION__ < 5)
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/* High I/O Activity Causes Output Voltage of Internal Voltage Regulator (Vddint) to Decrease */
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#define ANOMALY_05000270 (__SILICON_REVISION__ < 5)
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/* Spontaneous Reset of Internal Voltage Regulator */
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#define ANOMALY_05000271 (__SILICON_REVISION__ == 3)
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/* Certain Data Cache Writethrough Modes Fail for Vddint <= 0.9V */
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#define ANOMALY_05000272 (1)
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/* Writes to Synchronous SDRAM Memory May Be Lost */
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#define ANOMALY_05000273 (__SILICON_REVISION__ < 6)
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/* Timing Requirements Change for External Frame Sync PPI Modes with Non-Zero PPI_DELAY */
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#define ANOMALY_05000276 (1)
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/* Writes to an I/O Data Register One SCLK Cycle after an Edge Is Detected May Clear Interrupt */
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#define ANOMALY_05000277 (__SILICON_REVISION__ < 6)
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/* Disabling Peripherals with DMA Running May Cause DMA System Instability */
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#define ANOMALY_05000278 (__SILICON_REVISION__ < 6)
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/* False Hardware Error when ISR Context Is Not Restored */
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#define ANOMALY_05000281 (__SILICON_REVISION__ < 6)
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/* Memory DMA Corruption with 32-Bit Data and Traffic Control */
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#define ANOMALY_05000282 (__SILICON_REVISION__ < 6)
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/* System MMR Write Is Stalled Indefinitely when Killed in a Particular Stage */
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#define ANOMALY_05000283 (__SILICON_REVISION__ < 6)
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/* SPORTs May Receive Bad Data If FIFOs Fill Up */
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#define ANOMALY_05000288 (__SILICON_REVISION__ < 6)
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/* Memory-To-Memory DMA Source/Destination Descriptors Must Be in Same Memory Space */
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#define ANOMALY_05000301 (__SILICON_REVISION__ < 6)
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/* SSYNCs after Writes to DMA MMR Registers May Not Be Handled Correctly */
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#define ANOMALY_05000302 (__SILICON_REVISION__ < 5)
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/* SPORT_HYS Bit in PLL_CTL Register Is Not Functional */
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#define ANOMALY_05000305 (__SILICON_REVISION__ < 5)
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/* ALT_TIMING Bit in PPI_CONTROL Register Is Not Functional */
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#define ANOMALY_05000306 (__SILICON_REVISION__ < 5)
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/* SCKELOW Bit Does Not Maintain State Through Hibernate */
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#define ANOMALY_05000307 (1) /* note: brokenness is noted in documentation, not anomaly sheet */
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/* False Hardware Errors Caused by Fetches at the Boundary of Reserved Memory */
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#define ANOMALY_05000310 (1)
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/* Erroneous Flag (GPIO) Pin Operations under Specific Sequences */
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#define ANOMALY_05000311 (__SILICON_REVISION__ < 6)
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/* Errors when SSYNC, CSYNC, or Loads to LT, LB and LC Registers Are Interrupted */
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#define ANOMALY_05000312 (__SILICON_REVISION__ < 6)
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/* PPI Is Level-Sensitive on First Transfer In Single Frame Sync Modes */
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#define ANOMALY_05000313 (__SILICON_REVISION__ < 6)
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/* Killed System MMR Write Completes Erroneously on Next System MMR Access */
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#define ANOMALY_05000315 (__SILICON_REVISION__ < 6)
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/* Internal Voltage Regulator Values of 1.05V, 1.10V and 1.15V Not Allowed for LQFP Packages */
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#define ANOMALY_05000319 ((ANOMALY_BF531 || ANOMALY_BF532) && __SILICON_REVISION__ < 6)
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/* Serial Port (SPORT) Multichannel Transmit Failure when Channel 0 Is Disabled */
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#define ANOMALY_05000357 (__SILICON_REVISION__ < 6)
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/* UART Break Signal Issues */
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#define ANOMALY_05000363 (__SILICON_REVISION__ < 5)
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/* PPI Underflow Error Goes Undetected in ITU-R 656 Mode */
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#define ANOMALY_05000366 (1)
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/* Possible RETS Register Corruption when Subroutine Is under 5 Cycles in Duration */
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#define ANOMALY_05000371 (__SILICON_REVISION__ < 6)
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/* PPI Does Not Start Properly In Specific Mode */
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#define ANOMALY_05000400 (__SILICON_REVISION__ == 5)
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/* SSYNC Stalls Processor when Executed from Non-Cacheable Memory */
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#define ANOMALY_05000402 (__SILICON_REVISION__ == 5)
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/* Level-Sensitive External GPIO Wakeups May Cause Indefinite Stall */
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#define ANOMALY_05000403 (1)
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/* Speculative Fetches Can Cause Undesired External FIFO Operations */
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#define ANOMALY_05000416 (1)
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/* Multichannel SPORT Channel Misalignment Under Specific Configuration */
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#define ANOMALY_05000425 (1)
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/* Speculative Fetches of Indirect-Pointer Instructions Can Cause False Hardware Errors */
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#define ANOMALY_05000426 (1)
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/* IFLUSH Instruction at End of Hardware Loop Causes Infinite Stall */
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#define ANOMALY_05000443 (1)
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/* False Hardware Error when RETI Points to Invalid Memory */
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#define ANOMALY_05000461 (1)
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/* Synchronization Problem at Startup May Cause SPORT Transmit Channels to Misalign */
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#define ANOMALY_05000462 (1)
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/* Boot Failure When SDRAM Control Signals Toggle Coming Out Of Reset */
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#define ANOMALY_05000471 (1)
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/* Interrupted SPORT Receive Data Register Read Results In Underflow when SLEN > 15 */
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#define ANOMALY_05000473 (1)
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/* Possible Lockup Condition when Modifying PLL from External Memory */
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#define ANOMALY_05000475 (1)
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/* TESTSET Instruction Cannot Be Interrupted */
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#define ANOMALY_05000477 (1)
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/* Reads of ITEST_COMMAND and ITEST_DATA Registers Cause Cache Corruption */
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#define ANOMALY_05000481 (1)
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/* PLL May Latch Incorrect Values Coming Out of Reset */
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#define ANOMALY_05000489 (1)
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/* Instruction Memory Stalls Can Cause IFLUSH to Fail */
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#define ANOMALY_05000491 (1)
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/* EXCPT Instruction May Be Lost If NMI Happens Simultaneously */
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#define ANOMALY_05000494 (1)
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/* RXS Bit in SPI_STAT May Become Stuck In RX DMA Modes */
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#define ANOMALY_05000501 (1)
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/*
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* These anomalies have been "phased" out of analog.com anomaly sheets and are
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* here to show running on older silicon just isn't feasible.
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*/
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/* Internal voltage regulator can't be modified via register writes */
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#define ANOMALY_05000066 (__SILICON_REVISION__ < 2)
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/* Watchpoints (Hardware Breakpoints) are not supported */
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#define ANOMALY_05000067 (__SILICON_REVISION__ < 3)
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/* SDRAM PSSE bit cannot be set again after SDRAM Powerup */
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#define ANOMALY_05000070 (__SILICON_REVISION__ < 2)
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/* Writing FIO_DIR can corrupt a programmable flag's data */
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#define ANOMALY_05000079 (__SILICON_REVISION__ < 2)
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/* Timer Auto-Baud Mode requires the UART clock to be enabled. */
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#define ANOMALY_05000086 (__SILICON_REVISION__ < 2)
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/* Internal Clocking Modes on SPORT0 not supported */
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#define ANOMALY_05000088 (__SILICON_REVISION__ < 2)
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/* Internal voltage regulator does not wake up from an RTC wakeup */
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#define ANOMALY_05000092 (__SILICON_REVISION__ < 2)
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/* The IFLUSH Instruction Must Be Preceded by a CSYNC Instruction */
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#define ANOMALY_05000093 (__SILICON_REVISION__ < 2)
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/* Vectoring to instruction that is being filled into the i-cache may cause erroneous behavior */
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#define ANOMALY_05000095 (__SILICON_REVISION__ < 2)
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/* PREFETCH, FLUSH, and FLUSHINV Instructions Must Be Followed by a CSYNC Instruction */
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#define ANOMALY_05000096 (__SILICON_REVISION__ < 2)
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/* Performance Monitor 0 and 1 are swapped when monitoring memory events */
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#define ANOMALY_05000097 (__SILICON_REVISION__ < 2)
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/* 32-bit SPORT DMA will be word reversed */
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#define ANOMALY_05000098 (__SILICON_REVISION__ < 2)
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/* Incorrect status in the UART_IIR register */
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#define ANOMALY_05000100 (__SILICON_REVISION__ < 2)
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/* Reading X_MODIFY or Y_MODIFY while DMA channel is active */
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#define ANOMALY_05000101 (__SILICON_REVISION__ < 2)
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/* Descriptor MemDMA may lock up with 32-bit transfers or if transfers span 64KB buffers */
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#define ANOMALY_05000102 (__SILICON_REVISION__ < 2)
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/* Incorrect Value Written to the Cycle Counters */
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#define ANOMALY_05000103 (__SILICON_REVISION__ < 2)
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/* Stores to L1 Data Memory Incorrect when a Specific Sequence Is Followed */
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#define ANOMALY_05000104 (__SILICON_REVISION__ < 2)
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/* Programmable Flag (PF3) functionality not supported in all PPI modes */
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#define ANOMALY_05000106 (__SILICON_REVISION__ < 2)
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/* Data store can be lost when targeting a cache line fill */
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#define ANOMALY_05000107 (__SILICON_REVISION__ < 2)
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/* Reserved Bits in SYSCFG Register Not Set at Power-On */
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#define ANOMALY_05000109 (__SILICON_REVISION__ < 3)
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/* Infinite Core Stall */
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#define ANOMALY_05000114 (__SILICON_REVISION__ < 2)
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/* PPI_FSx may glitch when generated by the on chip Timers. */
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#define ANOMALY_05000115 (__SILICON_REVISION__ < 2)
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/* Trace Buffers May Contain Errors in Emulation Mode and/or Exception, NMI, Reset Handlers */
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#define ANOMALY_05000116 (__SILICON_REVISION__ < 3)
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/* DTEST registers allow access to Data Cache when DTEST_COMMAND< 14 >= 0 */
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#define ANOMALY_05000117 (__SILICON_REVISION__ < 2)
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/* Booting from an 8-bit or 24-bit Addressable SPI device is not supported */
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#define ANOMALY_05000118 (__SILICON_REVISION__ < 2)
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/* DTEST_COMMAND Initiated Memory Access May Be Incorrect If Data Cache or DMA Is Active */
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#define ANOMALY_05000123 (__SILICON_REVISION__ < 3)
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/* DMA Lock-up at CCLK to SCLK ratios of 4:1, 2:1, or 1:1 */
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#define ANOMALY_05000124 (__SILICON_REVISION__ < 3)
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/* Erroneous Exception when Enabling Cache */
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#define ANOMALY_05000125 (__SILICON_REVISION__ < 3)
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/* SPI clock polarity and phase bits incorrect during booting */
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#define ANOMALY_05000126 (__SILICON_REVISION__ < 3)
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/* DMEM_CONTROL<12> Is Not Set on Reset */
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#define ANOMALY_05000137 (__SILICON_REVISION__ < 3)
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/* SPI boot will not complete if there is a zero fill block in the loader file */
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#define ANOMALY_05000138 (__SILICON_REVISION__ == 2)
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/* TIMERx_CONFIG[5] must be set for PPI in GP output mode with internal Frame Syncs */
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#define ANOMALY_05000139 (__SILICON_REVISION__ < 2)
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/* Allowing the SPORT RX FIFO to fill will cause an overflow */
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#define ANOMALY_05000140 (__SILICON_REVISION__ < 3)
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/* Infinite Stall may occur with a particular sequence of consecutive dual dag events */
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#define ANOMALY_05000141 (__SILICON_REVISION__ < 3)
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/* Interrupts may be lost when a programmable input flag is configured to be edge sensitive */
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#define ANOMALY_05000142 (__SILICON_REVISION__ < 3)
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/* A read from external memory may return a wrong value with data cache enabled */
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#define ANOMALY_05000143 (__SILICON_REVISION__ < 3)
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/* DMA and TESTSET conflict when both are accessing external memory */
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#define ANOMALY_05000144 (__SILICON_REVISION__ < 3)
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/* In PWM_OUT mode, you must enable the PPI block to generate a waveform from PPI_CLK */
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#define ANOMALY_05000145 (__SILICON_REVISION__ < 3)
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/* MDMA may lose the first few words of a descriptor chain */
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#define ANOMALY_05000146 (__SILICON_REVISION__ < 3)
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/* Source MDMA descriptor may stop with a DMA Error near beginning of descriptor fetch */
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#define ANOMALY_05000147 (__SILICON_REVISION__ < 3)
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/* When booting from 16-bit asynchronous memory, the upper 8 bits of each word must be 0x00 */
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#define ANOMALY_05000148 (__SILICON_REVISION__ < 3)
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/* Frame Delay in SPORT Multichannel Mode */
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#define ANOMALY_05000153 (__SILICON_REVISION__ < 3)
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/* SPORT TFS signal stays active in multichannel mode outside of valid channels */
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#define ANOMALY_05000154 (__SILICON_REVISION__ < 3)
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/* Timer1 can not be used for PWMOUT mode when a certain PPI mode is in use */
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#define ANOMALY_05000155 (__SILICON_REVISION__ < 3)
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/* Killed 32-Bit MMR Write Leads to Next System MMR Access Thinking It Should Be 32-Bit */
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#define ANOMALY_05000157 (__SILICON_REVISION__ < 3)
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/* SPORT Transmit Data Is Not Gated by External Frame Sync in Certain Conditions */
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#define ANOMALY_05000163 (__SILICON_REVISION__ < 3)
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/* Undefined Behavior when Power-Up Sequence Is Issued to SDRAM during Auto-Refresh */
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#define ANOMALY_05000168 (__SILICON_REVISION__ < 3)
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/* DATA CPLB Page Miss Can Result in Lost Write-Through Data Cache Writes */
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#define ANOMALY_05000169 (__SILICON_REVISION__ < 3)
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/* DMA vs Core accesses to external memory */
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#define ANOMALY_05000173 (__SILICON_REVISION__ < 3)
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/* Cache Fill Buffer Data lost */
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#define ANOMALY_05000174 (__SILICON_REVISION__ < 3)
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/* Overlapping Sequencer and Memory Stalls */
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#define ANOMALY_05000175 (__SILICON_REVISION__ < 3)
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/* Overflow Bit Asserted when Multiplication of -1 by -1 Followed by Accumulator Saturation */
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#define ANOMALY_05000176 (__SILICON_REVISION__ < 3)
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/* Disabling the PPI Resets the PPI Configuration Registers */
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#define ANOMALY_05000181 (__SILICON_REVISION__ < 3)
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/* Early PPI Transmit when FS1 Asserts before FS2 in TX Mode with 2 External Frame Syncs */
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#define ANOMALY_05000185 (__SILICON_REVISION__ < 3)
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/* PPI does not invert the Driving PPICLK edge in Transmit Modes */
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#define ANOMALY_05000191 (__SILICON_REVISION__ < 3)
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/* In PPI Transmit Modes with External Frame Syncs POLC bit must be set to 1 */
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#define ANOMALY_05000192 (__SILICON_REVISION__ < 3)
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/* Internal Voltage Regulator may not start up */
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#define ANOMALY_05000206 (__SILICON_REVISION__ < 3)
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/* Anomalies that don't exist on this proc */
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#define ANOMALY_05000120 (0)
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#define ANOMALY_05000149 (0)
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#define ANOMALY_05000171 (0)
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#define ANOMALY_05000182 (0)
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#define ANOMALY_05000220 (0)
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#define ANOMALY_05000248 (0)
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#define ANOMALY_05000266 (0)
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#define ANOMALY_05000274 (0)
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#define ANOMALY_05000287 (0)
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#define ANOMALY_05000323 (0)
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#define ANOMALY_05000353 (1)
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#define ANOMALY_05000362 (1)
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#define ANOMALY_05000364 (0)
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#define ANOMALY_05000380 (0)
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#define ANOMALY_05000383 (0)
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#define ANOMALY_05000386 (1)
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#define ANOMALY_05000389 (0)
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#define ANOMALY_05000412 (0)
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#define ANOMALY_05000430 (0)
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#define ANOMALY_05000432 (0)
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#define ANOMALY_05000435 (0)
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#define ANOMALY_05000440 (0)
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#define ANOMALY_05000447 (0)
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#define ANOMALY_05000448 (0)
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#define ANOMALY_05000456 (0)
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#define ANOMALY_05000450 (0)
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#define ANOMALY_05000465 (0)
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#define ANOMALY_05000467 (0)
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#define ANOMALY_05000474 (0)
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#define ANOMALY_05000480 (0)
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#define ANOMALY_05000485 (0)
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#define ANOMALY_16000030 (0)
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#endif
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