729 lines
15 KiB
C
729 lines
15 KiB
C
/* linux/arch/arm/plat-s5pc1xx/clock.c
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*
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* Copyright 2009 Samsung Electronics Co.
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*
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* S5PC1XX Base clock support
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*
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* Based on plat-s3c64xx/clock.c
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#include <linux/init.h>
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#include <linux/module.h>
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#include <linux/interrupt.h>
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#include <linux/ioport.h>
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#include <linux/clk.h>
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#include <linux/io.h>
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#include <mach/hardware.h>
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#include <mach/map.h>
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#include <plat/regs-clock.h>
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#include <plat/devs.h>
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#include <plat/clock.h>
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struct clk clk_27m = {
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.name = "clk_27m",
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.id = -1,
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.rate = 27000000,
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};
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static int clk_48m_ctrl(struct clk *clk, int enable)
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{
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unsigned long flags;
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u32 val;
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/* can't rely on clock lock, this register has other usages */
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local_irq_save(flags);
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val = __raw_readl(S5PC100_CLKSRC1);
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if (enable)
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val |= S5PC100_CLKSRC1_CLK48M_MASK;
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else
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val &= ~S5PC100_CLKSRC1_CLK48M_MASK;
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__raw_writel(val, S5PC100_CLKSRC1);
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local_irq_restore(flags);
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return 0;
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}
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struct clk clk_48m = {
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.name = "clk_48m",
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.id = -1,
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.rate = 48000000,
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.enable = clk_48m_ctrl,
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};
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struct clk clk_54m = {
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.name = "clk_54m",
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.id = -1,
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.rate = 54000000,
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};
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static int clk_default_setrate(struct clk *clk, unsigned long rate)
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{
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clk->rate = rate;
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return 0;
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}
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static int clk_dummy_enable(struct clk *clk, int enable)
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{
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return 0;
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}
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struct clk clk_hd0 = {
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.name = "hclkd0",
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.id = -1,
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.rate = 0,
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.parent = NULL,
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.ctrlbit = 0,
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.set_rate = clk_default_setrate,
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.enable = clk_dummy_enable,
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};
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struct clk clk_pd0 = {
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.name = "pclkd0",
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.id = -1,
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.rate = 0,
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.parent = NULL,
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.ctrlbit = 0,
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.set_rate = clk_default_setrate,
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.enable = clk_dummy_enable,
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};
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static int s5pc1xx_clk_gate(void __iomem *reg, struct clk *clk, int enable)
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{
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unsigned int ctrlbit = clk->ctrlbit;
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u32 con;
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con = __raw_readl(reg);
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if (enable)
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con |= ctrlbit;
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else
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con &= ~ctrlbit;
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__raw_writel(con, reg);
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return 0;
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}
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static int s5pc100_clk_d00_ctrl(struct clk *clk, int enable)
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{
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return s5pc1xx_clk_gate(S5PC100_CLKGATE_D00, clk, enable);
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}
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static int s5pc100_clk_d01_ctrl(struct clk *clk, int enable)
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{
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return s5pc1xx_clk_gate(S5PC100_CLKGATE_D01, clk, enable);
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}
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static int s5pc100_clk_d02_ctrl(struct clk *clk, int enable)
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{
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return s5pc1xx_clk_gate(S5PC100_CLKGATE_D02, clk, enable);
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}
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static int s5pc100_clk_d10_ctrl(struct clk *clk, int enable)
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{
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return s5pc1xx_clk_gate(S5PC100_CLKGATE_D10, clk, enable);
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}
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static int s5pc100_clk_d11_ctrl(struct clk *clk, int enable)
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{
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return s5pc1xx_clk_gate(S5PC100_CLKGATE_D11, clk, enable);
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}
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static int s5pc100_clk_d12_ctrl(struct clk *clk, int enable)
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{
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return s5pc1xx_clk_gate(S5PC100_CLKGATE_D12, clk, enable);
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}
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static int s5pc100_clk_d13_ctrl(struct clk *clk, int enable)
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{
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return s5pc1xx_clk_gate(S5PC100_CLKGATE_D13, clk, enable);
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}
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static int s5pc100_clk_d14_ctrl(struct clk *clk, int enable)
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{
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return s5pc1xx_clk_gate(S5PC100_CLKGATE_D14, clk, enable);
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}
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static int s5pc100_clk_d15_ctrl(struct clk *clk, int enable)
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{
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return s5pc1xx_clk_gate(S5PC100_CLKGATE_D15, clk, enable);
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}
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static int s5pc100_clk_d20_ctrl(struct clk *clk, int enable)
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{
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return s5pc1xx_clk_gate(S5PC100_CLKGATE_D20, clk, enable);
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}
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int s5pc100_sclk0_ctrl(struct clk *clk, int enable)
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{
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return s5pc1xx_clk_gate(S5PC100_SCLKGATE0, clk, enable);
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}
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int s5pc100_sclk1_ctrl(struct clk *clk, int enable)
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{
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return s5pc1xx_clk_gate(S5PC100_SCLKGATE1, clk, enable);
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}
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static struct clk s5pc100_init_clocks_disable[] = {
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{
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.name = "dsi",
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.id = -1,
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.parent = &clk_p,
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.enable = s5pc100_clk_d11_ctrl,
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.ctrlbit = S5PC100_CLKGATE_D11_DSI,
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}, {
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.name = "csi",
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.id = -1,
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.parent = &clk_h,
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.enable = s5pc100_clk_d11_ctrl,
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.ctrlbit = S5PC100_CLKGATE_D11_CSI,
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}, {
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.name = "ccan",
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.id = 0,
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.parent = &clk_p,
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.enable = s5pc100_clk_d14_ctrl,
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.ctrlbit = S5PC100_CLKGATE_D14_CCAN0,
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}, {
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.name = "ccan",
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.id = 1,
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.parent = &clk_p,
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.enable = s5pc100_clk_d14_ctrl,
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.ctrlbit = S5PC100_CLKGATE_D14_CCAN1,
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}, {
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.name = "keypad",
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.id = -1,
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.parent = &clk_p,
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.enable = s5pc100_clk_d15_ctrl,
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.ctrlbit = S5PC100_CLKGATE_D15_KEYIF,
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}, {
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.name = "hclkd2",
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.id = -1,
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.parent = NULL,
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.enable = s5pc100_clk_d20_ctrl,
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.ctrlbit = S5PC100_CLKGATE_D20_HCLKD2,
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}, {
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.name = "iis-d2",
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.id = -1,
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.parent = NULL,
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.enable = s5pc100_clk_d20_ctrl,
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.ctrlbit = S5PC100_CLKGATE_D20_I2SD2,
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},
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};
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static struct clk s5pc100_init_clocks[] = {
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/* System1 (D0_0) devices */
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{
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.name = "intc",
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.id = -1,
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.parent = &clk_hd0,
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.enable = s5pc100_clk_d00_ctrl,
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.ctrlbit = S5PC100_CLKGATE_D00_INTC,
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}, {
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.name = "tzic",
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.id = -1,
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.parent = &clk_hd0,
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.enable = s5pc100_clk_d00_ctrl,
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.ctrlbit = S5PC100_CLKGATE_D00_TZIC,
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}, {
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.name = "cf-ata",
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.id = -1,
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.parent = &clk_hd0,
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.enable = s5pc100_clk_d00_ctrl,
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.ctrlbit = S5PC100_CLKGATE_D00_CFCON,
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}, {
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.name = "mdma",
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.id = -1,
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.parent = &clk_hd0,
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.enable = s5pc100_clk_d00_ctrl,
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.ctrlbit = S5PC100_CLKGATE_D00_MDMA,
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}, {
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.name = "g2d",
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.id = -1,
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.parent = &clk_hd0,
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.enable = s5pc100_clk_d00_ctrl,
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.ctrlbit = S5PC100_CLKGATE_D00_G2D,
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}, {
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.name = "secss",
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.id = -1,
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.parent = &clk_hd0,
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.enable = s5pc100_clk_d00_ctrl,
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.ctrlbit = S5PC100_CLKGATE_D00_SECSS,
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}, {
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.name = "cssys",
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.id = -1,
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.parent = &clk_hd0,
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.enable = s5pc100_clk_d00_ctrl,
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.ctrlbit = S5PC100_CLKGATE_D00_CSSYS,
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},
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/* Memory (D0_1) devices */
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{
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.name = "dmc",
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.id = -1,
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.parent = &clk_hd0,
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.enable = s5pc100_clk_d01_ctrl,
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.ctrlbit = S5PC100_CLKGATE_D01_DMC,
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}, {
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.name = "sromc",
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.id = -1,
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.parent = &clk_hd0,
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.enable = s5pc100_clk_d01_ctrl,
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.ctrlbit = S5PC100_CLKGATE_D01_SROMC,
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}, {
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.name = "onenand",
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.id = -1,
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.parent = &clk_hd0,
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.enable = s5pc100_clk_d01_ctrl,
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.ctrlbit = S5PC100_CLKGATE_D01_ONENAND,
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}, {
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.name = "nand",
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.id = -1,
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.parent = &clk_hd0,
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.enable = s5pc100_clk_d01_ctrl,
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.ctrlbit = S5PC100_CLKGATE_D01_NFCON,
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}, {
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.name = "intmem",
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.id = -1,
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.parent = &clk_hd0,
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.enable = s5pc100_clk_d01_ctrl,
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.ctrlbit = S5PC100_CLKGATE_D01_INTMEM,
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}, {
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.name = "ebi",
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.id = -1,
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.parent = &clk_hd0,
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.enable = s5pc100_clk_d01_ctrl,
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.ctrlbit = S5PC100_CLKGATE_D01_EBI,
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},
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/* System2 (D0_2) devices */
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{
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.name = "seckey",
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.id = -1,
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.parent = &clk_pd0,
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.enable = s5pc100_clk_d02_ctrl,
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.ctrlbit = S5PC100_CLKGATE_D02_SECKEY,
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}, {
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.name = "sdm",
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.id = -1,
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.parent = &clk_hd0,
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.enable = s5pc100_clk_d02_ctrl,
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.ctrlbit = S5PC100_CLKGATE_D02_SDM,
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},
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/* File (D1_0) devices */
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{
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.name = "pdma",
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.id = 0,
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.parent = &clk_h,
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.enable = s5pc100_clk_d10_ctrl,
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.ctrlbit = S5PC100_CLKGATE_D10_PDMA0,
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}, {
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.name = "pdma",
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.id = 1,
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.parent = &clk_h,
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.enable = s5pc100_clk_d10_ctrl,
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.ctrlbit = S5PC100_CLKGATE_D10_PDMA1,
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}, {
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.name = "usb-host",
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.id = -1,
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.parent = &clk_h,
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.enable = s5pc100_clk_d10_ctrl,
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.ctrlbit = S5PC100_CLKGATE_D10_USBHOST,
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}, {
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.name = "otg",
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.id = -1,
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.parent = &clk_h,
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.enable = s5pc100_clk_d10_ctrl,
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.ctrlbit = S5PC100_CLKGATE_D10_USBOTG,
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}, {
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.name = "modem",
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.id = -1,
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.parent = &clk_h,
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.enable = s5pc100_clk_d10_ctrl,
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.ctrlbit = S5PC100_CLKGATE_D10_MODEMIF,
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}, {
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.name = "hsmmc",
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.id = 0,
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.parent = &clk_48m,
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.enable = s5pc100_clk_d10_ctrl,
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.ctrlbit = S5PC100_CLKGATE_D10_HSMMC0,
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}, {
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.name = "hsmmc",
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.id = 1,
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.parent = &clk_48m,
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.enable = s5pc100_clk_d10_ctrl,
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.ctrlbit = S5PC100_CLKGATE_D10_HSMMC1,
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}, {
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.name = "hsmmc",
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.id = 2,
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.parent = &clk_48m,
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.enable = s5pc100_clk_d10_ctrl,
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.ctrlbit = S5PC100_CLKGATE_D10_HSMMC2,
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},
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/* Multimedia1 (D1_1) devices */
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{
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.name = "lcd",
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.id = -1,
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.parent = &clk_p,
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.enable = s5pc100_clk_d11_ctrl,
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.ctrlbit = S5PC100_CLKGATE_D11_LCD,
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}, {
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.name = "rotator",
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.id = -1,
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.parent = &clk_p,
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.enable = s5pc100_clk_d11_ctrl,
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.ctrlbit = S5PC100_CLKGATE_D11_ROTATOR,
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}, {
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.name = "fimc",
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.id = -1,
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.parent = &clk_p,
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.enable = s5pc100_clk_d11_ctrl,
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.ctrlbit = S5PC100_CLKGATE_D11_FIMC0,
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}, {
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.name = "fimc",
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.id = -1,
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.parent = &clk_p,
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.enable = s5pc100_clk_d11_ctrl,
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.ctrlbit = S5PC100_CLKGATE_D11_FIMC1,
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}, {
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.name = "fimc",
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.id = -1,
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.parent = &clk_p,
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.enable = s5pc100_clk_d11_ctrl,
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.ctrlbit = S5PC100_CLKGATE_D11_FIMC2,
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}, {
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.name = "jpeg",
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.id = -1,
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.parent = &clk_p,
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.enable = s5pc100_clk_d11_ctrl,
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.ctrlbit = S5PC100_CLKGATE_D11_JPEG,
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}, {
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.name = "g3d",
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.id = -1,
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.parent = &clk_p,
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.enable = s5pc100_clk_d11_ctrl,
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.ctrlbit = S5PC100_CLKGATE_D11_G3D,
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},
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/* Multimedia2 (D1_2) devices */
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{
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.name = "tv",
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.id = -1,
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.parent = &clk_p,
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.enable = s5pc100_clk_d12_ctrl,
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.ctrlbit = S5PC100_CLKGATE_D12_TV,
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}, {
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.name = "vp",
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.id = -1,
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.parent = &clk_p,
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.enable = s5pc100_clk_d12_ctrl,
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.ctrlbit = S5PC100_CLKGATE_D12_VP,
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}, {
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.name = "mixer",
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.id = -1,
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.parent = &clk_p,
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.enable = s5pc100_clk_d12_ctrl,
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.ctrlbit = S5PC100_CLKGATE_D12_MIXER,
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}, {
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.name = "hdmi",
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.id = -1,
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.parent = &clk_p,
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.enable = s5pc100_clk_d12_ctrl,
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.ctrlbit = S5PC100_CLKGATE_D12_HDMI,
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}, {
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.name = "mfc",
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.id = -1,
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.parent = &clk_p,
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.enable = s5pc100_clk_d12_ctrl,
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.ctrlbit = S5PC100_CLKGATE_D12_MFC,
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},
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/* System (D1_3) devices */
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{
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.name = "chipid",
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.id = -1,
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.parent = &clk_p,
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.enable = s5pc100_clk_d13_ctrl,
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.ctrlbit = S5PC100_CLKGATE_D13_CHIPID,
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}, {
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.name = "gpio",
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.id = -1,
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.parent = &clk_p,
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.enable = s5pc100_clk_d13_ctrl,
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.ctrlbit = S5PC100_CLKGATE_D13_GPIO,
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}, {
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.name = "apc",
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.id = -1,
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.parent = &clk_p,
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.enable = s5pc100_clk_d13_ctrl,
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.ctrlbit = S5PC100_CLKGATE_D13_APC,
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}, {
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.name = "iec",
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.id = -1,
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.parent = &clk_p,
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.enable = s5pc100_clk_d13_ctrl,
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.ctrlbit = S5PC100_CLKGATE_D13_IEC,
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}, {
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.name = "timers",
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.id = -1,
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.parent = &clk_p,
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.enable = s5pc100_clk_d13_ctrl,
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.ctrlbit = S5PC100_CLKGATE_D13_PWM,
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}, {
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.name = "systimer",
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.id = -1,
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.parent = &clk_p,
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.enable = s5pc100_clk_d13_ctrl,
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.ctrlbit = S5PC100_CLKGATE_D13_SYSTIMER,
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}, {
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.name = "watchdog",
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.id = -1,
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.parent = &clk_p,
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.enable = s5pc100_clk_d13_ctrl,
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.ctrlbit = S5PC100_CLKGATE_D13_WDT,
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}, {
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.name = "rtc",
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.id = -1,
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.parent = &clk_p,
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.enable = s5pc100_clk_d13_ctrl,
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.ctrlbit = S5PC100_CLKGATE_D13_RTC,
|
|
},
|
|
|
|
/* Connectivity (D1_4) devices */
|
|
{
|
|
.name = "uart",
|
|
.id = 0,
|
|
.parent = &clk_p,
|
|
.enable = s5pc100_clk_d14_ctrl,
|
|
.ctrlbit = S5PC100_CLKGATE_D14_UART0,
|
|
}, {
|
|
.name = "uart",
|
|
.id = 1,
|
|
.parent = &clk_p,
|
|
.enable = s5pc100_clk_d14_ctrl,
|
|
.ctrlbit = S5PC100_CLKGATE_D14_UART1,
|
|
}, {
|
|
.name = "uart",
|
|
.id = 2,
|
|
.parent = &clk_p,
|
|
.enable = s5pc100_clk_d14_ctrl,
|
|
.ctrlbit = S5PC100_CLKGATE_D14_UART2,
|
|
}, {
|
|
.name = "uart",
|
|
.id = 3,
|
|
.parent = &clk_p,
|
|
.enable = s5pc100_clk_d14_ctrl,
|
|
.ctrlbit = S5PC100_CLKGATE_D14_UART3,
|
|
}, {
|
|
.name = "i2c",
|
|
.id = -1,
|
|
.parent = &clk_p,
|
|
.enable = s5pc100_clk_d14_ctrl,
|
|
.ctrlbit = S5PC100_CLKGATE_D14_IIC,
|
|
}, {
|
|
.name = "hdmi-i2c",
|
|
.id = -1,
|
|
.parent = &clk_p,
|
|
.enable = s5pc100_clk_d14_ctrl,
|
|
.ctrlbit = S5PC100_CLKGATE_D14_HDMI_IIC,
|
|
}, {
|
|
.name = "spi",
|
|
.id = 0,
|
|
.parent = &clk_p,
|
|
.enable = s5pc100_clk_d14_ctrl,
|
|
.ctrlbit = S5PC100_CLKGATE_D14_SPI0,
|
|
}, {
|
|
.name = "spi",
|
|
.id = 1,
|
|
.parent = &clk_p,
|
|
.enable = s5pc100_clk_d14_ctrl,
|
|
.ctrlbit = S5PC100_CLKGATE_D14_SPI1,
|
|
}, {
|
|
.name = "spi",
|
|
.id = 2,
|
|
.parent = &clk_p,
|
|
.enable = s5pc100_clk_d14_ctrl,
|
|
.ctrlbit = S5PC100_CLKGATE_D14_SPI2,
|
|
}, {
|
|
.name = "irda",
|
|
.id = -1,
|
|
.parent = &clk_p,
|
|
.enable = s5pc100_clk_d14_ctrl,
|
|
.ctrlbit = S5PC100_CLKGATE_D14_IRDA,
|
|
}, {
|
|
.name = "hsitx",
|
|
.id = -1,
|
|
.parent = &clk_p,
|
|
.enable = s5pc100_clk_d14_ctrl,
|
|
.ctrlbit = S5PC100_CLKGATE_D14_HSITX,
|
|
}, {
|
|
.name = "hsirx",
|
|
.id = -1,
|
|
.parent = &clk_p,
|
|
.enable = s5pc100_clk_d14_ctrl,
|
|
.ctrlbit = S5PC100_CLKGATE_D14_HSIRX,
|
|
},
|
|
|
|
/* Audio (D1_5) devices */
|
|
{
|
|
.name = "iis",
|
|
.id = 0,
|
|
.parent = &clk_p,
|
|
.enable = s5pc100_clk_d15_ctrl,
|
|
.ctrlbit = S5PC100_CLKGATE_D15_IIS0,
|
|
}, {
|
|
.name = "iis",
|
|
.id = 1,
|
|
.parent = &clk_p,
|
|
.enable = s5pc100_clk_d15_ctrl,
|
|
.ctrlbit = S5PC100_CLKGATE_D15_IIS1,
|
|
}, {
|
|
.name = "iis",
|
|
.id = 2,
|
|
.parent = &clk_p,
|
|
.enable = s5pc100_clk_d15_ctrl,
|
|
.ctrlbit = S5PC100_CLKGATE_D15_IIS2,
|
|
}, {
|
|
.name = "ac97",
|
|
.id = -1,
|
|
.parent = &clk_p,
|
|
.enable = s5pc100_clk_d15_ctrl,
|
|
.ctrlbit = S5PC100_CLKGATE_D15_AC97,
|
|
}, {
|
|
.name = "pcm",
|
|
.id = 0,
|
|
.parent = &clk_p,
|
|
.enable = s5pc100_clk_d15_ctrl,
|
|
.ctrlbit = S5PC100_CLKGATE_D15_PCM0,
|
|
}, {
|
|
.name = "pcm",
|
|
.id = 1,
|
|
.parent = &clk_p,
|
|
.enable = s5pc100_clk_d15_ctrl,
|
|
.ctrlbit = S5PC100_CLKGATE_D15_PCM1,
|
|
}, {
|
|
.name = "spdif",
|
|
.id = -1,
|
|
.parent = &clk_p,
|
|
.enable = s5pc100_clk_d15_ctrl,
|
|
.ctrlbit = S5PC100_CLKGATE_D15_SPDIF,
|
|
}, {
|
|
.name = "adc",
|
|
.id = -1,
|
|
.parent = &clk_p,
|
|
.enable = s5pc100_clk_d15_ctrl,
|
|
.ctrlbit = S5PC100_CLKGATE_D15_TSADC,
|
|
}, {
|
|
.name = "cg",
|
|
.id = -1,
|
|
.parent = &clk_p,
|
|
.enable = s5pc100_clk_d15_ctrl,
|
|
.ctrlbit = S5PC100_CLKGATE_D15_CG,
|
|
},
|
|
|
|
/* Audio (D2_0) devices: all disabled */
|
|
|
|
/* Special Clocks 0 */
|
|
{
|
|
.name = "sclk_hpm",
|
|
.id = -1,
|
|
.parent = NULL,
|
|
.enable = s5pc100_sclk0_ctrl,
|
|
.ctrlbit = S5PC100_CLKGATE_SCLK0_HPM,
|
|
}, {
|
|
.name = "sclk_onenand",
|
|
.id = -1,
|
|
.parent = NULL,
|
|
.enable = s5pc100_sclk0_ctrl,
|
|
.ctrlbit = S5PC100_CLKGATE_SCLK0_ONENAND,
|
|
}, {
|
|
.name = "spi_48",
|
|
.id = 0,
|
|
.parent = &clk_48m,
|
|
.enable = s5pc100_sclk0_ctrl,
|
|
.ctrlbit = S5PC100_CLKGATE_SCLK0_SPI0_48,
|
|
}, {
|
|
.name = "spi_48",
|
|
.id = 1,
|
|
.parent = &clk_48m,
|
|
.enable = s5pc100_sclk0_ctrl,
|
|
.ctrlbit = S5PC100_CLKGATE_SCLK0_SPI1_48,
|
|
}, {
|
|
.name = "spi_48",
|
|
.id = 2,
|
|
.parent = &clk_48m,
|
|
.enable = s5pc100_sclk0_ctrl,
|
|
.ctrlbit = S5PC100_CLKGATE_SCLK0_SPI2_48,
|
|
}, {
|
|
.name = "mmc_48",
|
|
.id = 0,
|
|
.parent = &clk_48m,
|
|
.enable = s5pc100_sclk0_ctrl,
|
|
.ctrlbit = S5PC100_CLKGATE_SCLK0_MMC0_48,
|
|
}, {
|
|
.name = "mmc_48",
|
|
.id = 1,
|
|
.parent = &clk_48m,
|
|
.enable = s5pc100_sclk0_ctrl,
|
|
.ctrlbit = S5PC100_CLKGATE_SCLK0_MMC1_48,
|
|
}, {
|
|
.name = "mmc_48",
|
|
.id = 2,
|
|
.parent = &clk_48m,
|
|
.enable = s5pc100_sclk0_ctrl,
|
|
.ctrlbit = S5PC100_CLKGATE_SCLK0_MMC2_48,
|
|
},
|
|
/* Special Clocks 1 */
|
|
};
|
|
|
|
static struct clk *clks[] __initdata = {
|
|
&clk_ext,
|
|
&clk_epll,
|
|
&clk_27m,
|
|
&clk_48m,
|
|
&clk_54m,
|
|
};
|
|
|
|
void __init s5pc1xx_register_clocks(void)
|
|
{
|
|
struct clk *clkp;
|
|
int ret;
|
|
int ptr;
|
|
int size;
|
|
|
|
s3c24xx_register_clocks(clks, ARRAY_SIZE(clks));
|
|
|
|
clkp = s5pc100_init_clocks;
|
|
size = ARRAY_SIZE(s5pc100_init_clocks);
|
|
|
|
for (ptr = 0; ptr < size; ptr++, clkp++) {
|
|
ret = s3c24xx_register_clock(clkp);
|
|
if (ret < 0) {
|
|
printk(KERN_ERR "Failed to register clock %s (%d)\n",
|
|
clkp->name, ret);
|
|
}
|
|
}
|
|
|
|
clkp = s5pc100_init_clocks_disable;
|
|
size = ARRAY_SIZE(s5pc100_init_clocks_disable);
|
|
|
|
for (ptr = 0; ptr < size; ptr++, clkp++) {
|
|
ret = s3c24xx_register_clock(clkp);
|
|
if (ret < 0) {
|
|
printk(KERN_ERR "Failed to register clock %s (%d)\n",
|
|
clkp->name, ret);
|
|
}
|
|
|
|
(clkp->enable)(clkp, 0);
|
|
}
|
|
|
|
s3c_pwmclk_init();
|
|
}
|