459 lines
9.8 KiB
C
459 lines
9.8 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
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/*
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* Copyright (c) 2014, The Linux Foundation. All rights reserved.
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*/
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#include <linux/kernel.h>
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#include <linux/bitops.h>
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#include <linux/err.h>
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#include <linux/platform_device.h>
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#include <linux/module.h>
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#include <linux/of.h>
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#include <linux/of_device.h>
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#include <linux/clk-provider.h>
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#include <linux/regmap.h>
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#include <dt-bindings/clock/qcom,lcc-ipq806x.h>
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#include "common.h"
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#include "clk-regmap.h"
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#include "clk-pll.h"
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#include "clk-rcg.h"
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#include "clk-branch.h"
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#include "clk-regmap-divider.h"
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#include "clk-regmap-mux.h"
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static struct clk_pll pll4 = {
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.l_reg = 0x4,
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.m_reg = 0x8,
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.n_reg = 0xc,
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.config_reg = 0x14,
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.mode_reg = 0x0,
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.status_reg = 0x18,
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.status_bit = 16,
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.clkr.hw.init = &(struct clk_init_data){
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.name = "pll4",
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.parent_names = (const char *[]){ "pxo" },
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.num_parents = 1,
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.ops = &clk_pll_ops,
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},
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};
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static const struct pll_config pll4_config = {
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.l = 0xf,
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.m = 0x91,
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.n = 0xc7,
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.vco_val = 0x0,
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.vco_mask = BIT(17) | BIT(16),
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.pre_div_val = 0x0,
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.pre_div_mask = BIT(19),
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.post_div_val = 0x0,
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.post_div_mask = BIT(21) | BIT(20),
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.mn_ena_mask = BIT(22),
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.main_output_mask = BIT(23),
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};
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enum {
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P_PXO,
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P_PLL4,
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};
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static const struct parent_map lcc_pxo_pll4_map[] = {
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{ P_PXO, 0 },
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{ P_PLL4, 2 }
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};
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static const char * const lcc_pxo_pll4[] = {
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"pxo",
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"pll4_vote",
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};
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static struct freq_tbl clk_tbl_aif_mi2s[] = {
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{ 1024000, P_PLL4, 4, 1, 96 },
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{ 1411200, P_PLL4, 4, 2, 139 },
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{ 1536000, P_PLL4, 4, 1, 64 },
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{ 2048000, P_PLL4, 4, 1, 48 },
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{ 2116800, P_PLL4, 4, 2, 93 },
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{ 2304000, P_PLL4, 4, 2, 85 },
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{ 2822400, P_PLL4, 4, 6, 209 },
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{ 3072000, P_PLL4, 4, 1, 32 },
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{ 3175200, P_PLL4, 4, 1, 31 },
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{ 4096000, P_PLL4, 4, 1, 24 },
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{ 4233600, P_PLL4, 4, 9, 209 },
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{ 4608000, P_PLL4, 4, 3, 64 },
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{ 5644800, P_PLL4, 4, 12, 209 },
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{ 6144000, P_PLL4, 4, 1, 16 },
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{ 6350400, P_PLL4, 4, 2, 31 },
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{ 8192000, P_PLL4, 4, 1, 12 },
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{ 8467200, P_PLL4, 4, 18, 209 },
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{ 9216000, P_PLL4, 4, 3, 32 },
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{ 11289600, P_PLL4, 4, 24, 209 },
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{ 12288000, P_PLL4, 4, 1, 8 },
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{ 12700800, P_PLL4, 4, 27, 209 },
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{ 13824000, P_PLL4, 4, 9, 64 },
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{ 16384000, P_PLL4, 4, 1, 6 },
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{ 16934400, P_PLL4, 4, 41, 238 },
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{ 18432000, P_PLL4, 4, 3, 16 },
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{ 22579200, P_PLL4, 2, 24, 209 },
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{ 24576000, P_PLL4, 4, 1, 4 },
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{ 27648000, P_PLL4, 4, 9, 32 },
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{ 33868800, P_PLL4, 4, 41, 119 },
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{ 36864000, P_PLL4, 4, 3, 8 },
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{ 45158400, P_PLL4, 1, 24, 209 },
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{ 49152000, P_PLL4, 4, 1, 2 },
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{ 50803200, P_PLL4, 1, 27, 209 },
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{ }
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};
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static struct clk_rcg mi2s_osr_src = {
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.ns_reg = 0x48,
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.md_reg = 0x4c,
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.mn = {
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.mnctr_en_bit = 8,
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.mnctr_reset_bit = 7,
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.mnctr_mode_shift = 5,
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.n_val_shift = 24,
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.m_val_shift = 8,
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.width = 8,
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},
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.p = {
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.pre_div_shift = 3,
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.pre_div_width = 2,
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},
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.s = {
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.src_sel_shift = 0,
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.parent_map = lcc_pxo_pll4_map,
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},
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.freq_tbl = clk_tbl_aif_mi2s,
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.clkr = {
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.enable_reg = 0x48,
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.enable_mask = BIT(9),
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.hw.init = &(struct clk_init_data){
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.name = "mi2s_osr_src",
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.parent_names = lcc_pxo_pll4,
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.num_parents = 2,
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.ops = &clk_rcg_ops,
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.flags = CLK_SET_RATE_GATE,
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},
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},
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};
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static const char * const lcc_mi2s_parents[] = {
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"mi2s_osr_src",
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};
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static struct clk_branch mi2s_osr_clk = {
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.halt_reg = 0x50,
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.halt_bit = 1,
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.halt_check = BRANCH_HALT_ENABLE,
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.clkr = {
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.enable_reg = 0x48,
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.enable_mask = BIT(17),
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.hw.init = &(struct clk_init_data){
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.name = "mi2s_osr_clk",
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.parent_names = lcc_mi2s_parents,
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.num_parents = 1,
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.ops = &clk_branch_ops,
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.flags = CLK_SET_RATE_PARENT,
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},
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},
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};
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static struct clk_regmap_div mi2s_div_clk = {
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.reg = 0x48,
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.shift = 10,
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.width = 4,
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.clkr = {
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.hw.init = &(struct clk_init_data){
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.name = "mi2s_div_clk",
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.parent_names = lcc_mi2s_parents,
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.num_parents = 1,
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.ops = &clk_regmap_div_ops,
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},
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},
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};
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static struct clk_branch mi2s_bit_div_clk = {
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.halt_reg = 0x50,
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.halt_bit = 0,
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.halt_check = BRANCH_HALT_ENABLE,
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.clkr = {
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.enable_reg = 0x48,
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.enable_mask = BIT(15),
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.hw.init = &(struct clk_init_data){
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.name = "mi2s_bit_div_clk",
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.parent_names = (const char *[]){ "mi2s_div_clk" },
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.num_parents = 1,
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.ops = &clk_branch_ops,
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.flags = CLK_SET_RATE_PARENT,
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},
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},
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};
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static struct clk_regmap_mux mi2s_bit_clk = {
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.reg = 0x48,
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.shift = 14,
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.width = 1,
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.clkr = {
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.hw.init = &(struct clk_init_data){
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.name = "mi2s_bit_clk",
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.parent_names = (const char *[]){
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"mi2s_bit_div_clk",
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"mi2s_codec_clk",
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},
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.num_parents = 2,
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.ops = &clk_regmap_mux_closest_ops,
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.flags = CLK_SET_RATE_PARENT,
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},
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},
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};
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static struct freq_tbl clk_tbl_pcm[] = {
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{ 64000, P_PLL4, 4, 1, 1536 },
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{ 128000, P_PLL4, 4, 1, 768 },
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{ 256000, P_PLL4, 4, 1, 384 },
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{ 512000, P_PLL4, 4, 1, 192 },
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{ 1024000, P_PLL4, 4, 1, 96 },
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{ 2048000, P_PLL4, 4, 1, 48 },
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{ },
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};
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static struct clk_rcg pcm_src = {
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.ns_reg = 0x54,
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.md_reg = 0x58,
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.mn = {
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.mnctr_en_bit = 8,
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.mnctr_reset_bit = 7,
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.mnctr_mode_shift = 5,
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.n_val_shift = 16,
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.m_val_shift = 16,
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.width = 16,
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},
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.p = {
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.pre_div_shift = 3,
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.pre_div_width = 2,
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},
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.s = {
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.src_sel_shift = 0,
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.parent_map = lcc_pxo_pll4_map,
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},
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.freq_tbl = clk_tbl_pcm,
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.clkr = {
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.enable_reg = 0x54,
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.enable_mask = BIT(9),
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.hw.init = &(struct clk_init_data){
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.name = "pcm_src",
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.parent_names = lcc_pxo_pll4,
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.num_parents = 2,
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.ops = &clk_rcg_ops,
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.flags = CLK_SET_RATE_GATE,
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},
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},
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};
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static struct clk_branch pcm_clk_out = {
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.halt_reg = 0x5c,
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.halt_bit = 0,
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.halt_check = BRANCH_HALT_ENABLE,
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.clkr = {
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.enable_reg = 0x54,
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.enable_mask = BIT(11),
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.hw.init = &(struct clk_init_data){
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.name = "pcm_clk_out",
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.parent_names = (const char *[]){ "pcm_src" },
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.num_parents = 1,
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.ops = &clk_branch_ops,
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.flags = CLK_SET_RATE_PARENT,
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},
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},
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};
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static struct clk_regmap_mux pcm_clk = {
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.reg = 0x54,
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.shift = 10,
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.width = 1,
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.clkr = {
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.hw.init = &(struct clk_init_data){
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.name = "pcm_clk",
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.parent_names = (const char *[]){
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"pcm_clk_out",
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"pcm_codec_clk",
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},
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.num_parents = 2,
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.ops = &clk_regmap_mux_closest_ops,
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.flags = CLK_SET_RATE_PARENT,
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},
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},
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};
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static struct freq_tbl clk_tbl_aif_osr[] = {
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{ 2822400, P_PLL4, 1, 147, 20480 },
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{ 4096000, P_PLL4, 1, 1, 96 },
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{ 5644800, P_PLL4, 1, 147, 10240 },
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{ 6144000, P_PLL4, 1, 1, 64 },
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{ 11289600, P_PLL4, 1, 147, 5120 },
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{ 12288000, P_PLL4, 1, 1, 32 },
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{ 22579200, P_PLL4, 1, 147, 2560 },
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{ 24576000, P_PLL4, 1, 1, 16 },
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{ },
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};
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static struct clk_rcg spdif_src = {
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.ns_reg = 0xcc,
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.md_reg = 0xd0,
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.mn = {
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.mnctr_en_bit = 8,
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.mnctr_reset_bit = 7,
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.mnctr_mode_shift = 5,
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.n_val_shift = 16,
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.m_val_shift = 16,
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.width = 8,
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},
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.p = {
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.pre_div_shift = 3,
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.pre_div_width = 2,
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},
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.s = {
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.src_sel_shift = 0,
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.parent_map = lcc_pxo_pll4_map,
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},
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.freq_tbl = clk_tbl_aif_osr,
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.clkr = {
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.enable_reg = 0xcc,
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.enable_mask = BIT(9),
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.hw.init = &(struct clk_init_data){
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.name = "spdif_src",
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.parent_names = lcc_pxo_pll4,
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.num_parents = 2,
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.ops = &clk_rcg_ops,
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.flags = CLK_SET_RATE_GATE,
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},
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},
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};
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static const char * const lcc_spdif_parents[] = {
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"spdif_src",
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};
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static struct clk_branch spdif_clk = {
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.halt_reg = 0xd4,
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.halt_bit = 1,
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.halt_check = BRANCH_HALT_ENABLE,
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.clkr = {
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.enable_reg = 0xcc,
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.enable_mask = BIT(12),
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.hw.init = &(struct clk_init_data){
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.name = "spdif_clk",
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.parent_names = lcc_spdif_parents,
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.num_parents = 1,
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.ops = &clk_branch_ops,
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.flags = CLK_SET_RATE_PARENT,
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},
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},
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};
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static struct freq_tbl clk_tbl_ahbix[] = {
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{ 131072000, P_PLL4, 1, 1, 3 },
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{ },
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};
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static struct clk_rcg ahbix_clk = {
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.ns_reg = 0x38,
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.md_reg = 0x3c,
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.mn = {
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.mnctr_en_bit = 8,
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.mnctr_reset_bit = 7,
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.mnctr_mode_shift = 5,
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.n_val_shift = 24,
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.m_val_shift = 8,
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.width = 8,
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},
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.p = {
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.pre_div_shift = 3,
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.pre_div_width = 2,
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},
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.s = {
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.src_sel_shift = 0,
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.parent_map = lcc_pxo_pll4_map,
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},
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.freq_tbl = clk_tbl_ahbix,
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.clkr = {
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.enable_reg = 0x38,
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.enable_mask = BIT(11),
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.hw.init = &(struct clk_init_data){
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.name = "ahbix",
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.parent_names = lcc_pxo_pll4,
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.num_parents = 2,
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.ops = &clk_rcg_lcc_ops,
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},
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},
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};
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static struct clk_regmap *lcc_ipq806x_clks[] = {
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[PLL4] = &pll4.clkr,
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[MI2S_OSR_SRC] = &mi2s_osr_src.clkr,
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[MI2S_OSR_CLK] = &mi2s_osr_clk.clkr,
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[MI2S_DIV_CLK] = &mi2s_div_clk.clkr,
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[MI2S_BIT_DIV_CLK] = &mi2s_bit_div_clk.clkr,
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[MI2S_BIT_CLK] = &mi2s_bit_clk.clkr,
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[PCM_SRC] = &pcm_src.clkr,
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[PCM_CLK_OUT] = &pcm_clk_out.clkr,
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[PCM_CLK] = &pcm_clk.clkr,
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[SPDIF_SRC] = &spdif_src.clkr,
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[SPDIF_CLK] = &spdif_clk.clkr,
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[AHBIX_CLK] = &ahbix_clk.clkr,
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};
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static const struct regmap_config lcc_ipq806x_regmap_config = {
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.reg_bits = 32,
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.reg_stride = 4,
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.val_bits = 32,
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.max_register = 0xfc,
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.fast_io = true,
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};
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static const struct qcom_cc_desc lcc_ipq806x_desc = {
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.config = &lcc_ipq806x_regmap_config,
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.clks = lcc_ipq806x_clks,
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.num_clks = ARRAY_SIZE(lcc_ipq806x_clks),
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};
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static const struct of_device_id lcc_ipq806x_match_table[] = {
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{ .compatible = "qcom,lcc-ipq8064" },
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{ }
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};
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MODULE_DEVICE_TABLE(of, lcc_ipq806x_match_table);
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static int lcc_ipq806x_probe(struct platform_device *pdev)
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{
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u32 val;
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struct regmap *regmap;
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regmap = qcom_cc_map(pdev, &lcc_ipq806x_desc);
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if (IS_ERR(regmap))
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return PTR_ERR(regmap);
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/* Configure the rate of PLL4 if the bootloader hasn't already */
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regmap_read(regmap, 0x0, &val);
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if (!val)
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clk_pll_configure_sr(&pll4, regmap, &pll4_config, true);
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/* Enable PLL4 source on the LPASS Primary PLL Mux */
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regmap_write(regmap, 0xc4, 0x1);
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return qcom_cc_really_probe(pdev, &lcc_ipq806x_desc, regmap);
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}
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static struct platform_driver lcc_ipq806x_driver = {
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.probe = lcc_ipq806x_probe,
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.driver = {
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.name = "lcc-ipq806x",
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.of_match_table = lcc_ipq806x_match_table,
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},
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};
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module_platform_driver(lcc_ipq806x_driver);
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MODULE_DESCRIPTION("QCOM LCC IPQ806x Driver");
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MODULE_LICENSE("GPL v2");
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MODULE_ALIAS("platform:lcc-ipq806x");
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