242 lines
7.1 KiB
C
242 lines
7.1 KiB
C
/*
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* Copyright (C) 2012 Ben Skeggs.
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* All Rights Reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining
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* a copy of this software and associated documentation files (the
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* "Software"), to deal in the Software without restriction, including
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* without limitation the rights to use, copy, modify, merge, publish,
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* distribute, sublicense, and/or sell copies of the Software, and to
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* permit persons to whom the Software is furnished to do so, subject to
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* the following conditions:
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*
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* The above copyright notice and this permission notice (including the
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* next paragraph) shall be included in all copies or substantial
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* portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
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* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
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* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
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* IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
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* LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
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* OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
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* WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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*
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*/
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#include "drmP.h"
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#include "drm.h"
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#include "nouveau_drv.h"
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#include "nouveau_fifo.h"
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#include "nouveau_ramht.h"
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#include "nouveau_vm.h"
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struct nv84_fifo_priv {
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struct nouveau_fifo_priv base;
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struct nouveau_gpuobj *playlist[2];
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int cur_playlist;
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};
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struct nv84_fifo_chan {
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struct nouveau_fifo_chan base;
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struct nouveau_gpuobj *ramfc;
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struct nouveau_gpuobj *cache;
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};
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static int
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nv84_fifo_context_new(struct nouveau_channel *chan, int engine)
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{
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struct nv84_fifo_priv *priv = nv_engine(chan->dev, engine);
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struct nv84_fifo_chan *fctx;
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struct drm_device *dev = chan->dev;
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struct drm_nouveau_private *dev_priv = dev->dev_private;
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u64 ib_offset = chan->pushbuf_base + chan->dma.ib_base * 4;
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u64 instance;
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unsigned long flags;
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int ret;
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fctx = chan->engctx[engine] = kzalloc(sizeof(*fctx), GFP_KERNEL);
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if (!fctx)
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return -ENOMEM;
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atomic_inc(&chan->vm->engref[engine]);
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chan->user = ioremap(pci_resource_start(dev->pdev, 0) +
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NV50_USER(chan->id), PAGE_SIZE);
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if (!chan->user) {
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ret = -ENOMEM;
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goto error;
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}
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ret = nouveau_gpuobj_new(dev, chan, 256, 256, NVOBJ_FLAG_ZERO_ALLOC |
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NVOBJ_FLAG_ZERO_FREE, &fctx->ramfc);
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if (ret)
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goto error;
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instance = fctx->ramfc->vinst >> 8;
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ret = nouveau_gpuobj_new(dev, chan, 4096, 1024, 0, &fctx->cache);
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if (ret)
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goto error;
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nv_wo32(fctx->ramfc, 0x3c, 0x403f6078);
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nv_wo32(fctx->ramfc, 0x40, 0x00000000);
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nv_wo32(fctx->ramfc, 0x44, 0x01003fff);
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nv_wo32(fctx->ramfc, 0x48, chan->pushbuf->cinst >> 4);
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nv_wo32(fctx->ramfc, 0x50, lower_32_bits(ib_offset));
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nv_wo32(fctx->ramfc, 0x54, upper_32_bits(ib_offset) |
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drm_order(chan->dma.ib_max + 1) << 16);
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nv_wo32(fctx->ramfc, 0x60, 0x7fffffff);
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nv_wo32(fctx->ramfc, 0x78, 0x00000000);
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nv_wo32(fctx->ramfc, 0x7c, 0x30000001);
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nv_wo32(fctx->ramfc, 0x80, ((chan->ramht->bits - 9) << 27) |
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(4 << 24) /* SEARCH_FULL */ |
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(chan->ramht->gpuobj->cinst >> 4));
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nv_wo32(fctx->ramfc, 0x88, fctx->cache->vinst >> 10);
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nv_wo32(fctx->ramfc, 0x98, chan->ramin->vinst >> 12);
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nv_wo32(chan->ramin, 0x00, chan->id);
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nv_wo32(chan->ramin, 0x04, fctx->ramfc->vinst >> 8);
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dev_priv->engine.instmem.flush(dev);
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spin_lock_irqsave(&dev_priv->context_switch_lock, flags);
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nv_wr32(dev, 0x002600 + (chan->id * 4), 0x80000000 | instance);
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nv50_fifo_playlist_update(dev);
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spin_unlock_irqrestore(&dev_priv->context_switch_lock, flags);
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error:
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if (ret)
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priv->base.base.context_del(chan, engine);
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return ret;
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}
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static void
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nv84_fifo_context_del(struct nouveau_channel *chan, int engine)
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{
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struct nv84_fifo_chan *fctx = chan->engctx[engine];
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struct drm_device *dev = chan->dev;
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struct drm_nouveau_private *dev_priv = dev->dev_private;
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unsigned long flags;
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/* remove channel from playlist, will context switch if active */
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spin_lock_irqsave(&dev_priv->context_switch_lock, flags);
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nv_mask(dev, 0x002600 + (chan->id * 4), 0x80000000, 0x00000000);
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nv50_fifo_playlist_update(dev);
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/* tell any engines on this channel to unload their contexts */
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nv_wr32(dev, 0x0032fc, chan->ramin->vinst >> 12);
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if (!nv_wait_ne(dev, 0x0032fc, 0xffffffff, 0xffffffff))
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NV_INFO(dev, "PFIFO: channel %d unload timeout\n", chan->id);
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nv_wr32(dev, 0x002600 + (chan->id * 4), 0x00000000);
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spin_unlock_irqrestore(&dev_priv->context_switch_lock, flags);
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/* clean up */
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if (chan->user) {
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iounmap(chan->user);
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chan->user = NULL;
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}
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nouveau_gpuobj_ref(NULL, &fctx->ramfc);
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nouveau_gpuobj_ref(NULL, &fctx->cache);
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atomic_dec(&chan->vm->engref[engine]);
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chan->engctx[engine] = NULL;
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kfree(fctx);
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}
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static int
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nv84_fifo_init(struct drm_device *dev, int engine)
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{
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struct drm_nouveau_private *dev_priv = dev->dev_private;
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struct nv84_fifo_chan *fctx;
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u32 instance;
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int i;
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nv_mask(dev, 0x000200, 0x00000100, 0x00000000);
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nv_mask(dev, 0x000200, 0x00000100, 0x00000100);
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nv_wr32(dev, 0x00250c, 0x6f3cfc34);
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nv_wr32(dev, 0x002044, 0x01003fff);
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nv_wr32(dev, 0x002100, 0xffffffff);
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nv_wr32(dev, 0x002140, 0xffffffff);
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for (i = 0; i < 128; i++) {
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struct nouveau_channel *chan = dev_priv->channels.ptr[i];
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if (chan && (fctx = chan->engctx[engine]))
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instance = 0x80000000 | fctx->ramfc->vinst >> 8;
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else
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instance = 0x00000000;
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nv_wr32(dev, 0x002600 + (i * 4), instance);
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}
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nv50_fifo_playlist_update(dev);
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nv_wr32(dev, 0x003200, 1);
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nv_wr32(dev, 0x003250, 1);
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nv_wr32(dev, 0x002500, 1);
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return 0;
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}
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static int
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nv84_fifo_fini(struct drm_device *dev, int engine, bool suspend)
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{
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struct drm_nouveau_private *dev_priv = dev->dev_private;
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struct nv84_fifo_priv *priv = nv_engine(dev, engine);
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int i;
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/* set playlist length to zero, fifo will unload context */
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nv_wr32(dev, 0x0032ec, 0);
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/* tell all connected engines to unload their contexts */
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for (i = 0; i < priv->base.channels; i++) {
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struct nouveau_channel *chan = dev_priv->channels.ptr[i];
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if (chan)
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nv_wr32(dev, 0x0032fc, chan->ramin->vinst >> 12);
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if (!nv_wait_ne(dev, 0x0032fc, 0xffffffff, 0xffffffff)) {
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NV_INFO(dev, "PFIFO: channel %d unload timeout\n", i);
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return -EBUSY;
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}
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}
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nv_wr32(dev, 0x002140, 0);
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return 0;
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}
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int
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nv84_fifo_create(struct drm_device *dev)
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{
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struct drm_nouveau_private *dev_priv = dev->dev_private;
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struct nv84_fifo_priv *priv;
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int ret;
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priv = kzalloc(sizeof(*priv), GFP_KERNEL);
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if (!priv)
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return -ENOMEM;
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priv->base.base.destroy = nv50_fifo_destroy;
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priv->base.base.init = nv84_fifo_init;
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priv->base.base.fini = nv84_fifo_fini;
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priv->base.base.context_new = nv84_fifo_context_new;
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priv->base.base.context_del = nv84_fifo_context_del;
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priv->base.base.tlb_flush = nv50_fifo_tlb_flush;
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priv->base.channels = 127;
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dev_priv->eng[NVOBJ_ENGINE_FIFO] = &priv->base.base;
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ret = nouveau_gpuobj_new(dev, NULL, priv->base.channels * 4, 0x1000,
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NVOBJ_FLAG_ZERO_ALLOC, &priv->playlist[0]);
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if (ret)
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goto error;
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ret = nouveau_gpuobj_new(dev, NULL, priv->base.channels * 4, 0x1000,
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NVOBJ_FLAG_ZERO_ALLOC, &priv->playlist[1]);
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if (ret)
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goto error;
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nouveau_irq_register(dev, 8, nv04_fifo_isr);
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error:
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if (ret)
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priv->base.base.destroy(dev, NVOBJ_ENGINE_FIFO);
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return ret;
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}
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