110 lines
3.8 KiB
C
110 lines
3.8 KiB
C
/*
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* This file contains the processor specific definitions
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* of the TI DM644x, DM355, DM365, and DM646x.
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*
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* Copyright (C) 2011 Texas Instruments Incorporated
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* Copyright (c) 2007 Deep Root Systems, LLC
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation version 2.
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*
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* This program is distributed "as is" WITHOUT ANY WARRANTY of any
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* kind, whether express or implied; without even the implied warranty
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* of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#ifndef __DAVINCI_H
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#define __DAVINCI_H
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#include <linux/clk.h>
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#include <linux/videodev2.h>
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#include <linux/davinci_emac.h>
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#include <linux/platform_device.h>
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#include <linux/spi/spi.h>
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#include <linux/platform_data/davinci_asp.h>
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#include <linux/platform_data/keyscan-davinci.h>
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#include <mach/hardware.h>
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#include <mach/edma.h>
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#include <media/davinci/vpfe_capture.h>
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#include <media/davinci/vpif_types.h>
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#include <media/davinci/vpss.h>
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#include <media/davinci/vpbe_types.h>
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#include <media/davinci/vpbe_venc.h>
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#include <media/davinci/vpbe.h>
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#include <media/davinci/vpbe_osd.h>
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#define DAVINCI_SYSTEM_MODULE_BASE 0x01c40000
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#define SYSMOD_VDAC_CONFIG 0x2c
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#define SYSMOD_VIDCLKCTL 0x38
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#define SYSMOD_VPSS_CLKCTL 0x44
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#define SYSMOD_VDD3P3VPWDN 0x48
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#define SYSMOD_VSCLKDIS 0x6c
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#define SYSMOD_PUPDCTL1 0x7c
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/* VPSS CLKCTL bit definitions */
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#define VPSS_MUXSEL_EXTCLK_ENABLE BIT(1)
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#define VPSS_VENCCLKEN_ENABLE BIT(3)
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#define VPSS_DACCLKEN_ENABLE BIT(4)
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#define VPSS_PLLC2SYSCLK5_ENABLE BIT(5)
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extern void __iomem *davinci_sysmod_base;
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#define DAVINCI_SYSMOD_VIRT(x) (davinci_sysmod_base + (x))
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void davinci_map_sysmod(void);
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/* DM355 base addresses */
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#define DM355_ASYNC_EMIF_CONTROL_BASE 0x01e10000
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#define DM355_ASYNC_EMIF_DATA_CE0_BASE 0x02000000
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#define ASP1_TX_EVT_EN 1
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#define ASP1_RX_EVT_EN 2
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/* DM365 base addresses */
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#define DM365_ASYNC_EMIF_CONTROL_BASE 0x01d10000
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#define DM365_ASYNC_EMIF_DATA_CE0_BASE 0x02000000
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#define DM365_ASYNC_EMIF_DATA_CE1_BASE 0x04000000
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/* DM644x base addresses */
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#define DM644X_ASYNC_EMIF_CONTROL_BASE 0x01e00000
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#define DM644X_ASYNC_EMIF_DATA_CE0_BASE 0x02000000
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#define DM644X_ASYNC_EMIF_DATA_CE1_BASE 0x04000000
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#define DM644X_ASYNC_EMIF_DATA_CE2_BASE 0x06000000
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#define DM644X_ASYNC_EMIF_DATA_CE3_BASE 0x08000000
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/* DM646x base addresses */
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#define DM646X_ASYNC_EMIF_CONTROL_BASE 0x20008000
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#define DM646X_ASYNC_EMIF_CS2_SPACE_BASE 0x42000000
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/* DM355 function declarations */
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void __init dm355_init(void);
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void dm355_init_spi0(unsigned chipselect_mask,
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const struct spi_board_info *info, unsigned len);
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void __init dm355_init_asp1(u32 evt_enable, struct snd_platform_data *pdata);
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int dm355_init_video(struct vpfe_config *, struct vpbe_config *);
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/* DM365 function declarations */
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void __init dm365_init(void);
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void __init dm365_init_asp(struct snd_platform_data *pdata);
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void __init dm365_init_vc(struct snd_platform_data *pdata);
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void __init dm365_init_ks(struct davinci_ks_platform_data *pdata);
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void __init dm365_init_rtc(void);
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void dm365_init_spi0(unsigned chipselect_mask,
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const struct spi_board_info *info, unsigned len);
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int dm365_init_video(struct vpfe_config *, struct vpbe_config *);
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/* DM644x function declarations */
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void __init dm644x_init(void);
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void __init dm644x_init_asp(struct snd_platform_data *pdata);
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int __init dm644x_init_video(struct vpfe_config *, struct vpbe_config *);
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/* DM646x function declarations */
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void __init dm646x_init(void);
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void __init dm646x_init_mcasp0(struct snd_platform_data *pdata);
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void __init dm646x_init_mcasp1(struct snd_platform_data *pdata);
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int __init dm646x_init_edma(struct edma_rsv_info *rsv);
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void dm646x_video_init(void);
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void dm646x_setup_vpif(struct vpif_display_config *,
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struct vpif_capture_config *);
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#endif /*__DAVINCI_H */
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