286 lines
6.9 KiB
C
286 lines
6.9 KiB
C
/*
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* Shared support code for AMD K8 northbridges and derivates.
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* Copyright 2006 Andi Kleen, SUSE Labs. Subject to GPLv2.
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*/
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#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
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#include <linux/types.h>
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#include <linux/slab.h>
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#include <linux/init.h>
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#include <linux/errno.h>
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#include <linux/module.h>
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#include <linux/spinlock.h>
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#include <asm/amd_nb.h>
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static u32 *flush_words;
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const struct pci_device_id amd_nb_misc_ids[] = {
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{ PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_K8_NB_MISC) },
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{ PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_10H_NB_MISC) },
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{ PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_15H_NB_F3) },
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{ PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_15H_M10H_F3) },
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{}
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};
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EXPORT_SYMBOL(amd_nb_misc_ids);
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static struct pci_device_id amd_nb_link_ids[] = {
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{ PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_15H_NB_F4) },
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{}
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};
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const struct amd_nb_bus_dev_range amd_nb_bus_dev_ranges[] __initconst = {
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{ 0x00, 0x18, 0x20 },
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{ 0xff, 0x00, 0x20 },
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{ 0xfe, 0x00, 0x20 },
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{ }
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};
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struct amd_northbridge_info amd_northbridges;
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EXPORT_SYMBOL(amd_northbridges);
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static struct pci_dev *next_northbridge(struct pci_dev *dev,
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const struct pci_device_id *ids)
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{
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do {
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dev = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, dev);
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if (!dev)
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break;
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} while (!pci_match_id(ids, dev));
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return dev;
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}
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int amd_cache_northbridges(void)
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{
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u16 i = 0;
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struct amd_northbridge *nb;
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struct pci_dev *misc, *link;
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if (amd_nb_num())
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return 0;
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misc = NULL;
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while ((misc = next_northbridge(misc, amd_nb_misc_ids)) != NULL)
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i++;
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if (i == 0)
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return 0;
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nb = kzalloc(i * sizeof(struct amd_northbridge), GFP_KERNEL);
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if (!nb)
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return -ENOMEM;
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amd_northbridges.nb = nb;
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amd_northbridges.num = i;
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link = misc = NULL;
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for (i = 0; i != amd_nb_num(); i++) {
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node_to_amd_nb(i)->misc = misc =
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next_northbridge(misc, amd_nb_misc_ids);
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node_to_amd_nb(i)->link = link =
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next_northbridge(link, amd_nb_link_ids);
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}
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/* some CPU families (e.g. family 0x11) do not support GART */
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if (boot_cpu_data.x86 == 0xf || boot_cpu_data.x86 == 0x10 ||
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boot_cpu_data.x86 == 0x15)
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amd_northbridges.flags |= AMD_NB_GART;
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/*
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* Some CPU families support L3 Cache Index Disable. There are some
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* limitations because of E382 and E388 on family 0x10.
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*/
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if (boot_cpu_data.x86 == 0x10 &&
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boot_cpu_data.x86_model >= 0x8 &&
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(boot_cpu_data.x86_model > 0x9 ||
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boot_cpu_data.x86_mask >= 0x1))
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amd_northbridges.flags |= AMD_NB_L3_INDEX_DISABLE;
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if (boot_cpu_data.x86 == 0x15)
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amd_northbridges.flags |= AMD_NB_L3_INDEX_DISABLE;
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/* L3 cache partitioning is supported on family 0x15 */
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if (boot_cpu_data.x86 == 0x15)
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amd_northbridges.flags |= AMD_NB_L3_PARTITIONING;
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return 0;
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}
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EXPORT_SYMBOL_GPL(amd_cache_northbridges);
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/*
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* Ignores subdevice/subvendor but as far as I can figure out
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* they're useless anyways
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*/
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bool __init early_is_amd_nb(u32 device)
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{
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const struct pci_device_id *id;
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u32 vendor = device & 0xffff;
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device >>= 16;
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for (id = amd_nb_misc_ids; id->vendor; id++)
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if (vendor == id->vendor && device == id->device)
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return true;
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return false;
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}
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struct resource *amd_get_mmconfig_range(struct resource *res)
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{
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u32 address;
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u64 base, msr;
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unsigned segn_busn_bits;
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if (boot_cpu_data.x86_vendor != X86_VENDOR_AMD)
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return NULL;
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/* assume all cpus from fam10h have mmconfig */
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if (boot_cpu_data.x86 < 0x10)
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return NULL;
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address = MSR_FAM10H_MMIO_CONF_BASE;
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rdmsrl(address, msr);
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/* mmconfig is not enabled */
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if (!(msr & FAM10H_MMIO_CONF_ENABLE))
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return NULL;
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base = msr & (FAM10H_MMIO_CONF_BASE_MASK<<FAM10H_MMIO_CONF_BASE_SHIFT);
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segn_busn_bits = (msr >> FAM10H_MMIO_CONF_BUSRANGE_SHIFT) &
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FAM10H_MMIO_CONF_BUSRANGE_MASK;
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res->flags = IORESOURCE_MEM;
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res->start = base;
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res->end = base + (1ULL<<(segn_busn_bits + 20)) - 1;
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return res;
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}
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int amd_get_subcaches(int cpu)
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{
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struct pci_dev *link = node_to_amd_nb(amd_get_nb_id(cpu))->link;
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unsigned int mask;
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int cuid;
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if (!amd_nb_has_feature(AMD_NB_L3_PARTITIONING))
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return 0;
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pci_read_config_dword(link, 0x1d4, &mask);
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cuid = cpu_data(cpu).compute_unit_id;
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return (mask >> (4 * cuid)) & 0xf;
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}
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int amd_set_subcaches(int cpu, int mask)
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{
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static unsigned int reset, ban;
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struct amd_northbridge *nb = node_to_amd_nb(amd_get_nb_id(cpu));
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unsigned int reg;
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int cuid;
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if (!amd_nb_has_feature(AMD_NB_L3_PARTITIONING) || mask > 0xf)
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return -EINVAL;
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/* if necessary, collect reset state of L3 partitioning and BAN mode */
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if (reset == 0) {
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pci_read_config_dword(nb->link, 0x1d4, &reset);
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pci_read_config_dword(nb->misc, 0x1b8, &ban);
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ban &= 0x180000;
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}
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/* deactivate BAN mode if any subcaches are to be disabled */
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if (mask != 0xf) {
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pci_read_config_dword(nb->misc, 0x1b8, ®);
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pci_write_config_dword(nb->misc, 0x1b8, reg & ~0x180000);
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}
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cuid = cpu_data(cpu).compute_unit_id;
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mask <<= 4 * cuid;
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mask |= (0xf ^ (1 << cuid)) << 26;
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pci_write_config_dword(nb->link, 0x1d4, mask);
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/* reset BAN mode if L3 partitioning returned to reset state */
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pci_read_config_dword(nb->link, 0x1d4, ®);
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if (reg == reset) {
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pci_read_config_dword(nb->misc, 0x1b8, ®);
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reg &= ~0x180000;
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pci_write_config_dword(nb->misc, 0x1b8, reg | ban);
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}
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return 0;
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}
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static int amd_cache_gart(void)
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{
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u16 i;
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if (!amd_nb_has_feature(AMD_NB_GART))
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return 0;
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flush_words = kmalloc(amd_nb_num() * sizeof(u32), GFP_KERNEL);
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if (!flush_words) {
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amd_northbridges.flags &= ~AMD_NB_GART;
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return -ENOMEM;
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}
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for (i = 0; i != amd_nb_num(); i++)
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pci_read_config_dword(node_to_amd_nb(i)->misc, 0x9c,
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&flush_words[i]);
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return 0;
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}
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void amd_flush_garts(void)
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{
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int flushed, i;
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unsigned long flags;
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static DEFINE_SPINLOCK(gart_lock);
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if (!amd_nb_has_feature(AMD_NB_GART))
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return;
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/* Avoid races between AGP and IOMMU. In theory it's not needed
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but I'm not sure if the hardware won't lose flush requests
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when another is pending. This whole thing is so expensive anyways
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that it doesn't matter to serialize more. -AK */
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spin_lock_irqsave(&gart_lock, flags);
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flushed = 0;
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for (i = 0; i < amd_nb_num(); i++) {
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pci_write_config_dword(node_to_amd_nb(i)->misc, 0x9c,
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flush_words[i] | 1);
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flushed++;
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}
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for (i = 0; i < amd_nb_num(); i++) {
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u32 w;
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/* Make sure the hardware actually executed the flush*/
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for (;;) {
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pci_read_config_dword(node_to_amd_nb(i)->misc,
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0x9c, &w);
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if (!(w & 1))
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break;
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cpu_relax();
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}
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}
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spin_unlock_irqrestore(&gart_lock, flags);
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if (!flushed)
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pr_notice("nothing to flush?\n");
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}
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EXPORT_SYMBOL_GPL(amd_flush_garts);
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static __init int init_amd_nbs(void)
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{
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int err = 0;
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err = amd_cache_northbridges();
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if (err < 0)
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pr_notice("Cannot enumerate AMD northbridges\n");
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if (amd_cache_gart() < 0)
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pr_notice("Cannot initialize GART flush words, GART support disabled\n");
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return err;
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}
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/* This has to go after the PCI subsystem */
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fs_initcall(init_amd_nbs);
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