260 lines
6.1 KiB
C
260 lines
6.1 KiB
C
/*
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* APIC driver for "bigsmp" xAPIC machines with more than 8 virtual CPUs.
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*
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* Drives the local APIC in "clustered mode".
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*/
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#include <linux/threads.h>
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#include <linux/cpumask.h>
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#include <linux/kernel.h>
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#include <linux/init.h>
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#include <linux/dmi.h>
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#include <linux/smp.h>
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#include <asm/apicdef.h>
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#include <asm/fixmap.h>
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#include <asm/mpspec.h>
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#include <asm/apic.h>
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#include <asm/ipi.h>
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static unsigned bigsmp_get_apic_id(unsigned long x)
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{
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return (x >> 24) & 0xFF;
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}
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static int bigsmp_apic_id_registered(void)
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{
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return 1;
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}
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static const struct cpumask *bigsmp_target_cpus(void)
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{
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#ifdef CONFIG_SMP
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return cpu_online_mask;
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#else
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return cpumask_of(0);
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#endif
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}
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static unsigned long bigsmp_check_apicid_used(physid_mask_t *map, int apicid)
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{
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return 0;
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}
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static unsigned long bigsmp_check_apicid_present(int bit)
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{
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return 1;
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}
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static inline unsigned long calculate_ldr(int cpu)
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{
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unsigned long val, id;
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val = apic_read(APIC_LDR) & ~APIC_LDR_MASK;
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id = per_cpu(x86_bios_cpu_apicid, cpu);
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val |= SET_APIC_LOGICAL_ID(id);
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return val;
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}
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/*
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* Set up the logical destination ID.
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*
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* Intel recommends to set DFR, LDR and TPR before enabling
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* an APIC. See e.g. "AP-388 82489DX User's Manual" (Intel
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* document number 292116). So here it goes...
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*/
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static void bigsmp_init_apic_ldr(void)
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{
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unsigned long val;
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int cpu = smp_processor_id();
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apic_write(APIC_DFR, APIC_DFR_FLAT);
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val = calculate_ldr(cpu);
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apic_write(APIC_LDR, val);
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}
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static void bigsmp_setup_apic_routing(void)
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{
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printk(KERN_INFO
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"Enabling APIC mode: Physflat. Using %d I/O APICs\n",
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nr_ioapics);
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}
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static int bigsmp_apicid_to_node(int logical_apicid)
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{
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return apicid_2_node[hard_smp_processor_id()];
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}
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static int bigsmp_cpu_present_to_apicid(int mps_cpu)
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{
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if (mps_cpu < nr_cpu_ids)
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return (int) per_cpu(x86_bios_cpu_apicid, mps_cpu);
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return BAD_APICID;
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}
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/* Mapping from cpu number to logical apicid */
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static inline int bigsmp_cpu_to_logical_apicid(int cpu)
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{
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if (cpu >= nr_cpu_ids)
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return BAD_APICID;
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return cpu_physical_id(cpu);
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}
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static void bigsmp_ioapic_phys_id_map(physid_mask_t *phys_map, physid_mask_t *retmap)
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{
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/* For clustered we don't have a good way to do this yet - hack */
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physids_promote(0xFFL, retmap);
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}
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static int bigsmp_check_phys_apicid_present(int phys_apicid)
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{
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return 1;
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}
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/* As we are using single CPU as destination, pick only one CPU here */
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static unsigned int bigsmp_cpu_mask_to_apicid(const struct cpumask *cpumask)
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{
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return bigsmp_cpu_to_logical_apicid(cpumask_first(cpumask));
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}
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static unsigned int bigsmp_cpu_mask_to_apicid_and(const struct cpumask *cpumask,
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const struct cpumask *andmask)
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{
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int cpu;
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/*
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* We're using fixed IRQ delivery, can only return one phys APIC ID.
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* May as well be the first.
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*/
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for_each_cpu_and(cpu, cpumask, andmask) {
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if (cpumask_test_cpu(cpu, cpu_online_mask))
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break;
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}
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return bigsmp_cpu_to_logical_apicid(cpu);
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}
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static int bigsmp_phys_pkg_id(int cpuid_apic, int index_msb)
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{
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return cpuid_apic >> index_msb;
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}
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static inline void bigsmp_send_IPI_mask(const struct cpumask *mask, int vector)
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{
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default_send_IPI_mask_sequence_phys(mask, vector);
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}
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static void bigsmp_send_IPI_allbutself(int vector)
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{
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default_send_IPI_mask_allbutself_phys(cpu_online_mask, vector);
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}
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static void bigsmp_send_IPI_all(int vector)
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{
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bigsmp_send_IPI_mask(cpu_online_mask, vector);
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}
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static int dmi_bigsmp; /* can be set by dmi scanners */
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static int hp_ht_bigsmp(const struct dmi_system_id *d)
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{
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printk(KERN_NOTICE "%s detected: force use of apic=bigsmp\n", d->ident);
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dmi_bigsmp = 1;
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return 0;
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}
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static const struct dmi_system_id bigsmp_dmi_table[] = {
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{ hp_ht_bigsmp, "HP ProLiant DL760 G2",
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{ DMI_MATCH(DMI_BIOS_VENDOR, "HP"),
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DMI_MATCH(DMI_BIOS_VERSION, "P44-"),
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}
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},
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{ hp_ht_bigsmp, "HP ProLiant DL740",
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{ DMI_MATCH(DMI_BIOS_VENDOR, "HP"),
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DMI_MATCH(DMI_BIOS_VERSION, "P47-"),
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}
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},
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{ } /* NULL entry stops DMI scanning */
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};
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static void bigsmp_vector_allocation_domain(int cpu, struct cpumask *retmask)
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{
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cpumask_clear(retmask);
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cpumask_set_cpu(cpu, retmask);
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}
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static int probe_bigsmp(void)
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{
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if (def_to_bigsmp)
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dmi_bigsmp = 1;
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else
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dmi_check_system(bigsmp_dmi_table);
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return dmi_bigsmp;
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}
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struct apic apic_bigsmp = {
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.name = "bigsmp",
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.probe = probe_bigsmp,
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.acpi_madt_oem_check = NULL,
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.apic_id_registered = bigsmp_apic_id_registered,
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.irq_delivery_mode = dest_Fixed,
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/* phys delivery to target CPU: */
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.irq_dest_mode = 0,
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.target_cpus = bigsmp_target_cpus,
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.disable_esr = 1,
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.dest_logical = 0,
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.check_apicid_used = bigsmp_check_apicid_used,
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.check_apicid_present = bigsmp_check_apicid_present,
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.vector_allocation_domain = bigsmp_vector_allocation_domain,
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.init_apic_ldr = bigsmp_init_apic_ldr,
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.ioapic_phys_id_map = bigsmp_ioapic_phys_id_map,
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.setup_apic_routing = bigsmp_setup_apic_routing,
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.multi_timer_check = NULL,
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.apicid_to_node = bigsmp_apicid_to_node,
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.cpu_to_logical_apicid = bigsmp_cpu_to_logical_apicid,
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.cpu_present_to_apicid = bigsmp_cpu_present_to_apicid,
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.apicid_to_cpu_present = physid_set_mask_of_physid,
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.setup_portio_remap = NULL,
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.check_phys_apicid_present = bigsmp_check_phys_apicid_present,
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.enable_apic_mode = NULL,
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.phys_pkg_id = bigsmp_phys_pkg_id,
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.mps_oem_check = NULL,
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.get_apic_id = bigsmp_get_apic_id,
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.set_apic_id = NULL,
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.apic_id_mask = 0xFF << 24,
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.cpu_mask_to_apicid = bigsmp_cpu_mask_to_apicid,
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.cpu_mask_to_apicid_and = bigsmp_cpu_mask_to_apicid_and,
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.send_IPI_mask = bigsmp_send_IPI_mask,
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.send_IPI_mask_allbutself = NULL,
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.send_IPI_allbutself = bigsmp_send_IPI_allbutself,
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.send_IPI_all = bigsmp_send_IPI_all,
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.send_IPI_self = default_send_IPI_self,
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.trampoline_phys_low = DEFAULT_TRAMPOLINE_PHYS_LOW,
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.trampoline_phys_high = DEFAULT_TRAMPOLINE_PHYS_HIGH,
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.wait_for_init_deassert = default_wait_for_init_deassert,
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.smp_callin_clear_local_apic = NULL,
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.inquire_remote_apic = default_inquire_remote_apic,
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.read = native_apic_mem_read,
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.write = native_apic_mem_write,
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.icr_read = native_apic_icr_read,
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.icr_write = native_apic_icr_write,
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.wait_icr_idle = native_apic_wait_icr_idle,
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.safe_wait_icr_idle = native_safe_apic_wait_icr_idle,
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};
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