295 lines
7.1 KiB
C
295 lines
7.1 KiB
C
/*
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* at91sam926x_time.c - Periodic Interval Timer (PIT) for at91sam926x
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*
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* Copyright (C) 2005-2006 M. Amine SAYA, ATMEL Rousset, France
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* Revision 2005 M. Nicolas Diremdjian, ATMEL Rousset, France
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* Converted to ClockSource/ClockEvents by David Brownell.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#include <linux/interrupt.h>
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#include <linux/irq.h>
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#include <linux/kernel.h>
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#include <linux/clk.h>
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#include <linux/clockchips.h>
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#include <linux/of.h>
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#include <linux/of_address.h>
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#include <linux/of_irq.h>
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#include <asm/mach/time.h>
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#include <mach/hardware.h>
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#define AT91_PIT_MR 0x00 /* Mode Register */
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#define AT91_PIT_PITIEN (1 << 25) /* Timer Interrupt Enable */
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#define AT91_PIT_PITEN (1 << 24) /* Timer Enabled */
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#define AT91_PIT_PIV (0xfffff) /* Periodic Interval Value */
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#define AT91_PIT_SR 0x04 /* Status Register */
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#define AT91_PIT_PITS (1 << 0) /* Timer Status */
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#define AT91_PIT_PIVR 0x08 /* Periodic Interval Value Register */
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#define AT91_PIT_PIIR 0x0c /* Periodic Interval Image Register */
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#define AT91_PIT_PICNT (0xfff << 20) /* Interval Counter */
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#define AT91_PIT_CPIV (0xfffff) /* Inverval Value */
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#define PIT_CPIV(x) ((x) & AT91_PIT_CPIV)
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#define PIT_PICNT(x) (((x) & AT91_PIT_PICNT) >> 20)
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static u32 pit_cycle; /* write-once */
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static u32 pit_cnt; /* access only w/system irq blocked */
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static void __iomem *pit_base_addr __read_mostly;
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static struct clk *mck;
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static inline unsigned int pit_read(unsigned int reg_offset)
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{
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return __raw_readl(pit_base_addr + reg_offset);
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}
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static inline void pit_write(unsigned int reg_offset, unsigned long value)
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{
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__raw_writel(value, pit_base_addr + reg_offset);
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}
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/*
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* Clocksource: just a monotonic counter of MCK/16 cycles.
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* We don't care whether or not PIT irqs are enabled.
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*/
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static cycle_t read_pit_clk(struct clocksource *cs)
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{
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unsigned long flags;
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u32 elapsed;
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u32 t;
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raw_local_irq_save(flags);
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elapsed = pit_cnt;
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t = pit_read(AT91_PIT_PIIR);
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raw_local_irq_restore(flags);
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elapsed += PIT_PICNT(t) * pit_cycle;
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elapsed += PIT_CPIV(t);
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return elapsed;
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}
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static struct clocksource pit_clk = {
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.name = "pit",
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.rating = 175,
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.read = read_pit_clk,
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.flags = CLOCK_SOURCE_IS_CONTINUOUS,
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};
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/*
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* Clockevent device: interrupts every 1/HZ (== pit_cycles * MCK/16)
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*/
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static void
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pit_clkevt_mode(enum clock_event_mode mode, struct clock_event_device *dev)
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{
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switch (mode) {
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case CLOCK_EVT_MODE_PERIODIC:
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/* update clocksource counter */
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pit_cnt += pit_cycle * PIT_PICNT(pit_read(AT91_PIT_PIVR));
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pit_write(AT91_PIT_MR, (pit_cycle - 1) | AT91_PIT_PITEN
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| AT91_PIT_PITIEN);
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break;
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case CLOCK_EVT_MODE_ONESHOT:
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BUG();
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/* FALLTHROUGH */
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case CLOCK_EVT_MODE_SHUTDOWN:
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case CLOCK_EVT_MODE_UNUSED:
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/* disable irq, leaving the clocksource active */
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pit_write(AT91_PIT_MR, (pit_cycle - 1) | AT91_PIT_PITEN);
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break;
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case CLOCK_EVT_MODE_RESUME:
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break;
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}
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}
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static void at91sam926x_pit_suspend(struct clock_event_device *cedev)
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{
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/* Disable timer */
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pit_write(AT91_PIT_MR, 0);
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}
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static void at91sam926x_pit_reset(void)
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{
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/* Disable timer and irqs */
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pit_write(AT91_PIT_MR, 0);
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/* Clear any pending interrupts, wait for PIT to stop counting */
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while (PIT_CPIV(pit_read(AT91_PIT_PIVR)) != 0)
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cpu_relax();
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/* Start PIT but don't enable IRQ */
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pit_write(AT91_PIT_MR, (pit_cycle - 1) | AT91_PIT_PITEN);
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}
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static void at91sam926x_pit_resume(struct clock_event_device *cedev)
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{
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at91sam926x_pit_reset();
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}
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static struct clock_event_device pit_clkevt = {
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.name = "pit",
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.features = CLOCK_EVT_FEAT_PERIODIC,
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.shift = 32,
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.rating = 100,
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.set_mode = pit_clkevt_mode,
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.suspend = at91sam926x_pit_suspend,
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.resume = at91sam926x_pit_resume,
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};
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/*
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* IRQ handler for the timer.
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*/
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static irqreturn_t at91sam926x_pit_interrupt(int irq, void *dev_id)
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{
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/*
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* irqs should be disabled here, but as the irq is shared they are only
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* guaranteed to be off if the timer irq is registered first.
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*/
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WARN_ON_ONCE(!irqs_disabled());
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/* The PIT interrupt may be disabled, and is shared */
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if ((pit_clkevt.mode == CLOCK_EVT_MODE_PERIODIC)
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&& (pit_read(AT91_PIT_SR) & AT91_PIT_PITS)) {
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unsigned nr_ticks;
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/* Get number of ticks performed before irq, and ack it */
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nr_ticks = PIT_PICNT(pit_read(AT91_PIT_PIVR));
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do {
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pit_cnt += pit_cycle;
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pit_clkevt.event_handler(&pit_clkevt);
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nr_ticks--;
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} while (nr_ticks);
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return IRQ_HANDLED;
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}
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return IRQ_NONE;
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}
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static struct irqaction at91sam926x_pit_irq = {
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.name = "at91_tick",
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.flags = IRQF_SHARED | IRQF_TIMER | IRQF_IRQPOLL,
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.handler = at91sam926x_pit_interrupt,
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.irq = NR_IRQS_LEGACY + AT91_ID_SYS,
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};
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#ifdef CONFIG_OF
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static struct of_device_id pit_timer_ids[] = {
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{ .compatible = "atmel,at91sam9260-pit" },
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{ /* sentinel */ }
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};
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static int __init of_at91sam926x_pit_init(void)
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{
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struct device_node *np;
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int ret;
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np = of_find_matching_node(NULL, pit_timer_ids);
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if (!np)
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goto err;
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pit_base_addr = of_iomap(np, 0);
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if (!pit_base_addr)
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goto node_err;
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mck = of_clk_get(np, 0);
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/* Get the interrupts property */
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ret = irq_of_parse_and_map(np, 0);
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if (!ret) {
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pr_crit("AT91: PIT: Unable to get IRQ from DT\n");
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if (!IS_ERR(mck))
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clk_put(mck);
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goto ioremap_err;
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}
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at91sam926x_pit_irq.irq = ret;
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of_node_put(np);
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return 0;
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ioremap_err:
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iounmap(pit_base_addr);
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node_err:
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of_node_put(np);
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err:
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return -EINVAL;
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}
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#else
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static int __init of_at91sam926x_pit_init(void)
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{
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return -EINVAL;
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}
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#endif
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/*
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* Set up both clocksource and clockevent support.
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*/
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void __init at91sam926x_pit_init(void)
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{
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unsigned long pit_rate;
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unsigned bits;
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int ret;
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mck = ERR_PTR(-ENOENT);
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/* For device tree enabled device: initialize here */
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of_at91sam926x_pit_init();
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/*
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* Use our actual MCK to figure out how many MCK/16 ticks per
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* 1/HZ period (instead of a compile-time constant LATCH).
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*/
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if (IS_ERR(mck))
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mck = clk_get(NULL, "mck");
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if (IS_ERR(mck))
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panic("AT91: PIT: Unable to get mck clk\n");
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pit_rate = clk_get_rate(mck) / 16;
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pit_cycle = (pit_rate + HZ/2) / HZ;
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WARN_ON(((pit_cycle - 1) & ~AT91_PIT_PIV) != 0);
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/* Initialize and enable the timer */
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at91sam926x_pit_reset();
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/*
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* Register clocksource. The high order bits of PIV are unused,
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* so this isn't a 32-bit counter unless we get clockevent irqs.
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*/
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bits = 12 /* PICNT */ + ilog2(pit_cycle) /* PIV */;
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pit_clk.mask = CLOCKSOURCE_MASK(bits);
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clocksource_register_hz(&pit_clk, pit_rate);
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/* Set up irq handler */
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ret = setup_irq(at91sam926x_pit_irq.irq, &at91sam926x_pit_irq);
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if (ret)
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pr_crit("AT91: PIT: Unable to setup IRQ\n");
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/* Set up and register clockevents */
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pit_clkevt.mult = div_sc(pit_rate, NSEC_PER_SEC, pit_clkevt.shift);
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pit_clkevt.cpumask = cpumask_of(0);
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clockevents_register_device(&pit_clkevt);
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}
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void __init at91sam926x_ioremap_pit(u32 addr)
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{
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#if defined(CONFIG_OF)
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struct device_node *np =
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of_find_matching_node(NULL, pit_timer_ids);
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if (np) {
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of_node_put(np);
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return;
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}
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#endif
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pit_base_addr = ioremap(addr, 16);
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if (!pit_base_addr)
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panic("Impossible to ioremap PIT\n");
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}
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