351 lines
8.3 KiB
C
351 lines
8.3 KiB
C
/*
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* arch/ppc/platforms/82xx/pq2ads_pd.c
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*
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* MPC82xx Board-specific PlatformDevice descriptions
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*
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* 2005 (c) MontaVista Software, Inc.
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* Vitaly Bordug <vbordug@ru.mvista.com>
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*
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* This file is licensed under the terms of the GNU General Public License
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* version 2. This program is licensed "as is" without any warranty of any
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* kind, whether express or implied.
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*/
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#include <linux/init.h>
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#include <linux/module.h>
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#include <linux/device.h>
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#include <linux/ioport.h>
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#include <linux/fs_enet_pd.h>
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#include <linux/platform_device.h>
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#include <asm/io.h>
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#include <asm/mpc8260.h>
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#include <asm/cpm2.h>
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#include <asm/immap_cpm2.h>
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#include <asm/irq.h>
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#include <asm/ppc_sys.h>
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#include <asm/ppcboot.h>
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#include <linux/fs_uart_pd.h>
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#include "pq2ads_pd.h"
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static void init_fcc1_ioports(void);
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static void init_fcc2_ioports(void);
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static void init_scc1_uart_ioports(void);
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static void init_scc4_uart_ioports(void);
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static struct fs_uart_platform_info mpc8272_uart_pdata[] = {
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[fsid_scc1_uart] = {
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.init_ioports = init_scc1_uart_ioports,
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.fs_no = fsid_scc1_uart,
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.brg = 1,
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.tx_num_fifo = 4,
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.tx_buf_size = 32,
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.rx_num_fifo = 4,
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.rx_buf_size = 32,
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},
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[fsid_scc4_uart] = {
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.init_ioports = init_scc4_uart_ioports,
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.fs_no = fsid_scc4_uart,
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.brg = 4,
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.tx_num_fifo = 4,
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.tx_buf_size = 32,
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.rx_num_fifo = 4,
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.rx_buf_size = 32,
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},
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};
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static struct fs_mii_bus_info mii_bus_info = {
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.method = fsmii_bitbang,
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.id = 0,
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.i.bitbang = {
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.mdio_port = fsiop_portc,
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.mdio_bit = 18,
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.mdc_port = fsiop_portc,
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.mdc_bit = 19,
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.delay = 1,
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},
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};
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static struct fs_platform_info mpc82xx_fcc1_pdata = {
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.fs_no = fsid_fcc1,
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.cp_page = CPM_CR_FCC1_PAGE,
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.cp_block = CPM_CR_FCC1_SBLOCK,
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.clk_trx = (PC_F1RXCLK | PC_F1TXCLK),
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.clk_route = CMX1_CLK_ROUTE,
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.clk_mask = CMX1_CLK_MASK,
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.init_ioports = init_fcc1_ioports,
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.phy_addr = 0,
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#ifdef PHY_INTERRUPT
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.phy_irq = PHY_INTERRUPT,
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#else
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.phy_irq = -1;
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#endif
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.mem_offset = FCC1_MEM_OFFSET,
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.bus_info = &mii_bus_info,
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.rx_ring = 32,
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.tx_ring = 32,
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.rx_copybreak = 240,
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.use_napi = 0,
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.napi_weight = 17,
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};
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static struct fs_platform_info mpc82xx_fcc2_pdata = {
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.fs_no = fsid_fcc2,
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.cp_page = CPM_CR_FCC2_PAGE,
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.cp_block = CPM_CR_FCC2_SBLOCK,
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.clk_trx = (PC_F2RXCLK | PC_F2TXCLK),
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.clk_route = CMX2_CLK_ROUTE,
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.clk_mask = CMX2_CLK_MASK,
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.init_ioports = init_fcc2_ioports,
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.phy_addr = 3,
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#ifdef PHY_INTERRUPT
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.phy_irq = PHY_INTERRUPT,
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#else
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.phy_irq = -1;
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#endif
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.mem_offset = FCC2_MEM_OFFSET,
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.bus_info = &mii_bus_info,
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.rx_ring = 32,
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.tx_ring = 32,
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.rx_copybreak = 240,
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.use_napi = 0,
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.napi_weight = 17,
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};
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static void init_fcc1_ioports(void)
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{
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struct io_port *io;
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u32 tempval;
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cpm2_map_t* immap = ioremap(CPM_MAP_ADDR, sizeof(cpm2_map_t));
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u32 *bcsr = ioremap(BCSR_ADDR+4, sizeof(u32));
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io = &immap->im_ioport;
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/* Enable the PHY */
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clrbits32(bcsr, BCSR1_FETHIEN);
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setbits32(bcsr, BCSR1_FETH_RST);
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/* FCC1 pins are on port A/C. */
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/* Configure port A and C pins for FCC1 Ethernet. */
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tempval = in_be32(&io->iop_pdira);
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tempval &= ~PA1_DIRA0;
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tempval |= PA1_DIRA1;
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out_be32(&io->iop_pdira, tempval);
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tempval = in_be32(&io->iop_psora);
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tempval &= ~PA1_PSORA0;
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tempval |= PA1_PSORA1;
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out_be32(&io->iop_psora, tempval);
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setbits32(&io->iop_ppara,PA1_DIRA0 | PA1_DIRA1);
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/* Alter clocks */
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tempval = PC_F1TXCLK|PC_F1RXCLK;
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clrbits32(&io->iop_psorc, tempval);
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clrbits32(&io->iop_pdirc, tempval);
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setbits32(&io->iop_pparc, tempval);
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clrbits32(&immap->im_cpmux.cmx_fcr, CMX1_CLK_MASK);
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setbits32(&immap->im_cpmux.cmx_fcr, CMX1_CLK_ROUTE);
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iounmap(bcsr);
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iounmap(immap);
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}
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static void init_fcc2_ioports(void)
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{
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cpm2_map_t* immap = ioremap(CPM_MAP_ADDR, sizeof(cpm2_map_t));
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u32 *bcsr = ioremap(BCSR_ADDR+12, sizeof(u32));
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struct io_port *io;
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u32 tempval;
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immap = cpm2_immr;
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io = &immap->im_ioport;
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/* Enable the PHY */
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clrbits32(bcsr, BCSR3_FETHIEN2);
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setbits32(bcsr, BCSR3_FETH2_RST);
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/* FCC2 are port B/C. */
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/* Configure port A and C pins for FCC2 Ethernet. */
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tempval = in_be32(&io->iop_pdirb);
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tempval &= ~PB2_DIRB0;
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tempval |= PB2_DIRB1;
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out_be32(&io->iop_pdirb, tempval);
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tempval = in_be32(&io->iop_psorb);
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tempval &= ~PB2_PSORB0;
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tempval |= PB2_PSORB1;
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out_be32(&io->iop_psorb, tempval);
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setbits32(&io->iop_pparb,PB2_DIRB0 | PB2_DIRB1);
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tempval = PC_F2RXCLK|PC_F2TXCLK;
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/* Alter clocks */
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clrbits32(&io->iop_psorc,tempval);
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clrbits32(&io->iop_pdirc,tempval);
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setbits32(&io->iop_pparc,tempval);
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clrbits32(&immap->im_cpmux.cmx_fcr, CMX2_CLK_MASK);
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setbits32(&immap->im_cpmux.cmx_fcr, CMX2_CLK_ROUTE);
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iounmap(bcsr);
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iounmap(immap);
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}
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static void __init mpc8272ads_fixup_enet_pdata(struct platform_device *pdev,
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int idx)
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{
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bd_t* bi = (void*)__res;
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int fs_no = fsid_fcc1+pdev->id-1;
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mpc82xx_fcc1_pdata.dpram_offset = mpc82xx_fcc2_pdata.dpram_offset = (u32)cpm2_immr->im_dprambase;
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mpc82xx_fcc1_pdata.fcc_regs_c = mpc82xx_fcc2_pdata.fcc_regs_c = (u32)cpm2_immr->im_fcc_c;
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switch(fs_no) {
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case fsid_fcc1:
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memcpy(&mpc82xx_fcc1_pdata.macaddr,bi->bi_enetaddr,6);
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pdev->dev.platform_data = &mpc82xx_fcc1_pdata;
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break;
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case fsid_fcc2:
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memcpy(&mpc82xx_fcc2_pdata.macaddr,bi->bi_enetaddr,6);
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mpc82xx_fcc2_pdata.macaddr[5] ^= 1;
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pdev->dev.platform_data = &mpc82xx_fcc2_pdata;
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break;
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}
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}
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static void mpc8272ads_fixup_uart_pdata(struct platform_device *pdev,
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int idx)
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{
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bd_t *bd = (bd_t *) __res;
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struct fs_uart_platform_info *pinfo;
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int num = ARRAY_SIZE(mpc8272_uart_pdata);
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int id = fs_uart_id_scc2fsid(idx);
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/* no need to alter anything if console */
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if ((id <= num) && (!pdev->dev.platform_data)) {
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pinfo = &mpc8272_uart_pdata[id];
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pinfo->uart_clk = bd->bi_intfreq;
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pdev->dev.platform_data = pinfo;
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}
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}
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static void init_scc1_uart_ioports(void)
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{
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cpm2_map_t* immap = ioremap(CPM_MAP_ADDR, sizeof(cpm2_map_t));
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/* SCC1 is only on port D */
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setbits32(&immap->im_ioport.iop_ppard,0x00000003);
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clrbits32(&immap->im_ioport.iop_psord,0x00000001);
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setbits32(&immap->im_ioport.iop_psord,0x00000002);
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clrbits32(&immap->im_ioport.iop_pdird,0x00000001);
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setbits32(&immap->im_ioport.iop_pdird,0x00000002);
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/* Wire BRG1 to SCC1 */
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clrbits32(&immap->im_cpmux.cmx_scr,0x00ffffff);
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iounmap(immap);
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}
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static void init_scc4_uart_ioports(void)
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{
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cpm2_map_t* immap = ioremap(CPM_MAP_ADDR, sizeof(cpm2_map_t));
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setbits32(&immap->im_ioport.iop_ppard,0x00000600);
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clrbits32(&immap->im_ioport.iop_psord,0x00000600);
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clrbits32(&immap->im_ioport.iop_pdird,0x00000200);
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setbits32(&immap->im_ioport.iop_pdird,0x00000400);
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/* Wire BRG4 to SCC4 */
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clrbits32(&immap->im_cpmux.cmx_scr,0x000000ff);
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setbits32(&immap->im_cpmux.cmx_scr,0x0000001b);
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iounmap(immap);
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}
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static int mpc8272ads_platform_notify(struct device *dev)
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{
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static const struct platform_notify_dev_map dev_map[] = {
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{
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.bus_id = "fsl-cpm-fcc",
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.rtn = mpc8272ads_fixup_enet_pdata,
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},
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{
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.bus_id = "fsl-cpm-scc:uart",
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.rtn = mpc8272ads_fixup_uart_pdata,
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},
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{
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.bus_id = NULL
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}
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};
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platform_notify_map(dev_map,dev);
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return 0;
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}
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int __init mpc8272ads_init(void)
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{
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printk(KERN_NOTICE "mpc8272ads: Init\n");
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platform_notify = mpc8272ads_platform_notify;
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ppc_sys_device_initfunc();
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ppc_sys_device_disable_all();
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ppc_sys_device_enable(MPC82xx_CPM_FCC1);
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ppc_sys_device_enable(MPC82xx_CPM_FCC2);
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/* to be ready for console, let's attach pdata here */
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#ifdef CONFIG_SERIAL_CPM_SCC1
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ppc_sys_device_setfunc(MPC82xx_CPM_SCC1, PPC_SYS_FUNC_UART);
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ppc_sys_device_enable(MPC82xx_CPM_SCC1);
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#endif
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#ifdef CONFIG_SERIAL_CPM_SCC4
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ppc_sys_device_setfunc(MPC82xx_CPM_SCC4, PPC_SYS_FUNC_UART);
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ppc_sys_device_enable(MPC82xx_CPM_SCC4);
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#endif
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return 0;
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}
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/*
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To prevent confusion, console selection is gross:
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by 0 assumed SCC1 and by 1 assumed SCC4
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*/
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struct platform_device* early_uart_get_pdev(int index)
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{
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bd_t *bd = (bd_t *) __res;
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struct fs_uart_platform_info *pinfo;
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struct platform_device* pdev = NULL;
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if(index) { /*assume SCC4 here*/
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pdev = &ppc_sys_platform_devices[MPC82xx_CPM_SCC4];
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pinfo = &mpc8272_uart_pdata[fsid_scc4_uart];
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} else { /*over SCC1*/
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pdev = &ppc_sys_platform_devices[MPC82xx_CPM_SCC1];
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pinfo = &mpc8272_uart_pdata[fsid_scc1_uart];
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}
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pinfo->uart_clk = bd->bi_intfreq;
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pdev->dev.platform_data = pinfo;
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ppc_sys_fixup_mem_resource(pdev, CPM_MAP_ADDR);
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return NULL;
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}
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arch_initcall(mpc8272ads_init);
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