270 lines
6.7 KiB
C
270 lines
6.7 KiB
C
/*
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* Clock driver for Keystone 2 based devices
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*
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* Copyright (C) 2013 Texas Instruments.
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* Murali Karicheri <m-karicheri2@ti.com>
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* Santosh Shilimkar <santosh.shilimkar@ti.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*/
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#include <linux/clk.h>
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#include <linux/clk-provider.h>
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#include <linux/err.h>
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#include <linux/io.h>
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#include <linux/slab.h>
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#include <linux/of_address.h>
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#include <linux/of.h>
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#include <linux/module.h>
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/* PSC register offsets */
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#define PTCMD 0x120
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#define PTSTAT 0x128
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#define PDSTAT 0x200
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#define PDCTL 0x300
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#define MDSTAT 0x800
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#define MDCTL 0xa00
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/* PSC module states */
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#define PSC_STATE_SWRSTDISABLE 0
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#define PSC_STATE_SYNCRST 1
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#define PSC_STATE_DISABLE 2
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#define PSC_STATE_ENABLE 3
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#define MDSTAT_STATE_MASK 0x3f
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#define MDSTAT_MCKOUT BIT(12)
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#define PDSTAT_STATE_MASK 0x1f
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#define MDCTL_FORCE BIT(31)
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#define MDCTL_LRESET BIT(8)
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#define PDCTL_NEXT BIT(0)
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/* Maximum timeout to bail out state transition for module */
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#define STATE_TRANS_MAX_COUNT 0xffff
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static void __iomem *domain_transition_base;
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/**
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* struct clk_psc_data - PSC data
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* @control_base: Base address for a PSC control
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* @domain_base: Base address for a PSC domain
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* @domain_id: PSC domain id number
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*/
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struct clk_psc_data {
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void __iomem *control_base;
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void __iomem *domain_base;
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u32 domain_id;
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};
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/**
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* struct clk_psc - PSC clock structure
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* @hw: clk_hw for the psc
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* @psc_data: PSC driver specific data
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* @lock: Spinlock used by the driver
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*/
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struct clk_psc {
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struct clk_hw hw;
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struct clk_psc_data *psc_data;
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spinlock_t *lock;
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};
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static DEFINE_SPINLOCK(psc_lock);
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#define to_clk_psc(_hw) container_of(_hw, struct clk_psc, hw)
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static void psc_config(void __iomem *control_base, void __iomem *domain_base,
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u32 next_state, u32 domain_id)
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{
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u32 ptcmd, pdstat, pdctl, mdstat, mdctl, ptstat;
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u32 count = STATE_TRANS_MAX_COUNT;
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mdctl = readl(control_base + MDCTL);
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mdctl &= ~MDSTAT_STATE_MASK;
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mdctl |= next_state;
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/* For disable, we always put the module in local reset */
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if (next_state == PSC_STATE_DISABLE)
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mdctl &= ~MDCTL_LRESET;
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writel(mdctl, control_base + MDCTL);
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pdstat = readl(domain_base + PDSTAT);
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if (!(pdstat & PDSTAT_STATE_MASK)) {
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pdctl = readl(domain_base + PDCTL);
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pdctl |= PDCTL_NEXT;
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writel(pdctl, domain_base + PDCTL);
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}
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ptcmd = 1 << domain_id;
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writel(ptcmd, domain_transition_base + PTCMD);
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do {
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ptstat = readl(domain_transition_base + PTSTAT);
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} while (((ptstat >> domain_id) & 1) && count--);
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count = STATE_TRANS_MAX_COUNT;
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do {
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mdstat = readl(control_base + MDSTAT);
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} while (!((mdstat & MDSTAT_STATE_MASK) == next_state) && count--);
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}
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static int keystone_clk_is_enabled(struct clk_hw *hw)
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{
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struct clk_psc *psc = to_clk_psc(hw);
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struct clk_psc_data *data = psc->psc_data;
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u32 mdstat = readl(data->control_base + MDSTAT);
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return (mdstat & MDSTAT_MCKOUT) ? 1 : 0;
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}
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static int keystone_clk_enable(struct clk_hw *hw)
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{
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struct clk_psc *psc = to_clk_psc(hw);
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struct clk_psc_data *data = psc->psc_data;
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unsigned long flags = 0;
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if (psc->lock)
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spin_lock_irqsave(psc->lock, flags);
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psc_config(data->control_base, data->domain_base,
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PSC_STATE_ENABLE, data->domain_id);
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if (psc->lock)
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spin_unlock_irqrestore(psc->lock, flags);
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return 0;
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}
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static void keystone_clk_disable(struct clk_hw *hw)
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{
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struct clk_psc *psc = to_clk_psc(hw);
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struct clk_psc_data *data = psc->psc_data;
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unsigned long flags = 0;
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if (psc->lock)
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spin_lock_irqsave(psc->lock, flags);
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psc_config(data->control_base, data->domain_base,
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PSC_STATE_DISABLE, data->domain_id);
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if (psc->lock)
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spin_unlock_irqrestore(psc->lock, flags);
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}
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static const struct clk_ops clk_psc_ops = {
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.enable = keystone_clk_enable,
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.disable = keystone_clk_disable,
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.is_enabled = keystone_clk_is_enabled,
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};
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/**
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* clk_register_psc - register psc clock
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* @dev: device that is registering this clock
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* @name: name of this clock
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* @parent_name: name of clock's parent
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* @psc_data: platform data to configure this clock
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* @lock: spinlock used by this clock
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*/
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static struct clk *clk_register_psc(struct device *dev,
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const char *name,
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const char *parent_name,
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struct clk_psc_data *psc_data,
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spinlock_t *lock)
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{
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struct clk_init_data init;
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struct clk_psc *psc;
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struct clk *clk;
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psc = kzalloc(sizeof(*psc), GFP_KERNEL);
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if (!psc)
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return ERR_PTR(-ENOMEM);
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init.name = name;
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init.ops = &clk_psc_ops;
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init.flags = 0;
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init.parent_names = (parent_name ? &parent_name : NULL);
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init.num_parents = (parent_name ? 1 : 0);
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psc->psc_data = psc_data;
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psc->lock = lock;
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psc->hw.init = &init;
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clk = clk_register(NULL, &psc->hw);
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if (IS_ERR(clk))
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kfree(psc);
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return clk;
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}
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/**
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* of_psc_clk_init - initialize psc clock through DT
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* @node: device tree node for this clock
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* @lock: spinlock used by this clock
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*/
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static void __init of_psc_clk_init(struct device_node *node, spinlock_t *lock)
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{
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const char *clk_name = node->name;
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const char *parent_name;
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struct clk_psc_data *data;
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struct clk *clk;
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int i;
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data = kzalloc(sizeof(*data), GFP_KERNEL);
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if (!data) {
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pr_err("%s: Out of memory\n", __func__);
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return;
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}
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i = of_property_match_string(node, "reg-names", "control");
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data->control_base = of_iomap(node, i);
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if (!data->control_base) {
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pr_err("%s: control ioremap failed\n", __func__);
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goto out;
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}
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i = of_property_match_string(node, "reg-names", "domain");
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data->domain_base = of_iomap(node, i);
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if (!data->domain_base) {
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pr_err("%s: domain ioremap failed\n", __func__);
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goto unmap_ctrl;
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}
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of_property_read_u32(node, "domain-id", &data->domain_id);
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/* Domain transition registers at fixed address space of domain_id 0 */
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if (!domain_transition_base && !data->domain_id)
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domain_transition_base = data->domain_base;
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of_property_read_string(node, "clock-output-names", &clk_name);
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parent_name = of_clk_get_parent_name(node, 0);
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if (!parent_name) {
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pr_err("%s: Parent clock not found\n", __func__);
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goto unmap_domain;
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}
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clk = clk_register_psc(NULL, clk_name, parent_name, data, lock);
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if (!IS_ERR(clk)) {
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of_clk_add_provider(node, of_clk_src_simple_get, clk);
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return;
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}
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pr_err("%s: error registering clk %s\n", __func__, node->name);
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unmap_domain:
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iounmap(data->domain_base);
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unmap_ctrl:
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iounmap(data->control_base);
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out:
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kfree(data);
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return;
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}
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/**
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* of_keystone_psc_clk_init - initialize psc clock through DT
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* @node: device tree node for this clock
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*/
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static void __init of_keystone_psc_clk_init(struct device_node *node)
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{
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of_psc_clk_init(node, &psc_lock);
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}
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CLK_OF_DECLARE(keystone_gate_clk, "ti,keystone,psc-clock",
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of_keystone_psc_clk_init);
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