908 lines
21 KiB
C
908 lines
21 KiB
C
/*
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* arch/arm/mach-mv78xx0/common.c
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*
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* Core functions for Marvell MV78xx0 SoCs
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*
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* This file is licensed under the terms of the GNU General Public
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* License version 2. This program is licensed "as is" without any
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* warranty of any kind, whether express or implied.
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*/
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#include <linux/kernel.h>
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#include <linux/init.h>
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#include <linux/platform_device.h>
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#include <linux/serial_8250.h>
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#include <linux/mbus.h>
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#include <linux/mv643xx_eth.h>
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#include <linux/mv643xx_i2c.h>
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#include <linux/ata_platform.h>
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#include <linux/ethtool.h>
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#include <asm/mach/map.h>
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#include <asm/mach/time.h>
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#include <mach/mv78xx0.h>
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#include <mach/bridge-regs.h>
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#include <plat/cache-feroceon-l2.h>
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#include <plat/ehci-orion.h>
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#include <plat/orion_nand.h>
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#include <plat/time.h>
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#include "common.h"
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/*****************************************************************************
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* Common bits
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****************************************************************************/
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int mv78xx0_core_index(void)
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{
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u32 extra;
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/*
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* Read Extra Features register.
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*/
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__asm__("mrc p15, 1, %0, c15, c1, 0" : "=r" (extra));
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return !!(extra & 0x00004000);
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}
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static int get_hclk(void)
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{
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int hclk;
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/*
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* HCLK tick rate is configured by DEV_D[7:5] pins.
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*/
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switch ((readl(SAMPLE_AT_RESET_LOW) >> 5) & 7) {
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case 0:
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hclk = 166666667;
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break;
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case 1:
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hclk = 200000000;
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break;
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case 2:
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hclk = 266666667;
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break;
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case 3:
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hclk = 333333333;
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break;
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case 4:
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hclk = 400000000;
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break;
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default:
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panic("unknown HCLK PLL setting: %.8x\n",
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readl(SAMPLE_AT_RESET_LOW));
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}
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return hclk;
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}
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static void get_pclk_l2clk(int hclk, int core_index, int *pclk, int *l2clk)
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{
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u32 cfg;
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/*
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* Core #0 PCLK/L2CLK is configured by bits [13:8], core #1
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* PCLK/L2CLK by bits [19:14].
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*/
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if (core_index == 0) {
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cfg = (readl(SAMPLE_AT_RESET_LOW) >> 8) & 0x3f;
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} else {
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cfg = (readl(SAMPLE_AT_RESET_LOW) >> 14) & 0x3f;
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}
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/*
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* Bits [11:8] ([17:14] for core #1) configure the PCLK:HCLK
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* ratio (1, 1.5, 2, 2.5, 3, 3.5, 4, 4.5, 5, 5.5, 6).
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*/
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*pclk = ((u64)hclk * (2 + (cfg & 0xf))) >> 1;
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/*
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* Bits [13:12] ([19:18] for core #1) configure the PCLK:L2CLK
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* ratio (1, 2, 3).
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*/
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*l2clk = *pclk / (((cfg >> 4) & 3) + 1);
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}
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static int get_tclk(void)
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{
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int tclk;
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/*
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* TCLK tick rate is configured by DEV_A[2:0] strap pins.
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*/
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switch ((readl(SAMPLE_AT_RESET_HIGH) >> 6) & 7) {
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case 1:
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tclk = 166666667;
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break;
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case 3:
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tclk = 200000000;
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break;
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default:
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panic("unknown TCLK PLL setting: %.8x\n",
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readl(SAMPLE_AT_RESET_HIGH));
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}
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return tclk;
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}
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/*****************************************************************************
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* I/O Address Mapping
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****************************************************************************/
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static struct map_desc mv78xx0_io_desc[] __initdata = {
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{
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.virtual = MV78XX0_CORE_REGS_VIRT_BASE,
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.pfn = 0,
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.length = MV78XX0_CORE_REGS_SIZE,
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.type = MT_DEVICE,
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}, {
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.virtual = MV78XX0_PCIE_IO_VIRT_BASE(0),
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.pfn = __phys_to_pfn(MV78XX0_PCIE_IO_PHYS_BASE(0)),
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.length = MV78XX0_PCIE_IO_SIZE * 8,
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.type = MT_DEVICE,
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}, {
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.virtual = MV78XX0_REGS_VIRT_BASE,
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.pfn = __phys_to_pfn(MV78XX0_REGS_PHYS_BASE),
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.length = MV78XX0_REGS_SIZE,
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.type = MT_DEVICE,
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},
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};
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void __init mv78xx0_map_io(void)
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{
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unsigned long phys;
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/*
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* Map the right set of per-core registers depending on
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* which core we are running on.
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*/
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if (mv78xx0_core_index() == 0) {
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phys = MV78XX0_CORE0_REGS_PHYS_BASE;
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} else {
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phys = MV78XX0_CORE1_REGS_PHYS_BASE;
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}
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mv78xx0_io_desc[0].pfn = __phys_to_pfn(phys);
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iotable_init(mv78xx0_io_desc, ARRAY_SIZE(mv78xx0_io_desc));
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}
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/*****************************************************************************
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* EHCI
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****************************************************************************/
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static struct orion_ehci_data mv78xx0_ehci_data = {
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.dram = &mv78xx0_mbus_dram_info,
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.phy_version = EHCI_PHY_NA,
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};
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static u64 ehci_dmamask = DMA_BIT_MASK(32);
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/*****************************************************************************
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* EHCI0
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****************************************************************************/
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static struct resource mv78xx0_ehci0_resources[] = {
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{
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.start = USB0_PHYS_BASE,
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.end = USB0_PHYS_BASE + SZ_4K - 1,
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.flags = IORESOURCE_MEM,
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}, {
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.start = IRQ_MV78XX0_USB_0,
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.end = IRQ_MV78XX0_USB_0,
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.flags = IORESOURCE_IRQ,
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},
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};
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static struct platform_device mv78xx0_ehci0 = {
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.name = "orion-ehci",
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.id = 0,
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.dev = {
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.dma_mask = &ehci_dmamask,
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.coherent_dma_mask = DMA_BIT_MASK(32),
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.platform_data = &mv78xx0_ehci_data,
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},
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.resource = mv78xx0_ehci0_resources,
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.num_resources = ARRAY_SIZE(mv78xx0_ehci0_resources),
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};
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void __init mv78xx0_ehci0_init(void)
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{
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platform_device_register(&mv78xx0_ehci0);
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}
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/*****************************************************************************
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* EHCI1
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****************************************************************************/
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static struct resource mv78xx0_ehci1_resources[] = {
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{
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.start = USB1_PHYS_BASE,
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.end = USB1_PHYS_BASE + SZ_4K - 1,
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.flags = IORESOURCE_MEM,
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}, {
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.start = IRQ_MV78XX0_USB_1,
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.end = IRQ_MV78XX0_USB_1,
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.flags = IORESOURCE_IRQ,
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},
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};
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static struct platform_device mv78xx0_ehci1 = {
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.name = "orion-ehci",
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.id = 1,
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.dev = {
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.dma_mask = &ehci_dmamask,
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.coherent_dma_mask = DMA_BIT_MASK(32),
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.platform_data = &mv78xx0_ehci_data,
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},
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.resource = mv78xx0_ehci1_resources,
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.num_resources = ARRAY_SIZE(mv78xx0_ehci1_resources),
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};
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void __init mv78xx0_ehci1_init(void)
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{
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platform_device_register(&mv78xx0_ehci1);
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}
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/*****************************************************************************
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* EHCI2
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****************************************************************************/
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static struct resource mv78xx0_ehci2_resources[] = {
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{
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.start = USB2_PHYS_BASE,
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.end = USB2_PHYS_BASE + SZ_4K - 1,
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.flags = IORESOURCE_MEM,
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}, {
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.start = IRQ_MV78XX0_USB_2,
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.end = IRQ_MV78XX0_USB_2,
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.flags = IORESOURCE_IRQ,
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},
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};
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static struct platform_device mv78xx0_ehci2 = {
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.name = "orion-ehci",
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.id = 2,
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.dev = {
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.dma_mask = &ehci_dmamask,
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.coherent_dma_mask = DMA_BIT_MASK(32),
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.platform_data = &mv78xx0_ehci_data,
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},
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.resource = mv78xx0_ehci2_resources,
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.num_resources = ARRAY_SIZE(mv78xx0_ehci2_resources),
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};
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void __init mv78xx0_ehci2_init(void)
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{
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platform_device_register(&mv78xx0_ehci2);
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}
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/*****************************************************************************
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* GE00
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****************************************************************************/
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struct mv643xx_eth_shared_platform_data mv78xx0_ge00_shared_data = {
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.t_clk = 0,
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.dram = &mv78xx0_mbus_dram_info,
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};
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static struct resource mv78xx0_ge00_shared_resources[] = {
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{
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.name = "ge00 base",
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.start = GE00_PHYS_BASE + 0x2000,
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.end = GE00_PHYS_BASE + SZ_16K - 1,
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.flags = IORESOURCE_MEM,
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}, {
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.name = "ge err irq",
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.start = IRQ_MV78XX0_GE_ERR,
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.end = IRQ_MV78XX0_GE_ERR,
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.flags = IORESOURCE_IRQ,
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},
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};
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static struct platform_device mv78xx0_ge00_shared = {
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.name = MV643XX_ETH_SHARED_NAME,
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.id = 0,
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.dev = {
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.platform_data = &mv78xx0_ge00_shared_data,
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},
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.num_resources = ARRAY_SIZE(mv78xx0_ge00_shared_resources),
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.resource = mv78xx0_ge00_shared_resources,
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};
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static struct resource mv78xx0_ge00_resources[] = {
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{
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.name = "ge00 irq",
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.start = IRQ_MV78XX0_GE00_SUM,
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.end = IRQ_MV78XX0_GE00_SUM,
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.flags = IORESOURCE_IRQ,
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},
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};
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static struct platform_device mv78xx0_ge00 = {
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.name = MV643XX_ETH_NAME,
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.id = 0,
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.num_resources = 1,
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.resource = mv78xx0_ge00_resources,
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.dev = {
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.coherent_dma_mask = DMA_BIT_MASK(32),
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},
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};
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void __init mv78xx0_ge00_init(struct mv643xx_eth_platform_data *eth_data)
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{
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eth_data->shared = &mv78xx0_ge00_shared;
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mv78xx0_ge00.dev.platform_data = eth_data;
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platform_device_register(&mv78xx0_ge00_shared);
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platform_device_register(&mv78xx0_ge00);
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}
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/*****************************************************************************
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* GE01
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****************************************************************************/
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struct mv643xx_eth_shared_platform_data mv78xx0_ge01_shared_data = {
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.t_clk = 0,
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.dram = &mv78xx0_mbus_dram_info,
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.shared_smi = &mv78xx0_ge00_shared,
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};
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static struct resource mv78xx0_ge01_shared_resources[] = {
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{
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.name = "ge01 base",
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.start = GE01_PHYS_BASE + 0x2000,
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.end = GE01_PHYS_BASE + SZ_16K - 1,
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.flags = IORESOURCE_MEM,
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},
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};
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static struct platform_device mv78xx0_ge01_shared = {
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.name = MV643XX_ETH_SHARED_NAME,
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.id = 1,
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.dev = {
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.platform_data = &mv78xx0_ge01_shared_data,
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},
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.num_resources = 1,
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.resource = mv78xx0_ge01_shared_resources,
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};
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static struct resource mv78xx0_ge01_resources[] = {
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{
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.name = "ge01 irq",
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.start = IRQ_MV78XX0_GE01_SUM,
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.end = IRQ_MV78XX0_GE01_SUM,
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.flags = IORESOURCE_IRQ,
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},
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};
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static struct platform_device mv78xx0_ge01 = {
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.name = MV643XX_ETH_NAME,
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.id = 1,
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.num_resources = 1,
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.resource = mv78xx0_ge01_resources,
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.dev = {
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.coherent_dma_mask = DMA_BIT_MASK(32),
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},
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};
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void __init mv78xx0_ge01_init(struct mv643xx_eth_platform_data *eth_data)
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{
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eth_data->shared = &mv78xx0_ge01_shared;
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mv78xx0_ge01.dev.platform_data = eth_data;
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platform_device_register(&mv78xx0_ge01_shared);
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platform_device_register(&mv78xx0_ge01);
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}
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/*****************************************************************************
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* GE10
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****************************************************************************/
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struct mv643xx_eth_shared_platform_data mv78xx0_ge10_shared_data = {
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.t_clk = 0,
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.dram = &mv78xx0_mbus_dram_info,
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.shared_smi = &mv78xx0_ge00_shared,
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};
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static struct resource mv78xx0_ge10_shared_resources[] = {
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{
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.name = "ge10 base",
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.start = GE10_PHYS_BASE + 0x2000,
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.end = GE10_PHYS_BASE + SZ_16K - 1,
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.flags = IORESOURCE_MEM,
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},
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};
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static struct platform_device mv78xx0_ge10_shared = {
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.name = MV643XX_ETH_SHARED_NAME,
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.id = 2,
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.dev = {
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.platform_data = &mv78xx0_ge10_shared_data,
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},
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.num_resources = 1,
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.resource = mv78xx0_ge10_shared_resources,
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};
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static struct resource mv78xx0_ge10_resources[] = {
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{
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.name = "ge10 irq",
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.start = IRQ_MV78XX0_GE10_SUM,
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.end = IRQ_MV78XX0_GE10_SUM,
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.flags = IORESOURCE_IRQ,
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},
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};
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static struct platform_device mv78xx0_ge10 = {
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.name = MV643XX_ETH_NAME,
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.id = 2,
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.num_resources = 1,
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.resource = mv78xx0_ge10_resources,
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.dev = {
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.coherent_dma_mask = DMA_BIT_MASK(32),
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},
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};
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void __init mv78xx0_ge10_init(struct mv643xx_eth_platform_data *eth_data)
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{
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u32 dev, rev;
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eth_data->shared = &mv78xx0_ge10_shared;
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mv78xx0_ge10.dev.platform_data = eth_data;
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/*
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* On the Z0, ge10 and ge11 are internally connected back
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* to back, and not brought out.
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*/
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mv78xx0_pcie_id(&dev, &rev);
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if (dev == MV78X00_Z0_DEV_ID) {
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eth_data->phy_addr = MV643XX_ETH_PHY_NONE;
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eth_data->speed = SPEED_1000;
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eth_data->duplex = DUPLEX_FULL;
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}
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platform_device_register(&mv78xx0_ge10_shared);
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platform_device_register(&mv78xx0_ge10);
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}
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/*****************************************************************************
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* GE11
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****************************************************************************/
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struct mv643xx_eth_shared_platform_data mv78xx0_ge11_shared_data = {
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.t_clk = 0,
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.dram = &mv78xx0_mbus_dram_info,
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.shared_smi = &mv78xx0_ge00_shared,
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};
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static struct resource mv78xx0_ge11_shared_resources[] = {
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{
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.name = "ge11 base",
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.start = GE11_PHYS_BASE + 0x2000,
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.end = GE11_PHYS_BASE + SZ_16K - 1,
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.flags = IORESOURCE_MEM,
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},
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};
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static struct platform_device mv78xx0_ge11_shared = {
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.name = MV643XX_ETH_SHARED_NAME,
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.id = 3,
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.dev = {
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.platform_data = &mv78xx0_ge11_shared_data,
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},
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.num_resources = 1,
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.resource = mv78xx0_ge11_shared_resources,
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};
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static struct resource mv78xx0_ge11_resources[] = {
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{
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.name = "ge11 irq",
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.start = IRQ_MV78XX0_GE11_SUM,
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.end = IRQ_MV78XX0_GE11_SUM,
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.flags = IORESOURCE_IRQ,
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},
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};
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static struct platform_device mv78xx0_ge11 = {
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.name = MV643XX_ETH_NAME,
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.id = 3,
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.num_resources = 1,
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.resource = mv78xx0_ge11_resources,
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.dev = {
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.coherent_dma_mask = DMA_BIT_MASK(32),
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},
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};
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void __init mv78xx0_ge11_init(struct mv643xx_eth_platform_data *eth_data)
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{
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u32 dev, rev;
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eth_data->shared = &mv78xx0_ge11_shared;
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|
mv78xx0_ge11.dev.platform_data = eth_data;
|
|
|
|
/*
|
|
* On the Z0, ge10 and ge11 are internally connected back
|
|
* to back, and not brought out.
|
|
*/
|
|
mv78xx0_pcie_id(&dev, &rev);
|
|
if (dev == MV78X00_Z0_DEV_ID) {
|
|
eth_data->phy_addr = MV643XX_ETH_PHY_NONE;
|
|
eth_data->speed = SPEED_1000;
|
|
eth_data->duplex = DUPLEX_FULL;
|
|
}
|
|
|
|
platform_device_register(&mv78xx0_ge11_shared);
|
|
platform_device_register(&mv78xx0_ge11);
|
|
}
|
|
|
|
/*****************************************************************************
|
|
* I2C bus 0
|
|
****************************************************************************/
|
|
|
|
static struct mv64xxx_i2c_pdata mv78xx0_i2c_0_pdata = {
|
|
.freq_m = 8, /* assumes 166 MHz TCLK */
|
|
.freq_n = 3,
|
|
.timeout = 1000, /* Default timeout of 1 second */
|
|
};
|
|
|
|
static struct resource mv78xx0_i2c_0_resources[] = {
|
|
{
|
|
.start = I2C_0_PHYS_BASE,
|
|
.end = I2C_0_PHYS_BASE + 0x1f,
|
|
.flags = IORESOURCE_MEM,
|
|
}, {
|
|
.start = IRQ_MV78XX0_I2C_0,
|
|
.end = IRQ_MV78XX0_I2C_0,
|
|
.flags = IORESOURCE_IRQ,
|
|
},
|
|
};
|
|
|
|
|
|
static struct platform_device mv78xx0_i2c_0 = {
|
|
.name = MV64XXX_I2C_CTLR_NAME,
|
|
.id = 0,
|
|
.num_resources = ARRAY_SIZE(mv78xx0_i2c_0_resources),
|
|
.resource = mv78xx0_i2c_0_resources,
|
|
.dev = {
|
|
.platform_data = &mv78xx0_i2c_0_pdata,
|
|
},
|
|
};
|
|
|
|
/*****************************************************************************
|
|
* I2C bus 1
|
|
****************************************************************************/
|
|
|
|
static struct mv64xxx_i2c_pdata mv78xx0_i2c_1_pdata = {
|
|
.freq_m = 8, /* assumes 166 MHz TCLK */
|
|
.freq_n = 3,
|
|
.timeout = 1000, /* Default timeout of 1 second */
|
|
};
|
|
|
|
static struct resource mv78xx0_i2c_1_resources[] = {
|
|
{
|
|
.start = I2C_1_PHYS_BASE,
|
|
.end = I2C_1_PHYS_BASE + 0x1f,
|
|
.flags = IORESOURCE_MEM,
|
|
}, {
|
|
.start = IRQ_MV78XX0_I2C_1,
|
|
.end = IRQ_MV78XX0_I2C_1,
|
|
.flags = IORESOURCE_IRQ,
|
|
},
|
|
};
|
|
|
|
|
|
static struct platform_device mv78xx0_i2c_1 = {
|
|
.name = MV64XXX_I2C_CTLR_NAME,
|
|
.id = 1,
|
|
.num_resources = ARRAY_SIZE(mv78xx0_i2c_1_resources),
|
|
.resource = mv78xx0_i2c_1_resources,
|
|
.dev = {
|
|
.platform_data = &mv78xx0_i2c_1_pdata,
|
|
},
|
|
};
|
|
|
|
void __init mv78xx0_i2c_init(void)
|
|
{
|
|
platform_device_register(&mv78xx0_i2c_0);
|
|
platform_device_register(&mv78xx0_i2c_1);
|
|
}
|
|
|
|
/*****************************************************************************
|
|
* SATA
|
|
****************************************************************************/
|
|
static struct resource mv78xx0_sata_resources[] = {
|
|
{
|
|
.name = "sata base",
|
|
.start = SATA_PHYS_BASE,
|
|
.end = SATA_PHYS_BASE + 0x5000 - 1,
|
|
.flags = IORESOURCE_MEM,
|
|
}, {
|
|
.name = "sata irq",
|
|
.start = IRQ_MV78XX0_SATA,
|
|
.end = IRQ_MV78XX0_SATA,
|
|
.flags = IORESOURCE_IRQ,
|
|
},
|
|
};
|
|
|
|
static struct platform_device mv78xx0_sata = {
|
|
.name = "sata_mv",
|
|
.id = 0,
|
|
.dev = {
|
|
.coherent_dma_mask = DMA_BIT_MASK(32),
|
|
},
|
|
.num_resources = ARRAY_SIZE(mv78xx0_sata_resources),
|
|
.resource = mv78xx0_sata_resources,
|
|
};
|
|
|
|
void __init mv78xx0_sata_init(struct mv_sata_platform_data *sata_data)
|
|
{
|
|
sata_data->dram = &mv78xx0_mbus_dram_info;
|
|
mv78xx0_sata.dev.platform_data = sata_data;
|
|
platform_device_register(&mv78xx0_sata);
|
|
}
|
|
|
|
|
|
/*****************************************************************************
|
|
* UART0
|
|
****************************************************************************/
|
|
static struct plat_serial8250_port mv78xx0_uart0_data[] = {
|
|
{
|
|
.mapbase = UART0_PHYS_BASE,
|
|
.membase = (char *)UART0_VIRT_BASE,
|
|
.irq = IRQ_MV78XX0_UART_0,
|
|
.flags = UPF_SKIP_TEST | UPF_BOOT_AUTOCONF,
|
|
.iotype = UPIO_MEM,
|
|
.regshift = 2,
|
|
.uartclk = 0,
|
|
}, {
|
|
},
|
|
};
|
|
|
|
static struct resource mv78xx0_uart0_resources[] = {
|
|
{
|
|
.start = UART0_PHYS_BASE,
|
|
.end = UART0_PHYS_BASE + 0xff,
|
|
.flags = IORESOURCE_MEM,
|
|
}, {
|
|
.start = IRQ_MV78XX0_UART_0,
|
|
.end = IRQ_MV78XX0_UART_0,
|
|
.flags = IORESOURCE_IRQ,
|
|
},
|
|
};
|
|
|
|
static struct platform_device mv78xx0_uart0 = {
|
|
.name = "serial8250",
|
|
.id = PLAT8250_DEV_PLATFORM,
|
|
.dev = {
|
|
.platform_data = mv78xx0_uart0_data,
|
|
},
|
|
.resource = mv78xx0_uart0_resources,
|
|
.num_resources = ARRAY_SIZE(mv78xx0_uart0_resources),
|
|
};
|
|
|
|
void __init mv78xx0_uart0_init(void)
|
|
{
|
|
platform_device_register(&mv78xx0_uart0);
|
|
}
|
|
|
|
|
|
/*****************************************************************************
|
|
* UART1
|
|
****************************************************************************/
|
|
static struct plat_serial8250_port mv78xx0_uart1_data[] = {
|
|
{
|
|
.mapbase = UART1_PHYS_BASE,
|
|
.membase = (char *)UART1_VIRT_BASE,
|
|
.irq = IRQ_MV78XX0_UART_1,
|
|
.flags = UPF_SKIP_TEST | UPF_BOOT_AUTOCONF,
|
|
.iotype = UPIO_MEM,
|
|
.regshift = 2,
|
|
.uartclk = 0,
|
|
}, {
|
|
},
|
|
};
|
|
|
|
static struct resource mv78xx0_uart1_resources[] = {
|
|
{
|
|
.start = UART1_PHYS_BASE,
|
|
.end = UART1_PHYS_BASE + 0xff,
|
|
.flags = IORESOURCE_MEM,
|
|
}, {
|
|
.start = IRQ_MV78XX0_UART_1,
|
|
.end = IRQ_MV78XX0_UART_1,
|
|
.flags = IORESOURCE_IRQ,
|
|
},
|
|
};
|
|
|
|
static struct platform_device mv78xx0_uart1 = {
|
|
.name = "serial8250",
|
|
.id = PLAT8250_DEV_PLATFORM1,
|
|
.dev = {
|
|
.platform_data = mv78xx0_uart1_data,
|
|
},
|
|
.resource = mv78xx0_uart1_resources,
|
|
.num_resources = ARRAY_SIZE(mv78xx0_uart1_resources),
|
|
};
|
|
|
|
void __init mv78xx0_uart1_init(void)
|
|
{
|
|
platform_device_register(&mv78xx0_uart1);
|
|
}
|
|
|
|
|
|
/*****************************************************************************
|
|
* UART2
|
|
****************************************************************************/
|
|
static struct plat_serial8250_port mv78xx0_uart2_data[] = {
|
|
{
|
|
.mapbase = UART2_PHYS_BASE,
|
|
.membase = (char *)UART2_VIRT_BASE,
|
|
.irq = IRQ_MV78XX0_UART_2,
|
|
.flags = UPF_SKIP_TEST | UPF_BOOT_AUTOCONF,
|
|
.iotype = UPIO_MEM,
|
|
.regshift = 2,
|
|
.uartclk = 0,
|
|
}, {
|
|
},
|
|
};
|
|
|
|
static struct resource mv78xx0_uart2_resources[] = {
|
|
{
|
|
.start = UART2_PHYS_BASE,
|
|
.end = UART2_PHYS_BASE + 0xff,
|
|
.flags = IORESOURCE_MEM,
|
|
}, {
|
|
.start = IRQ_MV78XX0_UART_2,
|
|
.end = IRQ_MV78XX0_UART_2,
|
|
.flags = IORESOURCE_IRQ,
|
|
},
|
|
};
|
|
|
|
static struct platform_device mv78xx0_uart2 = {
|
|
.name = "serial8250",
|
|
.id = PLAT8250_DEV_PLATFORM2,
|
|
.dev = {
|
|
.platform_data = mv78xx0_uart2_data,
|
|
},
|
|
.resource = mv78xx0_uart2_resources,
|
|
.num_resources = ARRAY_SIZE(mv78xx0_uart2_resources),
|
|
};
|
|
|
|
void __init mv78xx0_uart2_init(void)
|
|
{
|
|
platform_device_register(&mv78xx0_uart2);
|
|
}
|
|
|
|
|
|
/*****************************************************************************
|
|
* UART3
|
|
****************************************************************************/
|
|
static struct plat_serial8250_port mv78xx0_uart3_data[] = {
|
|
{
|
|
.mapbase = UART3_PHYS_BASE,
|
|
.membase = (char *)UART3_VIRT_BASE,
|
|
.irq = IRQ_MV78XX0_UART_3,
|
|
.flags = UPF_SKIP_TEST | UPF_BOOT_AUTOCONF,
|
|
.iotype = UPIO_MEM,
|
|
.regshift = 2,
|
|
.uartclk = 0,
|
|
}, {
|
|
},
|
|
};
|
|
|
|
static struct resource mv78xx0_uart3_resources[] = {
|
|
{
|
|
.start = UART3_PHYS_BASE,
|
|
.end = UART3_PHYS_BASE + 0xff,
|
|
.flags = IORESOURCE_MEM,
|
|
}, {
|
|
.start = IRQ_MV78XX0_UART_3,
|
|
.end = IRQ_MV78XX0_UART_3,
|
|
.flags = IORESOURCE_IRQ,
|
|
},
|
|
};
|
|
|
|
static struct platform_device mv78xx0_uart3 = {
|
|
.name = "serial8250",
|
|
.id = 3,
|
|
.dev = {
|
|
.platform_data = mv78xx0_uart3_data,
|
|
},
|
|
.resource = mv78xx0_uart3_resources,
|
|
.num_resources = ARRAY_SIZE(mv78xx0_uart3_resources),
|
|
};
|
|
|
|
void __init mv78xx0_uart3_init(void)
|
|
{
|
|
platform_device_register(&mv78xx0_uart3);
|
|
}
|
|
|
|
|
|
/*****************************************************************************
|
|
* Time handling
|
|
****************************************************************************/
|
|
void __init mv78xx0_init_early(void)
|
|
{
|
|
orion_time_set_base(TIMER_VIRT_BASE);
|
|
}
|
|
|
|
static void mv78xx0_timer_init(void)
|
|
{
|
|
orion_time_init(BRIDGE_VIRT_BASE, BRIDGE_INT_TIMER1_CLR,
|
|
IRQ_MV78XX0_TIMER_1, get_tclk());
|
|
}
|
|
|
|
struct sys_timer mv78xx0_timer = {
|
|
.init = mv78xx0_timer_init,
|
|
};
|
|
|
|
|
|
/*****************************************************************************
|
|
* General
|
|
****************************************************************************/
|
|
static char * __init mv78xx0_id(void)
|
|
{
|
|
u32 dev, rev;
|
|
|
|
mv78xx0_pcie_id(&dev, &rev);
|
|
|
|
if (dev == MV78X00_Z0_DEV_ID) {
|
|
if (rev == MV78X00_REV_Z0)
|
|
return "MV78X00-Z0";
|
|
else
|
|
return "MV78X00-Rev-Unsupported";
|
|
} else if (dev == MV78100_DEV_ID) {
|
|
if (rev == MV78100_REV_A0)
|
|
return "MV78100-A0";
|
|
else if (rev == MV78100_REV_A1)
|
|
return "MV78100-A1";
|
|
else
|
|
return "MV78100-Rev-Unsupported";
|
|
} else if (dev == MV78200_DEV_ID) {
|
|
if (rev == MV78100_REV_A0)
|
|
return "MV78200-A0";
|
|
else
|
|
return "MV78200-Rev-Unsupported";
|
|
} else {
|
|
return "Device-Unknown";
|
|
}
|
|
}
|
|
|
|
static int __init is_l2_writethrough(void)
|
|
{
|
|
return !!(readl(CPU_CONTROL) & L2_WRITETHROUGH);
|
|
}
|
|
|
|
void __init mv78xx0_init(void)
|
|
{
|
|
int core_index;
|
|
int hclk;
|
|
int pclk;
|
|
int l2clk;
|
|
int tclk;
|
|
|
|
core_index = mv78xx0_core_index();
|
|
hclk = get_hclk();
|
|
get_pclk_l2clk(hclk, core_index, &pclk, &l2clk);
|
|
tclk = get_tclk();
|
|
|
|
printk(KERN_INFO "%s ", mv78xx0_id());
|
|
printk("core #%d, ", core_index);
|
|
printk("PCLK = %dMHz, ", (pclk + 499999) / 1000000);
|
|
printk("L2 = %dMHz, ", (l2clk + 499999) / 1000000);
|
|
printk("HCLK = %dMHz, ", (hclk + 499999) / 1000000);
|
|
printk("TCLK = %dMHz\n", (tclk + 499999) / 1000000);
|
|
|
|
mv78xx0_setup_cpu_mbus();
|
|
|
|
#ifdef CONFIG_CACHE_FEROCEON_L2
|
|
feroceon_l2_init(is_l2_writethrough());
|
|
#endif
|
|
|
|
mv78xx0_ge00_shared_data.t_clk = tclk;
|
|
mv78xx0_ge01_shared_data.t_clk = tclk;
|
|
mv78xx0_ge10_shared_data.t_clk = tclk;
|
|
mv78xx0_ge11_shared_data.t_clk = tclk;
|
|
mv78xx0_uart0_data[0].uartclk = tclk;
|
|
mv78xx0_uart1_data[0].uartclk = tclk;
|
|
mv78xx0_uart2_data[0].uartclk = tclk;
|
|
mv78xx0_uart3_data[0].uartclk = tclk;
|
|
}
|