721 lines
21 KiB
Plaintext
721 lines
21 KiB
Plaintext
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EDAC - Error Detection And Correction
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Written by Doug Thompson <dougthompson@xmission.com>
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7 Dec 2005
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17 Jul 2007 Updated
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EDAC is maintained and written by:
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Doug Thompson, Dave Jiang, Dave Peterson et al,
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original author: Thayne Harbaugh,
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Contact:
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website: bluesmoke.sourceforge.net
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mailing list: bluesmoke-devel@lists.sourceforge.net
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"bluesmoke" was the name for this device driver when it was "out-of-tree"
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and maintained at sourceforge.net. When it was pushed into 2.6.16 for the
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first time, it was renamed to 'EDAC'.
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The bluesmoke project at sourceforge.net is now utilized as a 'staging area'
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for EDAC development, before it is sent upstream to kernel.org
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At the bluesmoke/EDAC project site is a series of quilt patches against
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recent kernels, stored in a SVN repository. For easier downloading, there
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is also a tarball snapshot available.
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============================================================================
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EDAC PURPOSE
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The 'edac' kernel module goal is to detect and report errors that occur
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within the computer system running under linux.
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MEMORY
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In the initial release, memory Correctable Errors (CE) and Uncorrectable
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Errors (UE) are the primary errors being harvested. These types of errors
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are harvested by the 'edac_mc' class of device.
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Detecting CE events, then harvesting those events and reporting them,
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CAN be a predictor of future UE events. With CE events, the system can
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continue to operate, but with less safety. Preventive maintenance and
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proactive part replacement of memory DIMMs exhibiting CEs can reduce
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the likelihood of the dreaded UE events and system 'panics'.
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NON-MEMORY
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A new feature for EDAC, the edac_device class of device, was added in
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the 2.6.23 version of the kernel.
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This new device type allows for non-memory type of ECC hardware detectors
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to have their states harvested and presented to userspace via the sysfs
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interface.
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Some architectures have ECC detectors for L1, L2 and L3 caches, along with DMA
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engines, fabric switches, main data path switches, interconnections,
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and various other hardware data paths. If the hardware reports it, then
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a edac_device device probably can be constructed to harvest and present
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that to userspace.
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PCI BUS SCANNING
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In addition, PCI Bus Parity and SERR Errors are scanned for on PCI devices
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in order to determine if errors are occurring on data transfers.
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The presence of PCI Parity errors must be examined with a grain of salt.
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There are several add-in adapters that do NOT follow the PCI specification
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with regards to Parity generation and reporting. The specification says
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the vendor should tie the parity status bits to 0 if they do not intend
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to generate parity. Some vendors do not do this, and thus the parity bit
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can "float" giving false positives.
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In the kernel there is a PCI device attribute located in sysfs that is
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checked by the EDAC PCI scanning code. If that attribute is set,
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PCI parity/error scanning is skipped for that device. The attribute
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is:
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broken_parity_status
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as is located in /sys/devices/pci<XXX>/0000:XX:YY.Z directorys for
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PCI devices.
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FUTURE HARDWARE SCANNING
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EDAC will have future error detectors that will be integrated with
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EDAC or added to it, in the following list:
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MCE Machine Check Exception
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MCA Machine Check Architecture
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NMI NMI notification of ECC errors
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MSRs Machine Specific Register error cases
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and other mechanisms.
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These errors are usually bus errors, ECC errors, thermal throttling
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and the like.
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============================================================================
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EDAC VERSIONING
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EDAC is composed of a "core" module (edac_core.ko) and several Memory
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Controller (MC) driver modules. On a given system, the CORE
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is loaded and one MC driver will be loaded. Both the CORE and
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the MC driver (or edac_device driver) have individual versions that reflect
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current release level of their respective modules.
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Thus, to "report" on what version a system is running, one must report both
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the CORE's and the MC driver's versions.
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LOADING
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If 'edac' was statically linked with the kernel then no loading is
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necessary. If 'edac' was built as modules then simply modprobe the
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'edac' pieces that you need. You should be able to modprobe
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hardware-specific modules and have the dependencies load the necessary core
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modules.
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Example:
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$> modprobe amd76x_edac
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loads both the amd76x_edac.ko memory controller module and the edac_mc.ko
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core module.
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============================================================================
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EDAC sysfs INTERFACE
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EDAC presents a 'sysfs' interface for control, reporting and attribute
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reporting purposes.
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EDAC lives in the /sys/devices/system/edac directory.
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Within this directory there currently reside 2 'edac' components:
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mc memory controller(s) system
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pci PCI control and status system
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============================================================================
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Memory Controller (mc) Model
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First a background on the memory controller's model abstracted in EDAC.
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Each 'mc' device controls a set of DIMM memory modules. These modules are
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laid out in a Chip-Select Row (csrowX) and Channel table (chX). There can
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be multiple csrows and multiple channels.
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Memory controllers allow for several csrows, with 8 csrows being a typical value.
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Yet, the actual number of csrows depends on the electrical "loading"
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of a given motherboard, memory controller and DIMM characteristics.
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Dual channels allows for 128 bit data transfers to the CPU from memory.
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Some newer chipsets allow for more than 2 channels, like Fully Buffered DIMMs
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(FB-DIMMs). The following example will assume 2 channels:
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Channel 0 Channel 1
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===================================
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csrow0 | DIMM_A0 | DIMM_B0 |
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csrow1 | DIMM_A0 | DIMM_B0 |
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===================================
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===================================
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csrow2 | DIMM_A1 | DIMM_B1 |
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csrow3 | DIMM_A1 | DIMM_B1 |
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===================================
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In the above example table there are 4 physical slots on the motherboard
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for memory DIMMs:
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DIMM_A0
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DIMM_B0
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DIMM_A1
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DIMM_B1
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Labels for these slots are usually silk screened on the motherboard. Slots
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labeled 'A' are channel 0 in this example. Slots labeled 'B'
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are channel 1. Notice that there are two csrows possible on a
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physical DIMM. These csrows are allocated their csrow assignment
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based on the slot into which the memory DIMM is placed. Thus, when 1 DIMM
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is placed in each Channel, the csrows cross both DIMMs.
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Memory DIMMs come single or dual "ranked". A rank is a populated csrow.
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Thus, 2 single ranked DIMMs, placed in slots DIMM_A0 and DIMM_B0 above
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will have 1 csrow, csrow0. csrow1 will be empty. On the other hand,
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when 2 dual ranked DIMMs are similarly placed, then both csrow0 and
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csrow1 will be populated. The pattern repeats itself for csrow2 and
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csrow3.
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The representation of the above is reflected in the directory tree
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in EDAC's sysfs interface. Starting in directory
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/sys/devices/system/edac/mc each memory controller will be represented
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by its own 'mcX' directory, where 'X" is the index of the MC.
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..../edac/mc/
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|->mc0
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|->mc1
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|->mc2
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....
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Under each 'mcX' directory each 'csrowX' is again represented by a
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'csrowX', where 'X" is the csrow index:
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.../mc/mc0/
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|->csrow0
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|->csrow2
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|->csrow3
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....
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Notice that there is no csrow1, which indicates that csrow0 is
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composed of a single ranked DIMMs. This should also apply in both
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Channels, in order to have dual-channel mode be operational. Since
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both csrow2 and csrow3 are populated, this indicates a dual ranked
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set of DIMMs for channels 0 and 1.
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Within each of the 'mcX' and 'csrowX' directories are several
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EDAC control and attribute files.
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============================================================================
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'mcX' DIRECTORIES
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In 'mcX' directories are EDAC control and attribute files for
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this 'X" instance of the memory controllers:
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Counter reset control file:
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'reset_counters'
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This write-only control file will zero all the statistical counters
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for UE and CE errors. Zeroing the counters will also reset the timer
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indicating how long since the last counter zero. This is useful
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for computing errors/time. Since the counters are always reset at
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driver initialization time, no module/kernel parameter is available.
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RUN TIME: echo "anything" >/sys/devices/system/edac/mc/mc0/counter_reset
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This resets the counters on memory controller 0
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Seconds since last counter reset control file:
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'seconds_since_reset'
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This attribute file displays how many seconds have elapsed since the
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last counter reset. This can be used with the error counters to
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measure error rates.
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Memory Controller name attribute file:
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'mc_name'
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This attribute file displays the type of memory controller
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that is being utilized.
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Total memory managed by this memory controller attribute file:
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'size_mb'
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This attribute file displays, in count of megabytes, of memory
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that this instance of memory controller manages.
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Total Uncorrectable Errors count attribute file:
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'ue_count'
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This attribute file displays the total count of uncorrectable
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errors that have occurred on this memory controller. If panic_on_ue
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is set this counter will not have a chance to increment,
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since EDAC will panic the system.
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Total UE count that had no information attribute fileY:
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'ue_noinfo_count'
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This attribute file displays the number of UEs that
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have occurred have occurred with no informations as to which DIMM
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slot is having errors.
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Total Correctable Errors count attribute file:
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'ce_count'
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This attribute file displays the total count of correctable
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errors that have occurred on this memory controller. This
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count is very important to examine. CEs provide early
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indications that a DIMM is beginning to fail. This count
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field should be monitored for non-zero values and report
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such information to the system administrator.
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Total Correctable Errors count attribute file:
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'ce_noinfo_count'
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This attribute file displays the number of CEs that
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have occurred wherewith no informations as to which DIMM slot
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is having errors. Memory is handicapped, but operational,
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yet no information is available to indicate which slot
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the failing memory is in. This count field should be also
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be monitored for non-zero values.
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Device Symlink:
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'device'
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Symlink to the memory controller device.
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Sdram memory scrubbing rate:
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'sdram_scrub_rate'
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Read/Write attribute file that controls memory scrubbing. The scrubbing
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rate is set by writing a minimum bandwidth in bytes/sec to the attribute
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file. The rate will be translated to an internal value that gives at
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least the specified rate.
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Reading the file will return the actual scrubbing rate employed.
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If configuration fails or memory scrubbing is not implemented, the value
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of the attribute file will be -1.
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============================================================================
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'csrowX' DIRECTORIES
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In the 'csrowX' directories are EDAC control and attribute files for
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this 'X" instance of csrow:
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Total Uncorrectable Errors count attribute file:
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'ue_count'
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This attribute file displays the total count of uncorrectable
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errors that have occurred on this csrow. If panic_on_ue is set
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this counter will not have a chance to increment, since EDAC
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will panic the system.
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Total Correctable Errors count attribute file:
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'ce_count'
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This attribute file displays the total count of correctable
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errors that have occurred on this csrow. This
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count is very important to examine. CEs provide early
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indications that a DIMM is beginning to fail. This count
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field should be monitored for non-zero values and report
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such information to the system administrator.
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Total memory managed by this csrow attribute file:
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'size_mb'
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This attribute file displays, in count of megabytes, of memory
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that this csrow contains.
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Memory Type attribute file:
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'mem_type'
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This attribute file will display what type of memory is currently
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on this csrow. Normally, either buffered or unbuffered memory.
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Examples:
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Registered-DDR
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Unbuffered-DDR
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EDAC Mode of operation attribute file:
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'edac_mode'
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This attribute file will display what type of Error detection
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and correction is being utilized.
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Device type attribute file:
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'dev_type'
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This attribute file will display what type of DRAM device is
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being utilized on this DIMM.
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Examples:
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x1
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x2
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x4
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x8
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Channel 0 CE Count attribute file:
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'ch0_ce_count'
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This attribute file will display the count of CEs on this
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DIMM located in channel 0.
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Channel 0 UE Count attribute file:
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'ch0_ue_count'
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This attribute file will display the count of UEs on this
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DIMM located in channel 0.
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Channel 0 DIMM Label control file:
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'ch0_dimm_label'
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This control file allows this DIMM to have a label assigned
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to it. With this label in the module, when errors occur
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the output can provide the DIMM label in the system log.
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This becomes vital for panic events to isolate the
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cause of the UE event.
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DIMM Labels must be assigned after booting, with information
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that correctly identifies the physical slot with its
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silk screen label. This information is currently very
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motherboard specific and determination of this information
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must occur in userland at this time.
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Channel 1 CE Count attribute file:
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'ch1_ce_count'
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This attribute file will display the count of CEs on this
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DIMM located in channel 1.
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Channel 1 UE Count attribute file:
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'ch1_ue_count'
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This attribute file will display the count of UEs on this
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DIMM located in channel 0.
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Channel 1 DIMM Label control file:
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'ch1_dimm_label'
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This control file allows this DIMM to have a label assigned
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to it. With this label in the module, when errors occur
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the output can provide the DIMM label in the system log.
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This becomes vital for panic events to isolate the
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cause of the UE event.
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DIMM Labels must be assigned after booting, with information
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that correctly identifies the physical slot with its
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silk screen label. This information is currently very
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motherboard specific and determination of this information
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must occur in userland at this time.
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============================================================================
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SYSTEM LOGGING
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If logging for UEs and CEs are enabled then system logs will have
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error notices indicating errors that have been detected:
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EDAC MC0: CE page 0x283, offset 0xce0, grain 8, syndrome 0x6ec3, row 0,
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channel 1 "DIMM_B1": amd76x_edac
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EDAC MC0: CE page 0x1e5, offset 0xfb0, grain 8, syndrome 0xb741, row 0,
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channel 1 "DIMM_B1": amd76x_edac
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The structure of the message is:
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the memory controller (MC0)
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Error type (CE)
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memory page (0x283)
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offset in the page (0xce0)
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the byte granularity (grain 8)
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or resolution of the error
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the error syndrome (0xb741)
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memory row (row 0)
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memory channel (channel 1)
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DIMM label, if set prior (DIMM B1
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and then an optional, driver-specific message that may
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have additional information.
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Both UEs and CEs with no info will lack all but memory controller,
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error type, a notice of "no info" and then an optional,
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driver-specific error message.
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============================================================================
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PCI Bus Parity Detection
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On Header Type 00 devices the primary status is looked at
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for any parity error regardless of whether Parity is enabled on the
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device. (The spec indicates parity is generated in some cases).
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On Header Type 01 bridges, the secondary status register is also
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looked at to see if parity occurred on the bus on the other side of
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the bridge.
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SYSFS CONFIGURATION
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Under /sys/devices/system/edac/pci are control and attribute files as follows:
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Enable/Disable PCI Parity checking control file:
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'check_pci_parity'
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This control file enables or disables the PCI Bus Parity scanning
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operation. Writing a 1 to this file enables the scanning. Writing
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a 0 to this file disables the scanning.
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Enable:
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echo "1" >/sys/devices/system/edac/pci/check_pci_parity
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Disable:
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echo "0" >/sys/devices/system/edac/pci/check_pci_parity
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Parity Count:
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'pci_parity_count'
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This attribute file will display the number of parity errors that
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have been detected.
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============================================================================
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MODULE PARAMETERS
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Panic on UE control file:
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'edac_mc_panic_on_ue'
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An uncorrectable error will cause a machine panic. This is usually
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desirable. It is a bad idea to continue when an uncorrectable error
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occurs - it is indeterminate what was uncorrected and the operating
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system context might be so mangled that continuing will lead to further
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corruption. If the kernel has MCE configured, then EDAC will never
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notice the UE.
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LOAD TIME: module/kernel parameter: edac_mc_panic_on_ue=[0|1]
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RUN TIME: echo "1" > /sys/module/edac_core/parameters/edac_mc_panic_on_ue
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Log UE control file:
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'edac_mc_log_ue'
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Generate kernel messages describing uncorrectable errors. These errors
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are reported through the system message log system. UE statistics
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will be accumulated even when UE logging is disabled.
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LOAD TIME: module/kernel parameter: edac_mc_log_ue=[0|1]
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RUN TIME: echo "1" > /sys/module/edac_core/parameters/edac_mc_log_ue
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Log CE control file:
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'edac_mc_log_ce'
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Generate kernel messages describing correctable errors. These
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errors are reported through the system message log system.
|
|
CE statistics will be accumulated even when CE logging is disabled.
|
|
|
|
LOAD TIME: module/kernel parameter: edac_mc_log_ce=[0|1]
|
|
|
|
RUN TIME: echo "1" > /sys/module/edac_core/parameters/edac_mc_log_ce
|
|
|
|
|
|
Polling period control file:
|
|
|
|
'edac_mc_poll_msec'
|
|
|
|
The time period, in milliseconds, for polling for error information.
|
|
Too small a value wastes resources. Too large a value might delay
|
|
necessary handling of errors and might loose valuable information for
|
|
locating the error. 1000 milliseconds (once each second) is the current
|
|
default. Systems which require all the bandwidth they can get, may
|
|
increase this.
|
|
|
|
LOAD TIME: module/kernel parameter: edac_mc_poll_msec=[0|1]
|
|
|
|
RUN TIME: echo "1000" > /sys/module/edac_core/parameters/edac_mc_poll_msec
|
|
|
|
|
|
Panic on PCI PARITY Error:
|
|
|
|
'panic_on_pci_parity'
|
|
|
|
|
|
This control files enables or disables panicking when a parity
|
|
error has been detected.
|
|
|
|
|
|
module/kernel parameter: edac_panic_on_pci_pe=[0|1]
|
|
|
|
Enable:
|
|
echo "1" > /sys/module/edac_core/parameters/edac_panic_on_pci_pe
|
|
|
|
Disable:
|
|
echo "0" > /sys/module/edac_core/parameters/edac_panic_on_pci_pe
|
|
|
|
|
|
|
|
=======================================================================
|
|
|
|
|
|
EDAC_DEVICE type of device
|
|
|
|
In the header file, edac_core.h, there is a series of edac_device structures
|
|
and APIs for the EDAC_DEVICE.
|
|
|
|
User space access to an edac_device is through the sysfs interface.
|
|
|
|
At the location /sys/devices/system/edac (sysfs) new edac_device devices will
|
|
appear.
|
|
|
|
There is a three level tree beneath the above 'edac' directory. For example,
|
|
the 'test_device_edac' device (found at the bluesmoke.sourceforget.net website)
|
|
installs itself as:
|
|
|
|
/sys/devices/systm/edac/test-instance
|
|
|
|
in this directory are various controls, a symlink and one or more 'instance'
|
|
directorys.
|
|
|
|
The standard default controls are:
|
|
|
|
log_ce boolean to log CE events
|
|
log_ue boolean to log UE events
|
|
panic_on_ue boolean to 'panic' the system if an UE is encountered
|
|
(default off, can be set true via startup script)
|
|
poll_msec time period between POLL cycles for events
|
|
|
|
The test_device_edac device adds at least one of its own custom control:
|
|
|
|
test_bits which in the current test driver does nothing but
|
|
show how it is installed. A ported driver can
|
|
add one or more such controls and/or attributes
|
|
for specific uses.
|
|
One out-of-tree driver uses controls here to allow
|
|
for ERROR INJECTION operations to hardware
|
|
injection registers
|
|
|
|
The symlink points to the 'struct dev' that is registered for this edac_device.
|
|
|
|
INSTANCES
|
|
|
|
One or more instance directories are present. For the 'test_device_edac' case:
|
|
|
|
test-instance0
|
|
|
|
|
|
In this directory there are two default counter attributes, which are totals of
|
|
counter in deeper subdirectories.
|
|
|
|
ce_count total of CE events of subdirectories
|
|
ue_count total of UE events of subdirectories
|
|
|
|
BLOCKS
|
|
|
|
At the lowest directory level is the 'block' directory. There can be 0, 1
|
|
or more blocks specified in each instance.
|
|
|
|
test-block0
|
|
|
|
|
|
In this directory the default attributes are:
|
|
|
|
ce_count which is counter of CE events for this 'block'
|
|
of hardware being monitored
|
|
ue_count which is counter of UE events for this 'block'
|
|
of hardware being monitored
|
|
|
|
|
|
The 'test_device_edac' device adds 4 attributes and 1 control:
|
|
|
|
test-block-bits-0 for every POLL cycle this counter
|
|
is incremented
|
|
test-block-bits-1 every 10 cycles, this counter is bumped once,
|
|
and test-block-bits-0 is set to 0
|
|
test-block-bits-2 every 100 cycles, this counter is bumped once,
|
|
and test-block-bits-1 is set to 0
|
|
test-block-bits-3 every 1000 cycles, this counter is bumped once,
|
|
and test-block-bits-2 is set to 0
|
|
|
|
|
|
reset-counters writing ANY thing to this control will
|
|
reset all the above counters.
|
|
|
|
|
|
Use of the 'test_device_edac' driver should any others to create their own
|
|
unique drivers for their hardware systems.
|
|
|
|
The 'test_device_edac' sample driver is located at the
|
|
bluesmoke.sourceforge.net project site for EDAC.
|
|
|