443 lines
12 KiB
C
443 lines
12 KiB
C
/*******************************************************************************
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Intel 10 Gigabit PCI Express Linux driver
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Copyright(c) 1999 - 2011 Intel Corporation.
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This program is free software; you can redistribute it and/or modify it
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under the terms and conditions of the GNU General Public License,
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version 2, as published by the Free Software Foundation.
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This program is distributed in the hope it will be useful, but WITHOUT
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ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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more details.
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You should have received a copy of the GNU General Public License along with
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this program; if not, write to the Free Software Foundation, Inc.,
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51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
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The full GNU General Public License is included in this distribution in
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the file called "COPYING".
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Contact Information:
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e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
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Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
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*******************************************************************************/
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#include "ixgbe.h"
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#include "ixgbe_type.h"
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#include "ixgbe_dcb.h"
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#include "ixgbe_dcb_82599.h"
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/**
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* ixgbe_dcb_config_packet_buffers_82599 - Configure DCB packet buffers
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* @hw: pointer to hardware structure
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* @rx_pba: method to distribute packet buffer
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*
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* Configure packet buffers for DCB mode.
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*/
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static s32 ixgbe_dcb_config_packet_buffers_82599(struct ixgbe_hw *hw, u8 rx_pba)
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{
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s32 ret_val = 0;
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u32 value = IXGBE_RXPBSIZE_64KB;
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u8 i = 0;
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/* Setup Rx packet buffer sizes */
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switch (rx_pba) {
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case pba_80_48:
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/* Setup the first four at 80KB */
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value = IXGBE_RXPBSIZE_80KB;
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for (; i < 4; i++)
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IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(i), value);
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/* Setup the last four at 48KB...don't re-init i */
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value = IXGBE_RXPBSIZE_48KB;
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/* Fall Through */
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case pba_equal:
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default:
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for (; i < IXGBE_MAX_PACKET_BUFFERS; i++)
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IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(i), value);
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/* Setup Tx packet buffer sizes */
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for (i = 0; i < IXGBE_MAX_PACKET_BUFFERS; i++) {
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IXGBE_WRITE_REG(hw, IXGBE_TXPBSIZE(i),
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IXGBE_TXPBSIZE_20KB);
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IXGBE_WRITE_REG(hw, IXGBE_TXPBTHRESH(i),
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IXGBE_TXPBTHRESH_DCB);
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}
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break;
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}
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return ret_val;
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}
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/**
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* ixgbe_dcb_config_rx_arbiter_82599 - Config Rx Data arbiter
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* @hw: pointer to hardware structure
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* @refill: refill credits index by traffic class
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* @max: max credits index by traffic class
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* @bwg_id: bandwidth grouping indexed by traffic class
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* @prio_type: priority type indexed by traffic class
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*
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* Configure Rx Packet Arbiter and credits for each traffic class.
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*/
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s32 ixgbe_dcb_config_rx_arbiter_82599(struct ixgbe_hw *hw,
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u16 *refill,
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u16 *max,
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u8 *bwg_id,
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u8 *prio_type,
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u8 *prio_tc)
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{
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u32 reg = 0;
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u32 credit_refill = 0;
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u32 credit_max = 0;
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u8 i = 0;
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/*
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* Disable the arbiter before changing parameters
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* (always enable recycle mode; WSP)
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*/
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reg = IXGBE_RTRPCS_RRM | IXGBE_RTRPCS_RAC | IXGBE_RTRPCS_ARBDIS;
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IXGBE_WRITE_REG(hw, IXGBE_RTRPCS, reg);
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/* Map all traffic classes to their UP, 1 to 1 */
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reg = 0;
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for (i = 0; i < MAX_TRAFFIC_CLASS; i++)
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reg |= (prio_tc[i] << (i * IXGBE_RTRUP2TC_UP_SHIFT));
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IXGBE_WRITE_REG(hw, IXGBE_RTRUP2TC, reg);
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/* Configure traffic class credits and priority */
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for (i = 0; i < MAX_TRAFFIC_CLASS; i++) {
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credit_refill = refill[i];
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credit_max = max[i];
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reg = credit_refill | (credit_max << IXGBE_RTRPT4C_MCL_SHIFT);
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reg |= (u32)(bwg_id[i]) << IXGBE_RTRPT4C_BWG_SHIFT;
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if (prio_type[i] == prio_link)
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reg |= IXGBE_RTRPT4C_LSP;
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IXGBE_WRITE_REG(hw, IXGBE_RTRPT4C(i), reg);
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}
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/*
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* Configure Rx packet plane (recycle mode; WSP) and
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* enable arbiter
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*/
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reg = IXGBE_RTRPCS_RRM | IXGBE_RTRPCS_RAC;
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IXGBE_WRITE_REG(hw, IXGBE_RTRPCS, reg);
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return 0;
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}
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/**
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* ixgbe_dcb_config_tx_desc_arbiter_82599 - Config Tx Desc. arbiter
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* @hw: pointer to hardware structure
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* @refill: refill credits index by traffic class
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* @max: max credits index by traffic class
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* @bwg_id: bandwidth grouping indexed by traffic class
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* @prio_type: priority type indexed by traffic class
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*
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* Configure Tx Descriptor Arbiter and credits for each traffic class.
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*/
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s32 ixgbe_dcb_config_tx_desc_arbiter_82599(struct ixgbe_hw *hw,
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u16 *refill,
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u16 *max,
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u8 *bwg_id,
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u8 *prio_type)
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{
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u32 reg, max_credits;
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u8 i;
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/* Clear the per-Tx queue credits; we use per-TC instead */
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for (i = 0; i < 128; i++) {
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IXGBE_WRITE_REG(hw, IXGBE_RTTDQSEL, i);
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IXGBE_WRITE_REG(hw, IXGBE_RTTDT1C, 0);
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}
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/* Configure traffic class credits and priority */
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for (i = 0; i < MAX_TRAFFIC_CLASS; i++) {
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max_credits = max[i];
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reg = max_credits << IXGBE_RTTDT2C_MCL_SHIFT;
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reg |= refill[i];
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reg |= (u32)(bwg_id[i]) << IXGBE_RTTDT2C_BWG_SHIFT;
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if (prio_type[i] == prio_group)
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reg |= IXGBE_RTTDT2C_GSP;
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if (prio_type[i] == prio_link)
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reg |= IXGBE_RTTDT2C_LSP;
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IXGBE_WRITE_REG(hw, IXGBE_RTTDT2C(i), reg);
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}
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/*
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* Configure Tx descriptor plane (recycle mode; WSP) and
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* enable arbiter
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*/
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reg = IXGBE_RTTDCS_TDPAC | IXGBE_RTTDCS_TDRM;
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IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, reg);
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return 0;
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}
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/**
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* ixgbe_dcb_config_tx_data_arbiter_82599 - Config Tx Data arbiter
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* @hw: pointer to hardware structure
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* @refill: refill credits index by traffic class
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* @max: max credits index by traffic class
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* @bwg_id: bandwidth grouping indexed by traffic class
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* @prio_type: priority type indexed by traffic class
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*
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* Configure Tx Packet Arbiter and credits for each traffic class.
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*/
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s32 ixgbe_dcb_config_tx_data_arbiter_82599(struct ixgbe_hw *hw,
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u16 *refill,
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u16 *max,
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u8 *bwg_id,
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u8 *prio_type,
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u8 *prio_tc)
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{
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u32 reg;
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u8 i;
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/*
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* Disable the arbiter before changing parameters
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* (always enable recycle mode; SP; arb delay)
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*/
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reg = IXGBE_RTTPCS_TPPAC | IXGBE_RTTPCS_TPRM |
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(IXGBE_RTTPCS_ARBD_DCB << IXGBE_RTTPCS_ARBD_SHIFT) |
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IXGBE_RTTPCS_ARBDIS;
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IXGBE_WRITE_REG(hw, IXGBE_RTTPCS, reg);
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/* Map all traffic classes to their UP, 1 to 1 */
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reg = 0;
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for (i = 0; i < MAX_TRAFFIC_CLASS; i++)
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reg |= (prio_tc[i] << (i * IXGBE_RTTUP2TC_UP_SHIFT));
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IXGBE_WRITE_REG(hw, IXGBE_RTTUP2TC, reg);
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/* Configure traffic class credits and priority */
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for (i = 0; i < MAX_TRAFFIC_CLASS; i++) {
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reg = refill[i];
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reg |= (u32)(max[i]) << IXGBE_RTTPT2C_MCL_SHIFT;
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reg |= (u32)(bwg_id[i]) << IXGBE_RTTPT2C_BWG_SHIFT;
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if (prio_type[i] == prio_group)
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reg |= IXGBE_RTTPT2C_GSP;
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if (prio_type[i] == prio_link)
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reg |= IXGBE_RTTPT2C_LSP;
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IXGBE_WRITE_REG(hw, IXGBE_RTTPT2C(i), reg);
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}
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/*
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* Configure Tx packet plane (recycle mode; SP; arb delay) and
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* enable arbiter
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*/
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reg = IXGBE_RTTPCS_TPPAC | IXGBE_RTTPCS_TPRM |
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(IXGBE_RTTPCS_ARBD_DCB << IXGBE_RTTPCS_ARBD_SHIFT);
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IXGBE_WRITE_REG(hw, IXGBE_RTTPCS, reg);
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return 0;
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}
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/**
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* ixgbe_dcb_config_pfc_82599 - Configure priority flow control
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* @hw: pointer to hardware structure
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* @pfc_en: enabled pfc bitmask
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*
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* Configure Priority Flow Control (PFC) for each traffic class.
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*/
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s32 ixgbe_dcb_config_pfc_82599(struct ixgbe_hw *hw, u8 pfc_en)
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{
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u32 i, reg, rx_pba_size;
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/* Configure PFC Tx thresholds per TC */
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for (i = 0; i < MAX_TRAFFIC_CLASS; i++) {
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int enabled = pfc_en & (1 << i);
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rx_pba_size = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(i));
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rx_pba_size >>= IXGBE_RXPBSIZE_SHIFT;
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reg = (rx_pba_size - hw->fc.low_water) << 10;
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if (enabled)
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reg |= IXGBE_FCRTL_XONE;
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IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(i), reg);
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reg = (rx_pba_size - hw->fc.high_water) << 10;
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if (enabled)
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reg |= IXGBE_FCRTH_FCEN;
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IXGBE_WRITE_REG(hw, IXGBE_FCRTH_82599(i), reg);
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}
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if (pfc_en) {
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/* Configure pause time (2 TCs per register) */
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reg = hw->fc.pause_time | (hw->fc.pause_time << 16);
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for (i = 0; i < (MAX_TRAFFIC_CLASS / 2); i++)
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IXGBE_WRITE_REG(hw, IXGBE_FCTTV(i), reg);
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/* Configure flow control refresh threshold value */
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IXGBE_WRITE_REG(hw, IXGBE_FCRTV, hw->fc.pause_time / 2);
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reg = IXGBE_FCCFG_TFCE_PRIORITY;
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IXGBE_WRITE_REG(hw, IXGBE_FCCFG, reg);
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/*
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* Enable Receive PFC
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* We will always honor XOFF frames we receive when
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* we are in PFC mode.
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*/
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reg = IXGBE_READ_REG(hw, IXGBE_MFLCN);
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reg &= ~IXGBE_MFLCN_RFCE;
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reg |= IXGBE_MFLCN_RPFCE | IXGBE_MFLCN_DPF;
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IXGBE_WRITE_REG(hw, IXGBE_MFLCN, reg);
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} else {
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for (i = 0; i < MAX_TRAFFIC_CLASS; i++)
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hw->mac.ops.fc_enable(hw, i);
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}
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return 0;
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}
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/**
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* ixgbe_dcb_config_tc_stats_82599 - Config traffic class statistics
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* @hw: pointer to hardware structure
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*
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* Configure queue statistics registers, all queues belonging to same traffic
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* class uses a single set of queue statistics counters.
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*/
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static s32 ixgbe_dcb_config_tc_stats_82599(struct ixgbe_hw *hw)
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{
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u32 reg = 0;
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u8 i = 0;
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/*
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* Receive Queues stats setting
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* 32 RQSMR registers, each configuring 4 queues.
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* Set all 16 queues of each TC to the same stat
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* with TC 'n' going to stat 'n'.
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*/
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for (i = 0; i < 32; i++) {
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reg = 0x01010101 * (i / 4);
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IXGBE_WRITE_REG(hw, IXGBE_RQSMR(i), reg);
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}
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/*
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* Transmit Queues stats setting
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* 32 TQSM registers, each controlling 4 queues.
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* Set all queues of each TC to the same stat
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* with TC 'n' going to stat 'n'.
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* Tx queues are allocated non-uniformly to TCs:
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* 32, 32, 16, 16, 8, 8, 8, 8.
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*/
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for (i = 0; i < 32; i++) {
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if (i < 8)
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reg = 0x00000000;
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else if (i < 16)
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reg = 0x01010101;
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else if (i < 20)
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reg = 0x02020202;
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else if (i < 24)
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reg = 0x03030303;
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else if (i < 26)
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reg = 0x04040404;
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else if (i < 28)
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reg = 0x05050505;
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else if (i < 30)
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reg = 0x06060606;
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else
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reg = 0x07070707;
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IXGBE_WRITE_REG(hw, IXGBE_TQSM(i), reg);
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}
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return 0;
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}
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/**
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* ixgbe_dcb_config_82599 - Configure general DCB parameters
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* @hw: pointer to hardware structure
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*
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* Configure general DCB parameters.
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*/
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static s32 ixgbe_dcb_config_82599(struct ixgbe_hw *hw)
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{
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u32 reg;
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u32 q;
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/* Disable the Tx desc arbiter so that MTQC can be changed */
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reg = IXGBE_READ_REG(hw, IXGBE_RTTDCS);
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reg |= IXGBE_RTTDCS_ARBDIS;
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IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, reg);
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/* Enable DCB for Rx with 8 TCs */
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reg = IXGBE_READ_REG(hw, IXGBE_MRQC);
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switch (reg & IXGBE_MRQC_MRQE_MASK) {
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case 0:
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case IXGBE_MRQC_RT4TCEN:
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/* RSS disabled cases */
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reg = (reg & ~IXGBE_MRQC_MRQE_MASK) | IXGBE_MRQC_RT8TCEN;
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break;
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case IXGBE_MRQC_RSSEN:
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case IXGBE_MRQC_RTRSS4TCEN:
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/* RSS enabled cases */
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reg = (reg & ~IXGBE_MRQC_MRQE_MASK) | IXGBE_MRQC_RTRSS8TCEN;
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break;
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default:
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/* Unsupported value, assume stale data, overwrite no RSS */
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reg = (reg & ~IXGBE_MRQC_MRQE_MASK) | IXGBE_MRQC_RT8TCEN;
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}
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IXGBE_WRITE_REG(hw, IXGBE_MRQC, reg);
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/* Enable DCB for Tx with 8 TCs */
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reg = IXGBE_MTQC_RT_ENA | IXGBE_MTQC_8TC_8TQ;
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IXGBE_WRITE_REG(hw, IXGBE_MTQC, reg);
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/* Disable drop for all queues */
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for (q = 0; q < 128; q++)
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IXGBE_WRITE_REG(hw, IXGBE_QDE, q << IXGBE_QDE_IDX_SHIFT);
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/* Enable the Tx desc arbiter */
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reg = IXGBE_READ_REG(hw, IXGBE_RTTDCS);
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reg &= ~IXGBE_RTTDCS_ARBDIS;
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IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, reg);
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/* Enable Security TX Buffer IFG for DCB */
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reg = IXGBE_READ_REG(hw, IXGBE_SECTXMINIFG);
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reg |= IXGBE_SECTX_DCB;
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IXGBE_WRITE_REG(hw, IXGBE_SECTXMINIFG, reg);
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return 0;
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}
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/**
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* ixgbe_dcb_hw_config_82599 - Configure and enable DCB
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* @hw: pointer to hardware structure
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* @rx_pba: method to distribute packet buffer
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* @refill: refill credits index by traffic class
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* @max: max credits index by traffic class
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* @bwg_id: bandwidth grouping indexed by traffic class
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* @prio_type: priority type indexed by traffic class
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* @pfc_en: enabled pfc bitmask
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*
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* Configure dcb settings and enable dcb mode.
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*/
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s32 ixgbe_dcb_hw_config_82599(struct ixgbe_hw *hw,
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u8 rx_pba, u8 pfc_en, u16 *refill,
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u16 *max, u8 *bwg_id, u8 *prio_type, u8 *prio_tc)
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{
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ixgbe_dcb_config_packet_buffers_82599(hw, rx_pba);
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ixgbe_dcb_config_82599(hw);
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ixgbe_dcb_config_rx_arbiter_82599(hw, refill, max, bwg_id,
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prio_type, prio_tc);
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ixgbe_dcb_config_tx_desc_arbiter_82599(hw, refill, max,
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bwg_id, prio_type);
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ixgbe_dcb_config_tx_data_arbiter_82599(hw, refill, max,
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bwg_id, prio_type, prio_tc);
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ixgbe_dcb_config_pfc_82599(hw, pfc_en);
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ixgbe_dcb_config_tc_stats_82599(hw);
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return 0;
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}
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