1340 lines
42 KiB
C
1340 lines
42 KiB
C
/*
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* S3C24XX IRQ handling
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*
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* Copyright (c) 2003-2004 Simtec Electronics
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* Ben Dooks <ben@simtec.co.uk>
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* Copyright (c) 2012 Heiko Stuebner <heiko@sntech.de>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <linux/init.h>
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#include <linux/slab.h>
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#include <linux/module.h>
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#include <linux/io.h>
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#include <linux/err.h>
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#include <linux/interrupt.h>
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#include <linux/ioport.h>
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#include <linux/device.h>
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#include <linux/irqdomain.h>
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#include <linux/irqchip.h>
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#include <linux/irqchip/chained_irq.h>
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#include <linux/of.h>
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#include <linux/of_irq.h>
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#include <linux/of_address.h>
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#include <asm/exception.h>
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#include <asm/mach/irq.h>
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#include <mach/regs-irq.h>
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#include <mach/regs-gpio.h>
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#include <plat/cpu.h>
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#include <plat/regs-irqtype.h>
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#include <plat/pm.h>
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#define S3C_IRQTYPE_NONE 0
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#define S3C_IRQTYPE_EINT 1
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#define S3C_IRQTYPE_EDGE 2
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#define S3C_IRQTYPE_LEVEL 3
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struct s3c_irq_data {
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unsigned int type;
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unsigned long offset;
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unsigned long parent_irq;
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/* data gets filled during init */
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struct s3c_irq_intc *intc;
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unsigned long sub_bits;
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struct s3c_irq_intc *sub_intc;
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};
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/*
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* Sructure holding the controller data
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* @reg_pending register holding pending irqs
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* @reg_intpnd special register intpnd in main intc
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* @reg_mask mask register
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* @domain irq_domain of the controller
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* @parent parent controller for ext and sub irqs
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* @irqs irq-data, always s3c_irq_data[32]
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*/
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struct s3c_irq_intc {
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void __iomem *reg_pending;
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void __iomem *reg_intpnd;
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void __iomem *reg_mask;
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struct irq_domain *domain;
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struct s3c_irq_intc *parent;
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struct s3c_irq_data *irqs;
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};
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/*
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* Array holding pointers to the global controller structs
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* [0] ... main_intc
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* [1] ... sub_intc
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* [2] ... main_intc2 on s3c2416
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*/
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static struct s3c_irq_intc *s3c_intc[3];
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static void s3c_irq_mask(struct irq_data *data)
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{
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struct s3c_irq_data *irq_data = irq_data_get_irq_chip_data(data);
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struct s3c_irq_intc *intc = irq_data->intc;
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struct s3c_irq_intc *parent_intc = intc->parent;
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struct s3c_irq_data *parent_data;
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unsigned long mask;
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unsigned int irqno;
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mask = readl_relaxed(intc->reg_mask);
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mask |= (1UL << irq_data->offset);
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writel_relaxed(mask, intc->reg_mask);
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if (parent_intc) {
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parent_data = &parent_intc->irqs[irq_data->parent_irq];
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/* check to see if we need to mask the parent IRQ
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* The parent_irq is always in main_intc, so the hwirq
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* for find_mapping does not need an offset in any case.
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*/
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if ((mask & parent_data->sub_bits) == parent_data->sub_bits) {
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irqno = irq_find_mapping(parent_intc->domain,
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irq_data->parent_irq);
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s3c_irq_mask(irq_get_irq_data(irqno));
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}
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}
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}
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static void s3c_irq_unmask(struct irq_data *data)
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{
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struct s3c_irq_data *irq_data = irq_data_get_irq_chip_data(data);
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struct s3c_irq_intc *intc = irq_data->intc;
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struct s3c_irq_intc *parent_intc = intc->parent;
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unsigned long mask;
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unsigned int irqno;
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mask = readl_relaxed(intc->reg_mask);
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mask &= ~(1UL << irq_data->offset);
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writel_relaxed(mask, intc->reg_mask);
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if (parent_intc) {
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irqno = irq_find_mapping(parent_intc->domain,
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irq_data->parent_irq);
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s3c_irq_unmask(irq_get_irq_data(irqno));
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}
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}
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static inline void s3c_irq_ack(struct irq_data *data)
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{
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struct s3c_irq_data *irq_data = irq_data_get_irq_chip_data(data);
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struct s3c_irq_intc *intc = irq_data->intc;
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unsigned long bitval = 1UL << irq_data->offset;
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writel_relaxed(bitval, intc->reg_pending);
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if (intc->reg_intpnd)
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writel_relaxed(bitval, intc->reg_intpnd);
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}
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static int s3c_irq_type(struct irq_data *data, unsigned int type)
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{
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switch (type) {
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case IRQ_TYPE_NONE:
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break;
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case IRQ_TYPE_EDGE_RISING:
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case IRQ_TYPE_EDGE_FALLING:
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case IRQ_TYPE_EDGE_BOTH:
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irq_set_handler(data->irq, handle_edge_irq);
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break;
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case IRQ_TYPE_LEVEL_LOW:
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case IRQ_TYPE_LEVEL_HIGH:
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irq_set_handler(data->irq, handle_level_irq);
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break;
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default:
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pr_err("No such irq type %d\n", type);
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return -EINVAL;
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}
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return 0;
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}
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static int s3c_irqext_type_set(void __iomem *gpcon_reg,
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void __iomem *extint_reg,
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unsigned long gpcon_offset,
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unsigned long extint_offset,
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unsigned int type)
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{
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unsigned long newvalue = 0, value;
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/* Set the GPIO to external interrupt mode */
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value = readl_relaxed(gpcon_reg);
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value = (value & ~(3 << gpcon_offset)) | (0x02 << gpcon_offset);
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writel_relaxed(value, gpcon_reg);
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/* Set the external interrupt to pointed trigger type */
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switch (type)
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{
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case IRQ_TYPE_NONE:
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pr_warn("No edge setting!\n");
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break;
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case IRQ_TYPE_EDGE_RISING:
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newvalue = S3C2410_EXTINT_RISEEDGE;
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break;
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case IRQ_TYPE_EDGE_FALLING:
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newvalue = S3C2410_EXTINT_FALLEDGE;
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break;
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case IRQ_TYPE_EDGE_BOTH:
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newvalue = S3C2410_EXTINT_BOTHEDGE;
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break;
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case IRQ_TYPE_LEVEL_LOW:
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newvalue = S3C2410_EXTINT_LOWLEV;
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break;
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case IRQ_TYPE_LEVEL_HIGH:
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newvalue = S3C2410_EXTINT_HILEV;
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break;
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default:
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pr_err("No such irq type %d\n", type);
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return -EINVAL;
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}
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value = readl_relaxed(extint_reg);
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value = (value & ~(7 << extint_offset)) | (newvalue << extint_offset);
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writel_relaxed(value, extint_reg);
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return 0;
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}
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static int s3c_irqext_type(struct irq_data *data, unsigned int type)
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{
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void __iomem *extint_reg;
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void __iomem *gpcon_reg;
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unsigned long gpcon_offset, extint_offset;
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if ((data->hwirq >= 4) && (data->hwirq <= 7)) {
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gpcon_reg = S3C2410_GPFCON;
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extint_reg = S3C24XX_EXTINT0;
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gpcon_offset = (data->hwirq) * 2;
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extint_offset = (data->hwirq) * 4;
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} else if ((data->hwirq >= 8) && (data->hwirq <= 15)) {
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gpcon_reg = S3C2410_GPGCON;
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extint_reg = S3C24XX_EXTINT1;
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gpcon_offset = (data->hwirq - 8) * 2;
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extint_offset = (data->hwirq - 8) * 4;
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} else if ((data->hwirq >= 16) && (data->hwirq <= 23)) {
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gpcon_reg = S3C2410_GPGCON;
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extint_reg = S3C24XX_EXTINT2;
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gpcon_offset = (data->hwirq - 8) * 2;
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extint_offset = (data->hwirq - 16) * 4;
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} else {
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return -EINVAL;
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}
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return s3c_irqext_type_set(gpcon_reg, extint_reg, gpcon_offset,
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extint_offset, type);
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}
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static int s3c_irqext0_type(struct irq_data *data, unsigned int type)
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{
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void __iomem *extint_reg;
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void __iomem *gpcon_reg;
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unsigned long gpcon_offset, extint_offset;
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if ((data->hwirq >= 0) && (data->hwirq <= 3)) {
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gpcon_reg = S3C2410_GPFCON;
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extint_reg = S3C24XX_EXTINT0;
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gpcon_offset = (data->hwirq) * 2;
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extint_offset = (data->hwirq) * 4;
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} else {
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return -EINVAL;
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}
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return s3c_irqext_type_set(gpcon_reg, extint_reg, gpcon_offset,
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extint_offset, type);
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}
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static struct irq_chip s3c_irq_chip = {
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.name = "s3c",
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.irq_ack = s3c_irq_ack,
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.irq_mask = s3c_irq_mask,
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.irq_unmask = s3c_irq_unmask,
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.irq_set_type = s3c_irq_type,
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.irq_set_wake = s3c_irq_wake
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};
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static struct irq_chip s3c_irq_level_chip = {
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.name = "s3c-level",
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.irq_mask = s3c_irq_mask,
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.irq_unmask = s3c_irq_unmask,
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.irq_ack = s3c_irq_ack,
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.irq_set_type = s3c_irq_type,
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};
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static struct irq_chip s3c_irqext_chip = {
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.name = "s3c-ext",
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.irq_mask = s3c_irq_mask,
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.irq_unmask = s3c_irq_unmask,
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.irq_ack = s3c_irq_ack,
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.irq_set_type = s3c_irqext_type,
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.irq_set_wake = s3c_irqext_wake
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};
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static struct irq_chip s3c_irq_eint0t4 = {
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.name = "s3c-ext0",
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.irq_ack = s3c_irq_ack,
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.irq_mask = s3c_irq_mask,
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.irq_unmask = s3c_irq_unmask,
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.irq_set_wake = s3c_irq_wake,
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.irq_set_type = s3c_irqext0_type,
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};
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static void s3c_irq_demux(struct irq_desc *desc)
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{
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struct irq_chip *chip = irq_desc_get_chip(desc);
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struct s3c_irq_data *irq_data = irq_desc_get_chip_data(desc);
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struct s3c_irq_intc *intc = irq_data->intc;
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struct s3c_irq_intc *sub_intc = irq_data->sub_intc;
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unsigned int n, offset, irq;
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unsigned long src, msk;
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/* we're using individual domains for the non-dt case
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* and one big domain for the dt case where the subintc
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* starts at hwirq number 32.
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*/
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offset = irq_domain_get_of_node(intc->domain) ? 32 : 0;
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chained_irq_enter(chip, desc);
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src = readl_relaxed(sub_intc->reg_pending);
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msk = readl_relaxed(sub_intc->reg_mask);
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src &= ~msk;
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src &= irq_data->sub_bits;
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while (src) {
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n = __ffs(src);
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src &= ~(1 << n);
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irq = irq_find_mapping(sub_intc->domain, offset + n);
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generic_handle_irq(irq);
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}
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chained_irq_exit(chip, desc);
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}
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static inline int s3c24xx_handle_intc(struct s3c_irq_intc *intc,
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struct pt_regs *regs, int intc_offset)
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{
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int pnd;
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int offset;
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pnd = readl_relaxed(intc->reg_intpnd);
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if (!pnd)
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return false;
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/* non-dt machines use individual domains */
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if (!irq_domain_get_of_node(intc->domain))
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intc_offset = 0;
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/* We have a problem that the INTOFFSET register does not always
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* show one interrupt. Occasionally we get two interrupts through
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* the prioritiser, and this causes the INTOFFSET register to show
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* what looks like the logical-or of the two interrupt numbers.
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*
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* Thanks to Klaus, Shannon, et al for helping to debug this problem
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*/
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offset = readl_relaxed(intc->reg_intpnd + 4);
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/* Find the bit manually, when the offset is wrong.
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* The pending register only ever contains the one bit of the next
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* interrupt to handle.
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*/
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if (!(pnd & (1 << offset)))
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offset = __ffs(pnd);
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handle_domain_irq(intc->domain, intc_offset + offset, regs);
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return true;
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}
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asmlinkage void __exception_irq_entry s3c24xx_handle_irq(struct pt_regs *regs)
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{
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do {
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if (likely(s3c_intc[0]))
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if (s3c24xx_handle_intc(s3c_intc[0], regs, 0))
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continue;
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if (s3c_intc[2])
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if (s3c24xx_handle_intc(s3c_intc[2], regs, 64))
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continue;
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break;
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} while (1);
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}
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#ifdef CONFIG_FIQ
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/**
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* s3c24xx_set_fiq - set the FIQ routing
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* @irq: IRQ number to route to FIQ on processor.
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* @on: Whether to route @irq to the FIQ, or to remove the FIQ routing.
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*
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* Change the state of the IRQ to FIQ routing depending on @irq and @on. If
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* @on is true, the @irq is checked to see if it can be routed and the
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* interrupt controller updated to route the IRQ. If @on is false, the FIQ
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* routing is cleared, regardless of which @irq is specified.
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*/
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int s3c24xx_set_fiq(unsigned int irq, bool on)
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{
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u32 intmod;
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unsigned offs;
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if (on) {
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offs = irq - FIQ_START;
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if (offs > 31)
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return -EINVAL;
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intmod = 1 << offs;
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} else {
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intmod = 0;
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}
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writel_relaxed(intmod, S3C2410_INTMOD);
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return 0;
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}
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EXPORT_SYMBOL_GPL(s3c24xx_set_fiq);
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#endif
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static int s3c24xx_irq_map(struct irq_domain *h, unsigned int virq,
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irq_hw_number_t hw)
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{
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struct s3c_irq_intc *intc = h->host_data;
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struct s3c_irq_data *irq_data = &intc->irqs[hw];
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struct s3c_irq_intc *parent_intc;
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struct s3c_irq_data *parent_irq_data;
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unsigned int irqno;
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/* attach controller pointer to irq_data */
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irq_data->intc = intc;
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irq_data->offset = hw;
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parent_intc = intc->parent;
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/* set handler and flags */
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switch (irq_data->type) {
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case S3C_IRQTYPE_NONE:
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return 0;
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case S3C_IRQTYPE_EINT:
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/* On the S3C2412, the EINT0to3 have a parent irq
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* but need the s3c_irq_eint0t4 chip
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*/
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if (parent_intc && (!soc_is_s3c2412() || hw >= 4))
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irq_set_chip_and_handler(virq, &s3c_irqext_chip,
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handle_edge_irq);
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else
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irq_set_chip_and_handler(virq, &s3c_irq_eint0t4,
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handle_edge_irq);
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break;
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case S3C_IRQTYPE_EDGE:
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if (parent_intc || intc->reg_pending == S3C2416_SRCPND2)
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irq_set_chip_and_handler(virq, &s3c_irq_level_chip,
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handle_edge_irq);
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else
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irq_set_chip_and_handler(virq, &s3c_irq_chip,
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handle_edge_irq);
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break;
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case S3C_IRQTYPE_LEVEL:
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if (parent_intc)
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irq_set_chip_and_handler(virq, &s3c_irq_level_chip,
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handle_level_irq);
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else
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irq_set_chip_and_handler(virq, &s3c_irq_chip,
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handle_level_irq);
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break;
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default:
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pr_err("irq-s3c24xx: unsupported irqtype %d\n", irq_data->type);
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return -EINVAL;
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}
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irq_set_chip_data(virq, irq_data);
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if (parent_intc && irq_data->type != S3C_IRQTYPE_NONE) {
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if (irq_data->parent_irq > 31) {
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pr_err("irq-s3c24xx: parent irq %lu is out of range\n",
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irq_data->parent_irq);
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return -EINVAL;
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}
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parent_irq_data = &parent_intc->irqs[irq_data->parent_irq];
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parent_irq_data->sub_intc = intc;
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parent_irq_data->sub_bits |= (1UL << hw);
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/* attach the demuxer to the parent irq */
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irqno = irq_find_mapping(parent_intc->domain,
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irq_data->parent_irq);
|
|
if (!irqno) {
|
|
pr_err("irq-s3c24xx: could not find mapping for parent irq %lu\n",
|
|
irq_data->parent_irq);
|
|
return -EINVAL;
|
|
}
|
|
irq_set_chained_handler(irqno, s3c_irq_demux);
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
static const struct irq_domain_ops s3c24xx_irq_ops = {
|
|
.map = s3c24xx_irq_map,
|
|
.xlate = irq_domain_xlate_twocell,
|
|
};
|
|
|
|
static void s3c24xx_clear_intc(struct s3c_irq_intc *intc)
|
|
{
|
|
void __iomem *reg_source;
|
|
unsigned long pend;
|
|
unsigned long last;
|
|
int i;
|
|
|
|
/* if intpnd is set, read the next pending irq from there */
|
|
reg_source = intc->reg_intpnd ? intc->reg_intpnd : intc->reg_pending;
|
|
|
|
last = 0;
|
|
for (i = 0; i < 4; i++) {
|
|
pend = readl_relaxed(reg_source);
|
|
|
|
if (pend == 0 || pend == last)
|
|
break;
|
|
|
|
writel_relaxed(pend, intc->reg_pending);
|
|
if (intc->reg_intpnd)
|
|
writel_relaxed(pend, intc->reg_intpnd);
|
|
|
|
pr_info("irq: clearing pending status %08x\n", (int)pend);
|
|
last = pend;
|
|
}
|
|
}
|
|
|
|
static struct s3c_irq_intc * __init s3c24xx_init_intc(struct device_node *np,
|
|
struct s3c_irq_data *irq_data,
|
|
struct s3c_irq_intc *parent,
|
|
unsigned long address)
|
|
{
|
|
struct s3c_irq_intc *intc;
|
|
void __iomem *base = (void *)0xf6000000; /* static mapping */
|
|
int irq_num;
|
|
int irq_start;
|
|
int ret;
|
|
|
|
intc = kzalloc(sizeof(struct s3c_irq_intc), GFP_KERNEL);
|
|
if (!intc)
|
|
return ERR_PTR(-ENOMEM);
|
|
|
|
intc->irqs = irq_data;
|
|
|
|
if (parent)
|
|
intc->parent = parent;
|
|
|
|
/* select the correct data for the controller.
|
|
* Need to hard code the irq num start and offset
|
|
* to preserve the static mapping for now
|
|
*/
|
|
switch (address) {
|
|
case 0x4a000000:
|
|
pr_debug("irq: found main intc\n");
|
|
intc->reg_pending = base;
|
|
intc->reg_mask = base + 0x08;
|
|
intc->reg_intpnd = base + 0x10;
|
|
irq_num = 32;
|
|
irq_start = S3C2410_IRQ(0);
|
|
break;
|
|
case 0x4a000018:
|
|
pr_debug("irq: found subintc\n");
|
|
intc->reg_pending = base + 0x18;
|
|
intc->reg_mask = base + 0x1c;
|
|
irq_num = 29;
|
|
irq_start = S3C2410_IRQSUB(0);
|
|
break;
|
|
case 0x4a000040:
|
|
pr_debug("irq: found intc2\n");
|
|
intc->reg_pending = base + 0x40;
|
|
intc->reg_mask = base + 0x48;
|
|
intc->reg_intpnd = base + 0x50;
|
|
irq_num = 8;
|
|
irq_start = S3C2416_IRQ(0);
|
|
break;
|
|
case 0x560000a4:
|
|
pr_debug("irq: found eintc\n");
|
|
base = (void *)0xfd000000;
|
|
|
|
intc->reg_mask = base + 0xa4;
|
|
intc->reg_pending = base + 0xa8;
|
|
irq_num = 24;
|
|
irq_start = S3C2410_IRQ(32);
|
|
break;
|
|
default:
|
|
pr_err("irq: unsupported controller address\n");
|
|
ret = -EINVAL;
|
|
goto err;
|
|
}
|
|
|
|
/* now that all the data is complete, init the irq-domain */
|
|
s3c24xx_clear_intc(intc);
|
|
intc->domain = irq_domain_add_legacy(np, irq_num, irq_start,
|
|
0, &s3c24xx_irq_ops,
|
|
intc);
|
|
if (!intc->domain) {
|
|
pr_err("irq: could not create irq-domain\n");
|
|
ret = -EINVAL;
|
|
goto err;
|
|
}
|
|
|
|
set_handle_irq(s3c24xx_handle_irq);
|
|
|
|
return intc;
|
|
|
|
err:
|
|
kfree(intc);
|
|
return ERR_PTR(ret);
|
|
}
|
|
|
|
static struct s3c_irq_data __maybe_unused init_eint[32] = {
|
|
{ .type = S3C_IRQTYPE_NONE, }, /* reserved */
|
|
{ .type = S3C_IRQTYPE_NONE, }, /* reserved */
|
|
{ .type = S3C_IRQTYPE_NONE, }, /* reserved */
|
|
{ .type = S3C_IRQTYPE_NONE, }, /* reserved */
|
|
{ .type = S3C_IRQTYPE_EINT, .parent_irq = 4 }, /* EINT4 */
|
|
{ .type = S3C_IRQTYPE_EINT, .parent_irq = 4 }, /* EINT5 */
|
|
{ .type = S3C_IRQTYPE_EINT, .parent_irq = 4 }, /* EINT6 */
|
|
{ .type = S3C_IRQTYPE_EINT, .parent_irq = 4 }, /* EINT7 */
|
|
{ .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT8 */
|
|
{ .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT9 */
|
|
{ .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT10 */
|
|
{ .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT11 */
|
|
{ .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT12 */
|
|
{ .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT13 */
|
|
{ .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT14 */
|
|
{ .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT15 */
|
|
{ .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT16 */
|
|
{ .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT17 */
|
|
{ .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT18 */
|
|
{ .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT19 */
|
|
{ .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT20 */
|
|
{ .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT21 */
|
|
{ .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT22 */
|
|
{ .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT23 */
|
|
};
|
|
|
|
#ifdef CONFIG_CPU_S3C2410
|
|
static struct s3c_irq_data init_s3c2410base[32] = {
|
|
{ .type = S3C_IRQTYPE_EINT, }, /* EINT0 */
|
|
{ .type = S3C_IRQTYPE_EINT, }, /* EINT1 */
|
|
{ .type = S3C_IRQTYPE_EINT, }, /* EINT2 */
|
|
{ .type = S3C_IRQTYPE_EINT, }, /* EINT3 */
|
|
{ .type = S3C_IRQTYPE_LEVEL, }, /* EINT4to7 */
|
|
{ .type = S3C_IRQTYPE_LEVEL, }, /* EINT8to23 */
|
|
{ .type = S3C_IRQTYPE_NONE, }, /* reserved */
|
|
{ .type = S3C_IRQTYPE_EDGE, }, /* nBATT_FLT */
|
|
{ .type = S3C_IRQTYPE_EDGE, }, /* TICK */
|
|
{ .type = S3C_IRQTYPE_EDGE, }, /* WDT */
|
|
{ .type = S3C_IRQTYPE_EDGE, }, /* TIMER0 */
|
|
{ .type = S3C_IRQTYPE_EDGE, }, /* TIMER1 */
|
|
{ .type = S3C_IRQTYPE_EDGE, }, /* TIMER2 */
|
|
{ .type = S3C_IRQTYPE_EDGE, }, /* TIMER3 */
|
|
{ .type = S3C_IRQTYPE_EDGE, }, /* TIMER4 */
|
|
{ .type = S3C_IRQTYPE_LEVEL, }, /* UART2 */
|
|
{ .type = S3C_IRQTYPE_EDGE, }, /* LCD */
|
|
{ .type = S3C_IRQTYPE_EDGE, }, /* DMA0 */
|
|
{ .type = S3C_IRQTYPE_EDGE, }, /* DMA1 */
|
|
{ .type = S3C_IRQTYPE_EDGE, }, /* DMA2 */
|
|
{ .type = S3C_IRQTYPE_EDGE, }, /* DMA3 */
|
|
{ .type = S3C_IRQTYPE_EDGE, }, /* SDI */
|
|
{ .type = S3C_IRQTYPE_EDGE, }, /* SPI0 */
|
|
{ .type = S3C_IRQTYPE_LEVEL, }, /* UART1 */
|
|
{ .type = S3C_IRQTYPE_NONE, }, /* reserved */
|
|
{ .type = S3C_IRQTYPE_EDGE, }, /* USBD */
|
|
{ .type = S3C_IRQTYPE_EDGE, }, /* USBH */
|
|
{ .type = S3C_IRQTYPE_EDGE, }, /* IIC */
|
|
{ .type = S3C_IRQTYPE_LEVEL, }, /* UART0 */
|
|
{ .type = S3C_IRQTYPE_EDGE, }, /* SPI1 */
|
|
{ .type = S3C_IRQTYPE_EDGE, }, /* RTC */
|
|
{ .type = S3C_IRQTYPE_LEVEL, }, /* ADCPARENT */
|
|
};
|
|
|
|
static struct s3c_irq_data init_s3c2410subint[32] = {
|
|
{ .type = S3C_IRQTYPE_LEVEL, .parent_irq = 28 }, /* UART0-RX */
|
|
{ .type = S3C_IRQTYPE_LEVEL, .parent_irq = 28 }, /* UART0-TX */
|
|
{ .type = S3C_IRQTYPE_LEVEL, .parent_irq = 28 }, /* UART0-ERR */
|
|
{ .type = S3C_IRQTYPE_LEVEL, .parent_irq = 23 }, /* UART1-RX */
|
|
{ .type = S3C_IRQTYPE_LEVEL, .parent_irq = 23 }, /* UART1-TX */
|
|
{ .type = S3C_IRQTYPE_LEVEL, .parent_irq = 23 }, /* UART1-ERR */
|
|
{ .type = S3C_IRQTYPE_LEVEL, .parent_irq = 15 }, /* UART2-RX */
|
|
{ .type = S3C_IRQTYPE_LEVEL, .parent_irq = 15 }, /* UART2-TX */
|
|
{ .type = S3C_IRQTYPE_LEVEL, .parent_irq = 15 }, /* UART2-ERR */
|
|
{ .type = S3C_IRQTYPE_EDGE, .parent_irq = 31 }, /* TC */
|
|
{ .type = S3C_IRQTYPE_EDGE, .parent_irq = 31 }, /* ADC */
|
|
};
|
|
|
|
void __init s3c2410_init_irq(void)
|
|
{
|
|
#ifdef CONFIG_FIQ
|
|
init_FIQ(FIQ_START);
|
|
#endif
|
|
|
|
s3c_intc[0] = s3c24xx_init_intc(NULL, &init_s3c2410base[0], NULL,
|
|
0x4a000000);
|
|
if (IS_ERR(s3c_intc[0])) {
|
|
pr_err("irq: could not create main interrupt controller\n");
|
|
return;
|
|
}
|
|
|
|
s3c_intc[1] = s3c24xx_init_intc(NULL, &init_s3c2410subint[0],
|
|
s3c_intc[0], 0x4a000018);
|
|
s3c24xx_init_intc(NULL, &init_eint[0], s3c_intc[0], 0x560000a4);
|
|
}
|
|
#endif
|
|
|
|
#ifdef CONFIG_CPU_S3C2412
|
|
static struct s3c_irq_data init_s3c2412base[32] = {
|
|
{ .type = S3C_IRQTYPE_LEVEL, }, /* EINT0 */
|
|
{ .type = S3C_IRQTYPE_LEVEL, }, /* EINT1 */
|
|
{ .type = S3C_IRQTYPE_LEVEL, }, /* EINT2 */
|
|
{ .type = S3C_IRQTYPE_LEVEL, }, /* EINT3 */
|
|
{ .type = S3C_IRQTYPE_LEVEL, }, /* EINT4to7 */
|
|
{ .type = S3C_IRQTYPE_LEVEL, }, /* EINT8to23 */
|
|
{ .type = S3C_IRQTYPE_NONE, }, /* reserved */
|
|
{ .type = S3C_IRQTYPE_EDGE, }, /* nBATT_FLT */
|
|
{ .type = S3C_IRQTYPE_EDGE, }, /* TICK */
|
|
{ .type = S3C_IRQTYPE_EDGE, }, /* WDT */
|
|
{ .type = S3C_IRQTYPE_EDGE, }, /* TIMER0 */
|
|
{ .type = S3C_IRQTYPE_EDGE, }, /* TIMER1 */
|
|
{ .type = S3C_IRQTYPE_EDGE, }, /* TIMER2 */
|
|
{ .type = S3C_IRQTYPE_EDGE, }, /* TIMER3 */
|
|
{ .type = S3C_IRQTYPE_EDGE, }, /* TIMER4 */
|
|
{ .type = S3C_IRQTYPE_LEVEL, }, /* UART2 */
|
|
{ .type = S3C_IRQTYPE_EDGE, }, /* LCD */
|
|
{ .type = S3C_IRQTYPE_EDGE, }, /* DMA0 */
|
|
{ .type = S3C_IRQTYPE_EDGE, }, /* DMA1 */
|
|
{ .type = S3C_IRQTYPE_EDGE, }, /* DMA2 */
|
|
{ .type = S3C_IRQTYPE_EDGE, }, /* DMA3 */
|
|
{ .type = S3C_IRQTYPE_LEVEL, }, /* SDI/CF */
|
|
{ .type = S3C_IRQTYPE_EDGE, }, /* SPI0 */
|
|
{ .type = S3C_IRQTYPE_LEVEL, }, /* UART1 */
|
|
{ .type = S3C_IRQTYPE_NONE, }, /* reserved */
|
|
{ .type = S3C_IRQTYPE_EDGE, }, /* USBD */
|
|
{ .type = S3C_IRQTYPE_EDGE, }, /* USBH */
|
|
{ .type = S3C_IRQTYPE_EDGE, }, /* IIC */
|
|
{ .type = S3C_IRQTYPE_LEVEL, }, /* UART0 */
|
|
{ .type = S3C_IRQTYPE_EDGE, }, /* SPI1 */
|
|
{ .type = S3C_IRQTYPE_EDGE, }, /* RTC */
|
|
{ .type = S3C_IRQTYPE_LEVEL, }, /* ADCPARENT */
|
|
};
|
|
|
|
static struct s3c_irq_data init_s3c2412eint[32] = {
|
|
{ .type = S3C_IRQTYPE_EINT, .parent_irq = 0 }, /* EINT0 */
|
|
{ .type = S3C_IRQTYPE_EINT, .parent_irq = 1 }, /* EINT1 */
|
|
{ .type = S3C_IRQTYPE_EINT, .parent_irq = 2 }, /* EINT2 */
|
|
{ .type = S3C_IRQTYPE_EINT, .parent_irq = 3 }, /* EINT3 */
|
|
{ .type = S3C_IRQTYPE_EINT, .parent_irq = 4 }, /* EINT4 */
|
|
{ .type = S3C_IRQTYPE_EINT, .parent_irq = 4 }, /* EINT5 */
|
|
{ .type = S3C_IRQTYPE_EINT, .parent_irq = 4 }, /* EINT6 */
|
|
{ .type = S3C_IRQTYPE_EINT, .parent_irq = 4 }, /* EINT7 */
|
|
{ .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT8 */
|
|
{ .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT9 */
|
|
{ .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT10 */
|
|
{ .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT11 */
|
|
{ .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT12 */
|
|
{ .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT13 */
|
|
{ .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT14 */
|
|
{ .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT15 */
|
|
{ .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT16 */
|
|
{ .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT17 */
|
|
{ .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT18 */
|
|
{ .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT19 */
|
|
{ .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT20 */
|
|
{ .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT21 */
|
|
{ .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT22 */
|
|
{ .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT23 */
|
|
};
|
|
|
|
static struct s3c_irq_data init_s3c2412subint[32] = {
|
|
{ .type = S3C_IRQTYPE_LEVEL, .parent_irq = 28 }, /* UART0-RX */
|
|
{ .type = S3C_IRQTYPE_LEVEL, .parent_irq = 28 }, /* UART0-TX */
|
|
{ .type = S3C_IRQTYPE_LEVEL, .parent_irq = 28 }, /* UART0-ERR */
|
|
{ .type = S3C_IRQTYPE_LEVEL, .parent_irq = 23 }, /* UART1-RX */
|
|
{ .type = S3C_IRQTYPE_LEVEL, .parent_irq = 23 }, /* UART1-TX */
|
|
{ .type = S3C_IRQTYPE_LEVEL, .parent_irq = 23 }, /* UART1-ERR */
|
|
{ .type = S3C_IRQTYPE_LEVEL, .parent_irq = 15 }, /* UART2-RX */
|
|
{ .type = S3C_IRQTYPE_LEVEL, .parent_irq = 15 }, /* UART2-TX */
|
|
{ .type = S3C_IRQTYPE_LEVEL, .parent_irq = 15 }, /* UART2-ERR */
|
|
{ .type = S3C_IRQTYPE_EDGE, .parent_irq = 31 }, /* TC */
|
|
{ .type = S3C_IRQTYPE_EDGE, .parent_irq = 31 }, /* ADC */
|
|
{ .type = S3C_IRQTYPE_NONE, },
|
|
{ .type = S3C_IRQTYPE_NONE, },
|
|
{ .type = S3C_IRQTYPE_LEVEL, .parent_irq = 21 }, /* SDI */
|
|
{ .type = S3C_IRQTYPE_LEVEL, .parent_irq = 21 }, /* CF */
|
|
};
|
|
|
|
void __init s3c2412_init_irq(void)
|
|
{
|
|
pr_info("S3C2412: IRQ Support\n");
|
|
|
|
#ifdef CONFIG_FIQ
|
|
init_FIQ(FIQ_START);
|
|
#endif
|
|
|
|
s3c_intc[0] = s3c24xx_init_intc(NULL, &init_s3c2412base[0], NULL,
|
|
0x4a000000);
|
|
if (IS_ERR(s3c_intc[0])) {
|
|
pr_err("irq: could not create main interrupt controller\n");
|
|
return;
|
|
}
|
|
|
|
s3c24xx_init_intc(NULL, &init_s3c2412eint[0], s3c_intc[0], 0x560000a4);
|
|
s3c_intc[1] = s3c24xx_init_intc(NULL, &init_s3c2412subint[0],
|
|
s3c_intc[0], 0x4a000018);
|
|
}
|
|
#endif
|
|
|
|
#ifdef CONFIG_CPU_S3C2416
|
|
static struct s3c_irq_data init_s3c2416base[32] = {
|
|
{ .type = S3C_IRQTYPE_EINT, }, /* EINT0 */
|
|
{ .type = S3C_IRQTYPE_EINT, }, /* EINT1 */
|
|
{ .type = S3C_IRQTYPE_EINT, }, /* EINT2 */
|
|
{ .type = S3C_IRQTYPE_EINT, }, /* EINT3 */
|
|
{ .type = S3C_IRQTYPE_LEVEL, }, /* EINT4to7 */
|
|
{ .type = S3C_IRQTYPE_LEVEL, }, /* EINT8to23 */
|
|
{ .type = S3C_IRQTYPE_NONE, }, /* reserved */
|
|
{ .type = S3C_IRQTYPE_EDGE, }, /* nBATT_FLT */
|
|
{ .type = S3C_IRQTYPE_EDGE, }, /* TICK */
|
|
{ .type = S3C_IRQTYPE_LEVEL, }, /* WDT/AC97 */
|
|
{ .type = S3C_IRQTYPE_EDGE, }, /* TIMER0 */
|
|
{ .type = S3C_IRQTYPE_EDGE, }, /* TIMER1 */
|
|
{ .type = S3C_IRQTYPE_EDGE, }, /* TIMER2 */
|
|
{ .type = S3C_IRQTYPE_EDGE, }, /* TIMER3 */
|
|
{ .type = S3C_IRQTYPE_EDGE, }, /* TIMER4 */
|
|
{ .type = S3C_IRQTYPE_LEVEL, }, /* UART2 */
|
|
{ .type = S3C_IRQTYPE_LEVEL, }, /* LCD */
|
|
{ .type = S3C_IRQTYPE_LEVEL, }, /* DMA */
|
|
{ .type = S3C_IRQTYPE_LEVEL, }, /* UART3 */
|
|
{ .type = S3C_IRQTYPE_NONE, }, /* reserved */
|
|
{ .type = S3C_IRQTYPE_EDGE, }, /* SDI1 */
|
|
{ .type = S3C_IRQTYPE_EDGE, }, /* SDI0 */
|
|
{ .type = S3C_IRQTYPE_EDGE, }, /* SPI0 */
|
|
{ .type = S3C_IRQTYPE_LEVEL, }, /* UART1 */
|
|
{ .type = S3C_IRQTYPE_EDGE, }, /* NAND */
|
|
{ .type = S3C_IRQTYPE_EDGE, }, /* USBD */
|
|
{ .type = S3C_IRQTYPE_EDGE, }, /* USBH */
|
|
{ .type = S3C_IRQTYPE_EDGE, }, /* IIC */
|
|
{ .type = S3C_IRQTYPE_LEVEL, }, /* UART0 */
|
|
{ .type = S3C_IRQTYPE_NONE, },
|
|
{ .type = S3C_IRQTYPE_EDGE, }, /* RTC */
|
|
{ .type = S3C_IRQTYPE_LEVEL, }, /* ADCPARENT */
|
|
};
|
|
|
|
static struct s3c_irq_data init_s3c2416subint[32] = {
|
|
{ .type = S3C_IRQTYPE_LEVEL, .parent_irq = 28 }, /* UART0-RX */
|
|
{ .type = S3C_IRQTYPE_LEVEL, .parent_irq = 28 }, /* UART0-TX */
|
|
{ .type = S3C_IRQTYPE_LEVEL, .parent_irq = 28 }, /* UART0-ERR */
|
|
{ .type = S3C_IRQTYPE_LEVEL, .parent_irq = 23 }, /* UART1-RX */
|
|
{ .type = S3C_IRQTYPE_LEVEL, .parent_irq = 23 }, /* UART1-TX */
|
|
{ .type = S3C_IRQTYPE_LEVEL, .parent_irq = 23 }, /* UART1-ERR */
|
|
{ .type = S3C_IRQTYPE_LEVEL, .parent_irq = 15 }, /* UART2-RX */
|
|
{ .type = S3C_IRQTYPE_LEVEL, .parent_irq = 15 }, /* UART2-TX */
|
|
{ .type = S3C_IRQTYPE_LEVEL, .parent_irq = 15 }, /* UART2-ERR */
|
|
{ .type = S3C_IRQTYPE_EDGE, .parent_irq = 31 }, /* TC */
|
|
{ .type = S3C_IRQTYPE_EDGE, .parent_irq = 31 }, /* ADC */
|
|
{ .type = S3C_IRQTYPE_NONE }, /* reserved */
|
|
{ .type = S3C_IRQTYPE_NONE }, /* reserved */
|
|
{ .type = S3C_IRQTYPE_NONE }, /* reserved */
|
|
{ .type = S3C_IRQTYPE_NONE }, /* reserved */
|
|
{ .type = S3C_IRQTYPE_LEVEL, .parent_irq = 16 }, /* LCD2 */
|
|
{ .type = S3C_IRQTYPE_LEVEL, .parent_irq = 16 }, /* LCD3 */
|
|
{ .type = S3C_IRQTYPE_LEVEL, .parent_irq = 16 }, /* LCD4 */
|
|
{ .type = S3C_IRQTYPE_LEVEL, .parent_irq = 17 }, /* DMA0 */
|
|
{ .type = S3C_IRQTYPE_LEVEL, .parent_irq = 17 }, /* DMA1 */
|
|
{ .type = S3C_IRQTYPE_LEVEL, .parent_irq = 17 }, /* DMA2 */
|
|
{ .type = S3C_IRQTYPE_LEVEL, .parent_irq = 17 }, /* DMA3 */
|
|
{ .type = S3C_IRQTYPE_LEVEL, .parent_irq = 17 }, /* DMA4 */
|
|
{ .type = S3C_IRQTYPE_LEVEL, .parent_irq = 17 }, /* DMA5 */
|
|
{ .type = S3C_IRQTYPE_LEVEL, .parent_irq = 18 }, /* UART3-RX */
|
|
{ .type = S3C_IRQTYPE_LEVEL, .parent_irq = 18 }, /* UART3-TX */
|
|
{ .type = S3C_IRQTYPE_LEVEL, .parent_irq = 18 }, /* UART3-ERR */
|
|
{ .type = S3C_IRQTYPE_LEVEL, .parent_irq = 9 }, /* WDT */
|
|
{ .type = S3C_IRQTYPE_LEVEL, .parent_irq = 9 }, /* AC97 */
|
|
};
|
|
|
|
static struct s3c_irq_data init_s3c2416_second[32] = {
|
|
{ .type = S3C_IRQTYPE_EDGE }, /* 2D */
|
|
{ .type = S3C_IRQTYPE_NONE }, /* reserved */
|
|
{ .type = S3C_IRQTYPE_NONE }, /* reserved */
|
|
{ .type = S3C_IRQTYPE_NONE }, /* reserved */
|
|
{ .type = S3C_IRQTYPE_EDGE }, /* PCM0 */
|
|
{ .type = S3C_IRQTYPE_NONE }, /* reserved */
|
|
{ .type = S3C_IRQTYPE_EDGE }, /* I2S0 */
|
|
};
|
|
|
|
void __init s3c2416_init_irq(void)
|
|
{
|
|
pr_info("S3C2416: IRQ Support\n");
|
|
|
|
#ifdef CONFIG_FIQ
|
|
init_FIQ(FIQ_START);
|
|
#endif
|
|
|
|
s3c_intc[0] = s3c24xx_init_intc(NULL, &init_s3c2416base[0], NULL,
|
|
0x4a000000);
|
|
if (IS_ERR(s3c_intc[0])) {
|
|
pr_err("irq: could not create main interrupt controller\n");
|
|
return;
|
|
}
|
|
|
|
s3c24xx_init_intc(NULL, &init_eint[0], s3c_intc[0], 0x560000a4);
|
|
s3c_intc[1] = s3c24xx_init_intc(NULL, &init_s3c2416subint[0],
|
|
s3c_intc[0], 0x4a000018);
|
|
|
|
s3c_intc[2] = s3c24xx_init_intc(NULL, &init_s3c2416_second[0],
|
|
NULL, 0x4a000040);
|
|
}
|
|
|
|
#endif
|
|
|
|
#ifdef CONFIG_CPU_S3C2440
|
|
static struct s3c_irq_data init_s3c2440base[32] = {
|
|
{ .type = S3C_IRQTYPE_EINT, }, /* EINT0 */
|
|
{ .type = S3C_IRQTYPE_EINT, }, /* EINT1 */
|
|
{ .type = S3C_IRQTYPE_EINT, }, /* EINT2 */
|
|
{ .type = S3C_IRQTYPE_EINT, }, /* EINT3 */
|
|
{ .type = S3C_IRQTYPE_LEVEL, }, /* EINT4to7 */
|
|
{ .type = S3C_IRQTYPE_LEVEL, }, /* EINT8to23 */
|
|
{ .type = S3C_IRQTYPE_LEVEL, }, /* CAM */
|
|
{ .type = S3C_IRQTYPE_EDGE, }, /* nBATT_FLT */
|
|
{ .type = S3C_IRQTYPE_EDGE, }, /* TICK */
|
|
{ .type = S3C_IRQTYPE_LEVEL, }, /* WDT/AC97 */
|
|
{ .type = S3C_IRQTYPE_EDGE, }, /* TIMER0 */
|
|
{ .type = S3C_IRQTYPE_EDGE, }, /* TIMER1 */
|
|
{ .type = S3C_IRQTYPE_EDGE, }, /* TIMER2 */
|
|
{ .type = S3C_IRQTYPE_EDGE, }, /* TIMER3 */
|
|
{ .type = S3C_IRQTYPE_EDGE, }, /* TIMER4 */
|
|
{ .type = S3C_IRQTYPE_LEVEL, }, /* UART2 */
|
|
{ .type = S3C_IRQTYPE_EDGE, }, /* LCD */
|
|
{ .type = S3C_IRQTYPE_EDGE, }, /* DMA0 */
|
|
{ .type = S3C_IRQTYPE_EDGE, }, /* DMA1 */
|
|
{ .type = S3C_IRQTYPE_EDGE, }, /* DMA2 */
|
|
{ .type = S3C_IRQTYPE_EDGE, }, /* DMA3 */
|
|
{ .type = S3C_IRQTYPE_EDGE, }, /* SDI */
|
|
{ .type = S3C_IRQTYPE_EDGE, }, /* SPI0 */
|
|
{ .type = S3C_IRQTYPE_LEVEL, }, /* UART1 */
|
|
{ .type = S3C_IRQTYPE_LEVEL, }, /* NFCON */
|
|
{ .type = S3C_IRQTYPE_EDGE, }, /* USBD */
|
|
{ .type = S3C_IRQTYPE_EDGE, }, /* USBH */
|
|
{ .type = S3C_IRQTYPE_EDGE, }, /* IIC */
|
|
{ .type = S3C_IRQTYPE_LEVEL, }, /* UART0 */
|
|
{ .type = S3C_IRQTYPE_EDGE, }, /* SPI1 */
|
|
{ .type = S3C_IRQTYPE_EDGE, }, /* RTC */
|
|
{ .type = S3C_IRQTYPE_LEVEL, }, /* ADCPARENT */
|
|
};
|
|
|
|
static struct s3c_irq_data init_s3c2440subint[32] = {
|
|
{ .type = S3C_IRQTYPE_LEVEL, .parent_irq = 28 }, /* UART0-RX */
|
|
{ .type = S3C_IRQTYPE_LEVEL, .parent_irq = 28 }, /* UART0-TX */
|
|
{ .type = S3C_IRQTYPE_LEVEL, .parent_irq = 28 }, /* UART0-ERR */
|
|
{ .type = S3C_IRQTYPE_LEVEL, .parent_irq = 23 }, /* UART1-RX */
|
|
{ .type = S3C_IRQTYPE_LEVEL, .parent_irq = 23 }, /* UART1-TX */
|
|
{ .type = S3C_IRQTYPE_LEVEL, .parent_irq = 23 }, /* UART1-ERR */
|
|
{ .type = S3C_IRQTYPE_LEVEL, .parent_irq = 15 }, /* UART2-RX */
|
|
{ .type = S3C_IRQTYPE_LEVEL, .parent_irq = 15 }, /* UART2-TX */
|
|
{ .type = S3C_IRQTYPE_LEVEL, .parent_irq = 15 }, /* UART2-ERR */
|
|
{ .type = S3C_IRQTYPE_EDGE, .parent_irq = 31 }, /* TC */
|
|
{ .type = S3C_IRQTYPE_EDGE, .parent_irq = 31 }, /* ADC */
|
|
{ .type = S3C_IRQTYPE_LEVEL, .parent_irq = 6 }, /* CAM_C */
|
|
{ .type = S3C_IRQTYPE_LEVEL, .parent_irq = 6 }, /* CAM_P */
|
|
{ .type = S3C_IRQTYPE_LEVEL, .parent_irq = 9 }, /* WDT */
|
|
{ .type = S3C_IRQTYPE_LEVEL, .parent_irq = 9 }, /* AC97 */
|
|
};
|
|
|
|
void __init s3c2440_init_irq(void)
|
|
{
|
|
pr_info("S3C2440: IRQ Support\n");
|
|
|
|
#ifdef CONFIG_FIQ
|
|
init_FIQ(FIQ_START);
|
|
#endif
|
|
|
|
s3c_intc[0] = s3c24xx_init_intc(NULL, &init_s3c2440base[0], NULL,
|
|
0x4a000000);
|
|
if (IS_ERR(s3c_intc[0])) {
|
|
pr_err("irq: could not create main interrupt controller\n");
|
|
return;
|
|
}
|
|
|
|
s3c24xx_init_intc(NULL, &init_eint[0], s3c_intc[0], 0x560000a4);
|
|
s3c_intc[1] = s3c24xx_init_intc(NULL, &init_s3c2440subint[0],
|
|
s3c_intc[0], 0x4a000018);
|
|
}
|
|
#endif
|
|
|
|
#ifdef CONFIG_CPU_S3C2442
|
|
static struct s3c_irq_data init_s3c2442base[32] = {
|
|
{ .type = S3C_IRQTYPE_EINT, }, /* EINT0 */
|
|
{ .type = S3C_IRQTYPE_EINT, }, /* EINT1 */
|
|
{ .type = S3C_IRQTYPE_EINT, }, /* EINT2 */
|
|
{ .type = S3C_IRQTYPE_EINT, }, /* EINT3 */
|
|
{ .type = S3C_IRQTYPE_LEVEL, }, /* EINT4to7 */
|
|
{ .type = S3C_IRQTYPE_LEVEL, }, /* EINT8to23 */
|
|
{ .type = S3C_IRQTYPE_LEVEL, }, /* CAM */
|
|
{ .type = S3C_IRQTYPE_EDGE, }, /* nBATT_FLT */
|
|
{ .type = S3C_IRQTYPE_EDGE, }, /* TICK */
|
|
{ .type = S3C_IRQTYPE_EDGE, }, /* WDT */
|
|
{ .type = S3C_IRQTYPE_EDGE, }, /* TIMER0 */
|
|
{ .type = S3C_IRQTYPE_EDGE, }, /* TIMER1 */
|
|
{ .type = S3C_IRQTYPE_EDGE, }, /* TIMER2 */
|
|
{ .type = S3C_IRQTYPE_EDGE, }, /* TIMER3 */
|
|
{ .type = S3C_IRQTYPE_EDGE, }, /* TIMER4 */
|
|
{ .type = S3C_IRQTYPE_LEVEL, }, /* UART2 */
|
|
{ .type = S3C_IRQTYPE_EDGE, }, /* LCD */
|
|
{ .type = S3C_IRQTYPE_EDGE, }, /* DMA0 */
|
|
{ .type = S3C_IRQTYPE_EDGE, }, /* DMA1 */
|
|
{ .type = S3C_IRQTYPE_EDGE, }, /* DMA2 */
|
|
{ .type = S3C_IRQTYPE_EDGE, }, /* DMA3 */
|
|
{ .type = S3C_IRQTYPE_EDGE, }, /* SDI */
|
|
{ .type = S3C_IRQTYPE_EDGE, }, /* SPI0 */
|
|
{ .type = S3C_IRQTYPE_LEVEL, }, /* UART1 */
|
|
{ .type = S3C_IRQTYPE_LEVEL, }, /* NFCON */
|
|
{ .type = S3C_IRQTYPE_EDGE, }, /* USBD */
|
|
{ .type = S3C_IRQTYPE_EDGE, }, /* USBH */
|
|
{ .type = S3C_IRQTYPE_EDGE, }, /* IIC */
|
|
{ .type = S3C_IRQTYPE_LEVEL, }, /* UART0 */
|
|
{ .type = S3C_IRQTYPE_EDGE, }, /* SPI1 */
|
|
{ .type = S3C_IRQTYPE_EDGE, }, /* RTC */
|
|
{ .type = S3C_IRQTYPE_LEVEL, }, /* ADCPARENT */
|
|
};
|
|
|
|
static struct s3c_irq_data init_s3c2442subint[32] = {
|
|
{ .type = S3C_IRQTYPE_LEVEL, .parent_irq = 28 }, /* UART0-RX */
|
|
{ .type = S3C_IRQTYPE_LEVEL, .parent_irq = 28 }, /* UART0-TX */
|
|
{ .type = S3C_IRQTYPE_LEVEL, .parent_irq = 28 }, /* UART0-ERR */
|
|
{ .type = S3C_IRQTYPE_LEVEL, .parent_irq = 23 }, /* UART1-RX */
|
|
{ .type = S3C_IRQTYPE_LEVEL, .parent_irq = 23 }, /* UART1-TX */
|
|
{ .type = S3C_IRQTYPE_LEVEL, .parent_irq = 23 }, /* UART1-ERR */
|
|
{ .type = S3C_IRQTYPE_LEVEL, .parent_irq = 15 }, /* UART2-RX */
|
|
{ .type = S3C_IRQTYPE_LEVEL, .parent_irq = 15 }, /* UART2-TX */
|
|
{ .type = S3C_IRQTYPE_LEVEL, .parent_irq = 15 }, /* UART2-ERR */
|
|
{ .type = S3C_IRQTYPE_EDGE, .parent_irq = 31 }, /* TC */
|
|
{ .type = S3C_IRQTYPE_EDGE, .parent_irq = 31 }, /* ADC */
|
|
{ .type = S3C_IRQTYPE_LEVEL, .parent_irq = 6 }, /* CAM_C */
|
|
{ .type = S3C_IRQTYPE_LEVEL, .parent_irq = 6 }, /* CAM_P */
|
|
};
|
|
|
|
void __init s3c2442_init_irq(void)
|
|
{
|
|
pr_info("S3C2442: IRQ Support\n");
|
|
|
|
#ifdef CONFIG_FIQ
|
|
init_FIQ(FIQ_START);
|
|
#endif
|
|
|
|
s3c_intc[0] = s3c24xx_init_intc(NULL, &init_s3c2442base[0], NULL,
|
|
0x4a000000);
|
|
if (IS_ERR(s3c_intc[0])) {
|
|
pr_err("irq: could not create main interrupt controller\n");
|
|
return;
|
|
}
|
|
|
|
s3c24xx_init_intc(NULL, &init_eint[0], s3c_intc[0], 0x560000a4);
|
|
s3c_intc[1] = s3c24xx_init_intc(NULL, &init_s3c2442subint[0],
|
|
s3c_intc[0], 0x4a000018);
|
|
}
|
|
#endif
|
|
|
|
#ifdef CONFIG_CPU_S3C2443
|
|
static struct s3c_irq_data init_s3c2443base[32] = {
|
|
{ .type = S3C_IRQTYPE_EINT, }, /* EINT0 */
|
|
{ .type = S3C_IRQTYPE_EINT, }, /* EINT1 */
|
|
{ .type = S3C_IRQTYPE_EINT, }, /* EINT2 */
|
|
{ .type = S3C_IRQTYPE_EINT, }, /* EINT3 */
|
|
{ .type = S3C_IRQTYPE_LEVEL, }, /* EINT4to7 */
|
|
{ .type = S3C_IRQTYPE_LEVEL, }, /* EINT8to23 */
|
|
{ .type = S3C_IRQTYPE_LEVEL, }, /* CAM */
|
|
{ .type = S3C_IRQTYPE_EDGE, }, /* nBATT_FLT */
|
|
{ .type = S3C_IRQTYPE_EDGE, }, /* TICK */
|
|
{ .type = S3C_IRQTYPE_LEVEL, }, /* WDT/AC97 */
|
|
{ .type = S3C_IRQTYPE_EDGE, }, /* TIMER0 */
|
|
{ .type = S3C_IRQTYPE_EDGE, }, /* TIMER1 */
|
|
{ .type = S3C_IRQTYPE_EDGE, }, /* TIMER2 */
|
|
{ .type = S3C_IRQTYPE_EDGE, }, /* TIMER3 */
|
|
{ .type = S3C_IRQTYPE_EDGE, }, /* TIMER4 */
|
|
{ .type = S3C_IRQTYPE_LEVEL, }, /* UART2 */
|
|
{ .type = S3C_IRQTYPE_LEVEL, }, /* LCD */
|
|
{ .type = S3C_IRQTYPE_LEVEL, }, /* DMA */
|
|
{ .type = S3C_IRQTYPE_LEVEL, }, /* UART3 */
|
|
{ .type = S3C_IRQTYPE_EDGE, }, /* CFON */
|
|
{ .type = S3C_IRQTYPE_EDGE, }, /* SDI1 */
|
|
{ .type = S3C_IRQTYPE_EDGE, }, /* SDI0 */
|
|
{ .type = S3C_IRQTYPE_EDGE, }, /* SPI0 */
|
|
{ .type = S3C_IRQTYPE_LEVEL, }, /* UART1 */
|
|
{ .type = S3C_IRQTYPE_EDGE, }, /* NAND */
|
|
{ .type = S3C_IRQTYPE_EDGE, }, /* USBD */
|
|
{ .type = S3C_IRQTYPE_EDGE, }, /* USBH */
|
|
{ .type = S3C_IRQTYPE_EDGE, }, /* IIC */
|
|
{ .type = S3C_IRQTYPE_LEVEL, }, /* UART0 */
|
|
{ .type = S3C_IRQTYPE_EDGE, }, /* SPI1 */
|
|
{ .type = S3C_IRQTYPE_EDGE, }, /* RTC */
|
|
{ .type = S3C_IRQTYPE_LEVEL, }, /* ADCPARENT */
|
|
};
|
|
|
|
|
|
static struct s3c_irq_data init_s3c2443subint[32] = {
|
|
{ .type = S3C_IRQTYPE_LEVEL, .parent_irq = 28 }, /* UART0-RX */
|
|
{ .type = S3C_IRQTYPE_LEVEL, .parent_irq = 28 }, /* UART0-TX */
|
|
{ .type = S3C_IRQTYPE_LEVEL, .parent_irq = 28 }, /* UART0-ERR */
|
|
{ .type = S3C_IRQTYPE_LEVEL, .parent_irq = 23 }, /* UART1-RX */
|
|
{ .type = S3C_IRQTYPE_LEVEL, .parent_irq = 23 }, /* UART1-TX */
|
|
{ .type = S3C_IRQTYPE_LEVEL, .parent_irq = 23 }, /* UART1-ERR */
|
|
{ .type = S3C_IRQTYPE_LEVEL, .parent_irq = 15 }, /* UART2-RX */
|
|
{ .type = S3C_IRQTYPE_LEVEL, .parent_irq = 15 }, /* UART2-TX */
|
|
{ .type = S3C_IRQTYPE_LEVEL, .parent_irq = 15 }, /* UART2-ERR */
|
|
{ .type = S3C_IRQTYPE_EDGE, .parent_irq = 31 }, /* TC */
|
|
{ .type = S3C_IRQTYPE_EDGE, .parent_irq = 31 }, /* ADC */
|
|
{ .type = S3C_IRQTYPE_LEVEL, .parent_irq = 6 }, /* CAM_C */
|
|
{ .type = S3C_IRQTYPE_LEVEL, .parent_irq = 6 }, /* CAM_P */
|
|
{ .type = S3C_IRQTYPE_NONE }, /* reserved */
|
|
{ .type = S3C_IRQTYPE_LEVEL, .parent_irq = 16 }, /* LCD1 */
|
|
{ .type = S3C_IRQTYPE_LEVEL, .parent_irq = 16 }, /* LCD2 */
|
|
{ .type = S3C_IRQTYPE_LEVEL, .parent_irq = 16 }, /* LCD3 */
|
|
{ .type = S3C_IRQTYPE_LEVEL, .parent_irq = 16 }, /* LCD4 */
|
|
{ .type = S3C_IRQTYPE_LEVEL, .parent_irq = 17 }, /* DMA0 */
|
|
{ .type = S3C_IRQTYPE_LEVEL, .parent_irq = 17 }, /* DMA1 */
|
|
{ .type = S3C_IRQTYPE_LEVEL, .parent_irq = 17 }, /* DMA2 */
|
|
{ .type = S3C_IRQTYPE_LEVEL, .parent_irq = 17 }, /* DMA3 */
|
|
{ .type = S3C_IRQTYPE_LEVEL, .parent_irq = 17 }, /* DMA4 */
|
|
{ .type = S3C_IRQTYPE_LEVEL, .parent_irq = 17 }, /* DMA5 */
|
|
{ .type = S3C_IRQTYPE_LEVEL, .parent_irq = 18 }, /* UART3-RX */
|
|
{ .type = S3C_IRQTYPE_LEVEL, .parent_irq = 18 }, /* UART3-TX */
|
|
{ .type = S3C_IRQTYPE_LEVEL, .parent_irq = 18 }, /* UART3-ERR */
|
|
{ .type = S3C_IRQTYPE_LEVEL, .parent_irq = 9 }, /* WDT */
|
|
{ .type = S3C_IRQTYPE_LEVEL, .parent_irq = 9 }, /* AC97 */
|
|
};
|
|
|
|
void __init s3c2443_init_irq(void)
|
|
{
|
|
pr_info("S3C2443: IRQ Support\n");
|
|
|
|
#ifdef CONFIG_FIQ
|
|
init_FIQ(FIQ_START);
|
|
#endif
|
|
|
|
s3c_intc[0] = s3c24xx_init_intc(NULL, &init_s3c2443base[0], NULL,
|
|
0x4a000000);
|
|
if (IS_ERR(s3c_intc[0])) {
|
|
pr_err("irq: could not create main interrupt controller\n");
|
|
return;
|
|
}
|
|
|
|
s3c24xx_init_intc(NULL, &init_eint[0], s3c_intc[0], 0x560000a4);
|
|
s3c_intc[1] = s3c24xx_init_intc(NULL, &init_s3c2443subint[0],
|
|
s3c_intc[0], 0x4a000018);
|
|
}
|
|
#endif
|
|
|
|
#ifdef CONFIG_OF
|
|
static int s3c24xx_irq_map_of(struct irq_domain *h, unsigned int virq,
|
|
irq_hw_number_t hw)
|
|
{
|
|
unsigned int ctrl_num = hw / 32;
|
|
unsigned int intc_hw = hw % 32;
|
|
struct s3c_irq_intc *intc = s3c_intc[ctrl_num];
|
|
struct s3c_irq_intc *parent_intc = intc->parent;
|
|
struct s3c_irq_data *irq_data = &intc->irqs[intc_hw];
|
|
|
|
/* attach controller pointer to irq_data */
|
|
irq_data->intc = intc;
|
|
irq_data->offset = intc_hw;
|
|
|
|
if (!parent_intc)
|
|
irq_set_chip_and_handler(virq, &s3c_irq_chip, handle_edge_irq);
|
|
else
|
|
irq_set_chip_and_handler(virq, &s3c_irq_level_chip,
|
|
handle_edge_irq);
|
|
|
|
irq_set_chip_data(virq, irq_data);
|
|
|
|
return 0;
|
|
}
|
|
|
|
/* Translate our of irq notation
|
|
* format: <ctrl_num ctrl_irq parent_irq type>
|
|
*/
|
|
static int s3c24xx_irq_xlate_of(struct irq_domain *d, struct device_node *n,
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const u32 *intspec, unsigned int intsize,
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irq_hw_number_t *out_hwirq, unsigned int *out_type)
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{
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struct s3c_irq_intc *intc;
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struct s3c_irq_intc *parent_intc;
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struct s3c_irq_data *irq_data;
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struct s3c_irq_data *parent_irq_data;
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int irqno;
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if (WARN_ON(intsize < 4))
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return -EINVAL;
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if (intspec[0] > 2 || !s3c_intc[intspec[0]]) {
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pr_err("controller number %d invalid\n", intspec[0]);
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return -EINVAL;
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}
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intc = s3c_intc[intspec[0]];
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*out_hwirq = intspec[0] * 32 + intspec[2];
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*out_type = intspec[3] & IRQ_TYPE_SENSE_MASK;
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parent_intc = intc->parent;
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if (parent_intc) {
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irq_data = &intc->irqs[intspec[2]];
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irq_data->parent_irq = intspec[1];
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parent_irq_data = &parent_intc->irqs[irq_data->parent_irq];
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parent_irq_data->sub_intc = intc;
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parent_irq_data->sub_bits |= (1UL << intspec[2]);
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/* parent_intc is always s3c_intc[0], so no offset */
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irqno = irq_create_mapping(parent_intc->domain, intspec[1]);
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if (irqno < 0) {
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pr_err("irq: could not map parent interrupt\n");
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return irqno;
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}
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irq_set_chained_handler(irqno, s3c_irq_demux);
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}
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return 0;
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}
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static const struct irq_domain_ops s3c24xx_irq_ops_of = {
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.map = s3c24xx_irq_map_of,
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.xlate = s3c24xx_irq_xlate_of,
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};
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struct s3c24xx_irq_of_ctrl {
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char *name;
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unsigned long offset;
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struct s3c_irq_intc **handle;
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struct s3c_irq_intc **parent;
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struct irq_domain_ops *ops;
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};
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static int __init s3c_init_intc_of(struct device_node *np,
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struct device_node *interrupt_parent,
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struct s3c24xx_irq_of_ctrl *s3c_ctrl, int num_ctrl)
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{
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struct s3c_irq_intc *intc;
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struct s3c24xx_irq_of_ctrl *ctrl;
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struct irq_domain *domain;
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void __iomem *reg_base;
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int i;
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reg_base = of_iomap(np, 0);
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if (!reg_base) {
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pr_err("irq-s3c24xx: could not map irq registers\n");
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return -EINVAL;
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}
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domain = irq_domain_add_linear(np, num_ctrl * 32,
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&s3c24xx_irq_ops_of, NULL);
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if (!domain) {
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pr_err("irq: could not create irq-domain\n");
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return -EINVAL;
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}
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for (i = 0; i < num_ctrl; i++) {
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ctrl = &s3c_ctrl[i];
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pr_debug("irq: found controller %s\n", ctrl->name);
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intc = kzalloc(sizeof(struct s3c_irq_intc), GFP_KERNEL);
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if (!intc)
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return -ENOMEM;
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|
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intc->domain = domain;
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intc->irqs = kzalloc(sizeof(struct s3c_irq_data) * 32,
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GFP_KERNEL);
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if (!intc->irqs) {
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kfree(intc);
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return -ENOMEM;
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}
|
|
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if (ctrl->parent) {
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intc->reg_pending = reg_base + ctrl->offset;
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intc->reg_mask = reg_base + ctrl->offset + 0x4;
|
|
|
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if (*(ctrl->parent)) {
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intc->parent = *(ctrl->parent);
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} else {
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pr_warn("irq: parent of %s missing\n",
|
|
ctrl->name);
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kfree(intc->irqs);
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kfree(intc);
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continue;
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}
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} else {
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intc->reg_pending = reg_base + ctrl->offset;
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intc->reg_mask = reg_base + ctrl->offset + 0x08;
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intc->reg_intpnd = reg_base + ctrl->offset + 0x10;
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}
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|
|
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s3c24xx_clear_intc(intc);
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s3c_intc[i] = intc;
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}
|
|
|
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set_handle_irq(s3c24xx_handle_irq);
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|
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return 0;
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}
|
|
|
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static struct s3c24xx_irq_of_ctrl s3c2410_ctrl[] = {
|
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{
|
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.name = "intc",
|
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.offset = 0,
|
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}, {
|
|
.name = "subintc",
|
|
.offset = 0x18,
|
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.parent = &s3c_intc[0],
|
|
}
|
|
};
|
|
|
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int __init s3c2410_init_intc_of(struct device_node *np,
|
|
struct device_node *interrupt_parent)
|
|
{
|
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return s3c_init_intc_of(np, interrupt_parent,
|
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s3c2410_ctrl, ARRAY_SIZE(s3c2410_ctrl));
|
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}
|
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IRQCHIP_DECLARE(s3c2410_irq, "samsung,s3c2410-irq", s3c2410_init_intc_of);
|
|
|
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static struct s3c24xx_irq_of_ctrl s3c2416_ctrl[] = {
|
|
{
|
|
.name = "intc",
|
|
.offset = 0,
|
|
}, {
|
|
.name = "subintc",
|
|
.offset = 0x18,
|
|
.parent = &s3c_intc[0],
|
|
}, {
|
|
.name = "intc2",
|
|
.offset = 0x40,
|
|
}
|
|
};
|
|
|
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int __init s3c2416_init_intc_of(struct device_node *np,
|
|
struct device_node *interrupt_parent)
|
|
{
|
|
return s3c_init_intc_of(np, interrupt_parent,
|
|
s3c2416_ctrl, ARRAY_SIZE(s3c2416_ctrl));
|
|
}
|
|
IRQCHIP_DECLARE(s3c2416_irq, "samsung,s3c2416-irq", s3c2416_init_intc_of);
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#endif
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