288 lines
7.7 KiB
C
288 lines
7.7 KiB
C
/*
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* sata_sis.c - Silicon Integrated Systems SATA
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*
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* Maintained by: Uwe Koziolek
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* Please ALWAYS copy linux-ide@vger.kernel.org
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* on emails.
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*
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* Copyright 2004 Uwe Koziolek
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*
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* The contents of this file are subject to the Open
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* Software License version 1.1 that can be found at
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* http://www.opensource.org/licenses/osl-1.1.txt and is included herein
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* by reference.
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*
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* Alternatively, the contents of this file may be used under the terms
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* of the GNU General Public License version 2 (the "GPL") as distributed
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* in the kernel source COPYING file, in which case the provisions of
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* the GPL are applicable instead of the above. If you wish to allow
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* the use of your version of this file only under the terms of the
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* GPL and not to allow others to use your version of this file under
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* the OSL, indicate your decision by deleting the provisions above and
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* replace them with the notice and other provisions required by the GPL.
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* If you do not delete the provisions above, a recipient may use your
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* version of this file under either the OSL or the GPL.
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*
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*/
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#include <linux/config.h>
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/pci.h>
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#include <linux/init.h>
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#include <linux/blkdev.h>
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#include <linux/delay.h>
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#include <linux/interrupt.h>
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#include "scsi.h"
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#include <scsi/scsi_host.h>
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#include <linux/libata.h>
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#define DRV_NAME "sata_sis"
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#define DRV_VERSION "0.5"
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enum {
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sis_180 = 0,
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SIS_SCR_PCI_BAR = 5,
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/* PCI configuration registers */
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SIS_GENCTL = 0x54, /* IDE General Control register */
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SIS_SCR_BASE = 0xc0, /* sata0 phy SCR registers */
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SIS_SATA1_OFS = 0x10, /* offset from sata0->sata1 phy regs */
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/* random bits */
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SIS_FLAG_CFGSCR = (1 << 30), /* host flag: SCRs via PCI cfg */
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GENCTL_IOMAPPED_SCR = (1 << 26), /* if set, SCRs are in IO space */
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};
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static int sis_init_one (struct pci_dev *pdev, const struct pci_device_id *ent);
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static u32 sis_scr_read (struct ata_port *ap, unsigned int sc_reg);
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static void sis_scr_write (struct ata_port *ap, unsigned int sc_reg, u32 val);
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static struct pci_device_id sis_pci_tbl[] = {
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{ PCI_VENDOR_ID_SI, 0x180, PCI_ANY_ID, PCI_ANY_ID, 0, 0, sis_180 },
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{ PCI_VENDOR_ID_SI, 0x181, PCI_ANY_ID, PCI_ANY_ID, 0, 0, sis_180 },
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{ } /* terminate list */
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};
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static struct pci_driver sis_pci_driver = {
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.name = DRV_NAME,
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.id_table = sis_pci_tbl,
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.probe = sis_init_one,
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.remove = ata_pci_remove_one,
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};
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static Scsi_Host_Template sis_sht = {
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.module = THIS_MODULE,
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.name = DRV_NAME,
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.ioctl = ata_scsi_ioctl,
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.queuecommand = ata_scsi_queuecmd,
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.eh_strategy_handler = ata_scsi_error,
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.can_queue = ATA_DEF_QUEUE,
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.this_id = ATA_SHT_THIS_ID,
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.sg_tablesize = ATA_MAX_PRD,
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.max_sectors = ATA_MAX_SECTORS,
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.cmd_per_lun = ATA_SHT_CMD_PER_LUN,
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.emulated = ATA_SHT_EMULATED,
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.use_clustering = ATA_SHT_USE_CLUSTERING,
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.proc_name = DRV_NAME,
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.dma_boundary = ATA_DMA_BOUNDARY,
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.slave_configure = ata_scsi_slave_config,
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.bios_param = ata_std_bios_param,
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.ordered_flush = 1,
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};
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static struct ata_port_operations sis_ops = {
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.port_disable = ata_port_disable,
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.tf_load = ata_tf_load,
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.tf_read = ata_tf_read,
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.check_status = ata_check_status,
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.exec_command = ata_exec_command,
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.dev_select = ata_std_dev_select,
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.phy_reset = sata_phy_reset,
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.bmdma_setup = ata_bmdma_setup,
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.bmdma_start = ata_bmdma_start,
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.bmdma_stop = ata_bmdma_stop,
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.bmdma_status = ata_bmdma_status,
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.qc_prep = ata_qc_prep,
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.qc_issue = ata_qc_issue_prot,
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.eng_timeout = ata_eng_timeout,
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.irq_handler = ata_interrupt,
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.irq_clear = ata_bmdma_irq_clear,
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.scr_read = sis_scr_read,
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.scr_write = sis_scr_write,
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.port_start = ata_port_start,
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.port_stop = ata_port_stop,
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.host_stop = ata_host_stop,
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};
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static struct ata_port_info sis_port_info = {
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.sht = &sis_sht,
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.host_flags = ATA_FLAG_SATA | ATA_FLAG_SATA_RESET |
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ATA_FLAG_NO_LEGACY,
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.pio_mask = 0x1f,
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.mwdma_mask = 0x7,
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.udma_mask = 0x7f,
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.port_ops = &sis_ops,
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};
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MODULE_AUTHOR("Uwe Koziolek");
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MODULE_DESCRIPTION("low-level driver for Silicon Integratad Systems SATA controller");
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MODULE_LICENSE("GPL");
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MODULE_DEVICE_TABLE(pci, sis_pci_tbl);
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MODULE_VERSION(DRV_VERSION);
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static unsigned int get_scr_cfg_addr(unsigned int port_no, unsigned int sc_reg)
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{
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unsigned int addr = SIS_SCR_BASE + (4 * sc_reg);
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if (port_no)
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addr += SIS_SATA1_OFS;
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return addr;
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}
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static u32 sis_scr_cfg_read (struct ata_port *ap, unsigned int sc_reg)
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{
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struct pci_dev *pdev = to_pci_dev(ap->host_set->dev);
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unsigned int cfg_addr = get_scr_cfg_addr(ap->port_no, sc_reg);
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u32 val;
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if (sc_reg == SCR_ERROR) /* doesn't exist in PCI cfg space */
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return 0xffffffff;
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pci_read_config_dword(pdev, cfg_addr, &val);
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return val;
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}
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static void sis_scr_cfg_write (struct ata_port *ap, unsigned int scr, u32 val)
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{
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struct pci_dev *pdev = to_pci_dev(ap->host_set->dev);
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unsigned int cfg_addr = get_scr_cfg_addr(ap->port_no, scr);
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if (scr == SCR_ERROR) /* doesn't exist in PCI cfg space */
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return;
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pci_write_config_dword(pdev, cfg_addr, val);
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}
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static u32 sis_scr_read (struct ata_port *ap, unsigned int sc_reg)
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{
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if (sc_reg > SCR_CONTROL)
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return 0xffffffffU;
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if (ap->flags & SIS_FLAG_CFGSCR)
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return sis_scr_cfg_read(ap, sc_reg);
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return inl(ap->ioaddr.scr_addr + (sc_reg * 4));
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}
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static void sis_scr_write (struct ata_port *ap, unsigned int sc_reg, u32 val)
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{
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if (sc_reg > SCR_CONTROL)
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return;
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if (ap->flags & SIS_FLAG_CFGSCR)
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sis_scr_cfg_write(ap, sc_reg, val);
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else
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outl(val, ap->ioaddr.scr_addr + (sc_reg * 4));
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}
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/* move to PCI layer, integrate w/ MSI stuff */
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static void pci_enable_intx(struct pci_dev *pdev)
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{
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u16 pci_command;
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pci_read_config_word(pdev, PCI_COMMAND, &pci_command);
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if (pci_command & PCI_COMMAND_INTX_DISABLE) {
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pci_command &= ~PCI_COMMAND_INTX_DISABLE;
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pci_write_config_word(pdev, PCI_COMMAND, pci_command);
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}
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}
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static int sis_init_one (struct pci_dev *pdev, const struct pci_device_id *ent)
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{
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struct ata_probe_ent *probe_ent = NULL;
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int rc;
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u32 genctl;
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struct ata_port_info *ppi;
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int pci_dev_busy = 0;
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rc = pci_enable_device(pdev);
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if (rc)
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return rc;
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rc = pci_request_regions(pdev, DRV_NAME);
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if (rc) {
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pci_dev_busy = 1;
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goto err_out;
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}
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rc = pci_set_dma_mask(pdev, ATA_DMA_MASK);
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if (rc)
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goto err_out_regions;
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rc = pci_set_consistent_dma_mask(pdev, ATA_DMA_MASK);
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if (rc)
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goto err_out_regions;
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ppi = &sis_port_info;
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probe_ent = ata_pci_init_native_mode(pdev, &ppi);
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if (!probe_ent) {
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rc = -ENOMEM;
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goto err_out_regions;
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}
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/* check and see if the SCRs are in IO space or PCI cfg space */
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pci_read_config_dword(pdev, SIS_GENCTL, &genctl);
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if ((genctl & GENCTL_IOMAPPED_SCR) == 0)
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probe_ent->host_flags |= SIS_FLAG_CFGSCR;
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/* if hardware thinks SCRs are in IO space, but there are
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* no IO resources assigned, change to PCI cfg space.
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*/
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if ((!(probe_ent->host_flags & SIS_FLAG_CFGSCR)) &&
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((pci_resource_start(pdev, SIS_SCR_PCI_BAR) == 0) ||
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(pci_resource_len(pdev, SIS_SCR_PCI_BAR) < 128))) {
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genctl &= ~GENCTL_IOMAPPED_SCR;
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pci_write_config_dword(pdev, SIS_GENCTL, genctl);
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probe_ent->host_flags |= SIS_FLAG_CFGSCR;
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}
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if (!(probe_ent->host_flags & SIS_FLAG_CFGSCR)) {
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probe_ent->port[0].scr_addr =
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pci_resource_start(pdev, SIS_SCR_PCI_BAR);
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probe_ent->port[1].scr_addr =
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pci_resource_start(pdev, SIS_SCR_PCI_BAR) + 64;
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}
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pci_set_master(pdev);
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pci_enable_intx(pdev);
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/* FIXME: check ata_device_add return value */
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ata_device_add(probe_ent);
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kfree(probe_ent);
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return 0;
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err_out_regions:
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pci_release_regions(pdev);
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err_out:
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if (!pci_dev_busy)
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pci_disable_device(pdev);
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return rc;
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}
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static int __init sis_init(void)
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{
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return pci_module_init(&sis_pci_driver);
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}
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static void __exit sis_exit(void)
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{
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pci_unregister_driver(&sis_pci_driver);
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}
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module_init(sis_init);
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module_exit(sis_exit);
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