903 lines
26 KiB
C
903 lines
26 KiB
C
/******************************************************************************
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* arch/ia64/kernel/paravirt.c
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*
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* Copyright (c) 2008 Isaku Yamahata <yamahata at valinux co jp>
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* VA Linux Systems Japan K.K.
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* Yaozu (Eddie) Dong <eddie.dong@intel.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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*
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*/
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#include <linux/init.h>
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#include <linux/compiler.h>
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#include <linux/io.h>
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#include <linux/irq.h>
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#include <linux/module.h>
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#include <linux/types.h>
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#include <asm/iosapic.h>
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#include <asm/paravirt.h>
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/***************************************************************************
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* general info
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*/
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struct pv_info pv_info = {
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.kernel_rpl = 0,
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.paravirt_enabled = 0,
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.name = "bare hardware"
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};
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/***************************************************************************
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* pv_init_ops
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* initialization hooks.
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*/
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static void __init
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ia64_native_patch_branch(unsigned long tag, unsigned long type);
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struct pv_init_ops pv_init_ops =
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{
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#ifdef ASM_SUPPORTED
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.patch_bundle = ia64_native_patch_bundle,
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#endif
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.patch_branch = ia64_native_patch_branch,
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};
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/***************************************************************************
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* pv_cpu_ops
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* intrinsics hooks.
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*/
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#ifndef ASM_SUPPORTED
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/* ia64_native_xxx are macros so that we have to make them real functions */
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#define DEFINE_VOID_FUNC1(name) \
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static void \
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ia64_native_ ## name ## _func(unsigned long arg) \
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{ \
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ia64_native_ ## name(arg); \
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}
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#define DEFINE_VOID_FUNC1_VOID(name) \
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static void \
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ia64_native_ ## name ## _func(void *arg) \
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{ \
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ia64_native_ ## name(arg); \
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}
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#define DEFINE_VOID_FUNC2(name) \
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static void \
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ia64_native_ ## name ## _func(unsigned long arg0, \
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unsigned long arg1) \
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{ \
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ia64_native_ ## name(arg0, arg1); \
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}
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#define DEFINE_FUNC0(name) \
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static unsigned long \
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ia64_native_ ## name ## _func(void) \
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{ \
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return ia64_native_ ## name(); \
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}
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#define DEFINE_FUNC1(name, type) \
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static unsigned long \
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ia64_native_ ## name ## _func(type arg) \
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{ \
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return ia64_native_ ## name(arg); \
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} \
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DEFINE_VOID_FUNC1_VOID(fc);
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DEFINE_VOID_FUNC1(intrin_local_irq_restore);
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DEFINE_VOID_FUNC2(ptcga);
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DEFINE_VOID_FUNC2(set_rr);
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DEFINE_FUNC0(get_psr_i);
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DEFINE_FUNC1(thash, unsigned long);
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DEFINE_FUNC1(get_cpuid, int);
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DEFINE_FUNC1(get_pmd, int);
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DEFINE_FUNC1(get_rr, unsigned long);
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static void
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ia64_native_ssm_i_func(void)
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{
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ia64_native_ssm(IA64_PSR_I);
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}
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static void
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ia64_native_rsm_i_func(void)
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{
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ia64_native_rsm(IA64_PSR_I);
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}
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static void
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ia64_native_set_rr0_to_rr4_func(unsigned long val0, unsigned long val1,
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unsigned long val2, unsigned long val3,
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unsigned long val4)
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{
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ia64_native_set_rr0_to_rr4(val0, val1, val2, val3, val4);
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}
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#define CASE_GET_REG(id) \
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case _IA64_REG_ ## id: \
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res = ia64_native_getreg(_IA64_REG_ ## id); \
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break;
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#define CASE_GET_AR(id) CASE_GET_REG(AR_ ## id)
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#define CASE_GET_CR(id) CASE_GET_REG(CR_ ## id)
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unsigned long
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ia64_native_getreg_func(int regnum)
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{
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unsigned long res = -1;
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switch (regnum) {
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CASE_GET_REG(GP);
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/*CASE_GET_REG(IP);*/ /* returned ip value shouldn't be constant */
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CASE_GET_REG(PSR);
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CASE_GET_REG(TP);
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CASE_GET_REG(SP);
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CASE_GET_AR(KR0);
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CASE_GET_AR(KR1);
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CASE_GET_AR(KR2);
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CASE_GET_AR(KR3);
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CASE_GET_AR(KR4);
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CASE_GET_AR(KR5);
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CASE_GET_AR(KR6);
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CASE_GET_AR(KR7);
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CASE_GET_AR(RSC);
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CASE_GET_AR(BSP);
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CASE_GET_AR(BSPSTORE);
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CASE_GET_AR(RNAT);
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CASE_GET_AR(FCR);
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CASE_GET_AR(EFLAG);
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CASE_GET_AR(CSD);
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CASE_GET_AR(SSD);
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CASE_GET_AR(CFLAG);
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CASE_GET_AR(FSR);
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CASE_GET_AR(FIR);
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CASE_GET_AR(FDR);
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CASE_GET_AR(CCV);
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CASE_GET_AR(UNAT);
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CASE_GET_AR(FPSR);
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CASE_GET_AR(ITC);
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CASE_GET_AR(PFS);
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CASE_GET_AR(LC);
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CASE_GET_AR(EC);
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CASE_GET_CR(DCR);
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CASE_GET_CR(ITM);
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CASE_GET_CR(IVA);
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CASE_GET_CR(PTA);
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CASE_GET_CR(IPSR);
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CASE_GET_CR(ISR);
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CASE_GET_CR(IIP);
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CASE_GET_CR(IFA);
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CASE_GET_CR(ITIR);
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CASE_GET_CR(IIPA);
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CASE_GET_CR(IFS);
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CASE_GET_CR(IIM);
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CASE_GET_CR(IHA);
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CASE_GET_CR(LID);
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CASE_GET_CR(IVR);
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CASE_GET_CR(TPR);
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CASE_GET_CR(EOI);
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CASE_GET_CR(IRR0);
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CASE_GET_CR(IRR1);
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CASE_GET_CR(IRR2);
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CASE_GET_CR(IRR3);
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CASE_GET_CR(ITV);
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CASE_GET_CR(PMV);
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CASE_GET_CR(CMCV);
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CASE_GET_CR(LRR0);
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CASE_GET_CR(LRR1);
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default:
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printk(KERN_CRIT "wrong_getreg %d\n", regnum);
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break;
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}
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return res;
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}
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#define CASE_SET_REG(id) \
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case _IA64_REG_ ## id: \
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ia64_native_setreg(_IA64_REG_ ## id, val); \
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break;
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#define CASE_SET_AR(id) CASE_SET_REG(AR_ ## id)
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#define CASE_SET_CR(id) CASE_SET_REG(CR_ ## id)
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void
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ia64_native_setreg_func(int regnum, unsigned long val)
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{
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switch (regnum) {
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case _IA64_REG_PSR_L:
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ia64_native_setreg(_IA64_REG_PSR_L, val);
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ia64_dv_serialize_data();
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break;
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CASE_SET_REG(SP);
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CASE_SET_REG(GP);
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CASE_SET_AR(KR0);
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CASE_SET_AR(KR1);
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CASE_SET_AR(KR2);
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CASE_SET_AR(KR3);
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CASE_SET_AR(KR4);
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CASE_SET_AR(KR5);
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CASE_SET_AR(KR6);
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CASE_SET_AR(KR7);
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CASE_SET_AR(RSC);
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CASE_SET_AR(BSP);
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CASE_SET_AR(BSPSTORE);
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CASE_SET_AR(RNAT);
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CASE_SET_AR(FCR);
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CASE_SET_AR(EFLAG);
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CASE_SET_AR(CSD);
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CASE_SET_AR(SSD);
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CASE_SET_AR(CFLAG);
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CASE_SET_AR(FSR);
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CASE_SET_AR(FIR);
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CASE_SET_AR(FDR);
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CASE_SET_AR(CCV);
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CASE_SET_AR(UNAT);
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CASE_SET_AR(FPSR);
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CASE_SET_AR(ITC);
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CASE_SET_AR(PFS);
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CASE_SET_AR(LC);
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CASE_SET_AR(EC);
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CASE_SET_CR(DCR);
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CASE_SET_CR(ITM);
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CASE_SET_CR(IVA);
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CASE_SET_CR(PTA);
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CASE_SET_CR(IPSR);
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CASE_SET_CR(ISR);
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CASE_SET_CR(IIP);
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CASE_SET_CR(IFA);
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CASE_SET_CR(ITIR);
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CASE_SET_CR(IIPA);
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CASE_SET_CR(IFS);
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CASE_SET_CR(IIM);
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CASE_SET_CR(IHA);
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CASE_SET_CR(LID);
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CASE_SET_CR(IVR);
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CASE_SET_CR(TPR);
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CASE_SET_CR(EOI);
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CASE_SET_CR(IRR0);
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CASE_SET_CR(IRR1);
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CASE_SET_CR(IRR2);
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CASE_SET_CR(IRR3);
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CASE_SET_CR(ITV);
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CASE_SET_CR(PMV);
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CASE_SET_CR(CMCV);
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CASE_SET_CR(LRR0);
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CASE_SET_CR(LRR1);
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default:
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printk(KERN_CRIT "wrong setreg %d\n", regnum);
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break;
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}
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}
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#else
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#define __DEFINE_FUNC(name, code) \
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extern const char ia64_native_ ## name ## _direct_start[]; \
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extern const char ia64_native_ ## name ## _direct_end[]; \
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asm (".align 32\n" \
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".proc ia64_native_" #name "_func\n" \
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"ia64_native_" #name "_func:\n" \
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"ia64_native_" #name "_direct_start:\n" \
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code \
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"ia64_native_" #name "_direct_end:\n" \
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"br.cond.sptk.many b6\n" \
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".endp ia64_native_" #name "_func\n")
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#define DEFINE_VOID_FUNC0(name, code) \
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extern void \
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ia64_native_ ## name ## _func(void); \
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__DEFINE_FUNC(name, code)
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#define DEFINE_VOID_FUNC1(name, code) \
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extern void \
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ia64_native_ ## name ## _func(unsigned long arg); \
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__DEFINE_FUNC(name, code)
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#define DEFINE_VOID_FUNC1_VOID(name, code) \
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extern void \
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ia64_native_ ## name ## _func(void *arg); \
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__DEFINE_FUNC(name, code)
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#define DEFINE_VOID_FUNC2(name, code) \
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extern void \
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ia64_native_ ## name ## _func(unsigned long arg0, \
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unsigned long arg1); \
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__DEFINE_FUNC(name, code)
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#define DEFINE_FUNC0(name, code) \
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extern unsigned long \
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ia64_native_ ## name ## _func(void); \
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__DEFINE_FUNC(name, code)
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#define DEFINE_FUNC1(name, type, code) \
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extern unsigned long \
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ia64_native_ ## name ## _func(type arg); \
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__DEFINE_FUNC(name, code)
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DEFINE_VOID_FUNC1_VOID(fc,
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"fc r8\n");
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DEFINE_VOID_FUNC1(intrin_local_irq_restore,
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";;\n"
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" cmp.ne p6, p7 = r8, r0\n"
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";;\n"
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"(p6) ssm psr.i\n"
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"(p7) rsm psr.i\n"
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";;\n"
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"(p6) srlz.d\n");
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DEFINE_VOID_FUNC2(ptcga,
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"ptc.ga r8, r9\n");
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DEFINE_VOID_FUNC2(set_rr,
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"mov rr[r8] = r9\n");
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/* ia64_native_getreg(_IA64_REG_PSR) & IA64_PSR_I */
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DEFINE_FUNC0(get_psr_i,
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"mov r2 = " __stringify(1 << IA64_PSR_I_BIT) "\n"
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"mov r8 = psr\n"
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";;\n"
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"and r8 = r2, r8\n");
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DEFINE_FUNC1(thash, unsigned long,
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"thash r8 = r8\n");
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DEFINE_FUNC1(get_cpuid, int,
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"mov r8 = cpuid[r8]\n");
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DEFINE_FUNC1(get_pmd, int,
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"mov r8 = pmd[r8]\n");
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DEFINE_FUNC1(get_rr, unsigned long,
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"mov r8 = rr[r8]\n");
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DEFINE_VOID_FUNC0(ssm_i,
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"ssm psr.i\n");
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DEFINE_VOID_FUNC0(rsm_i,
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"rsm psr.i\n");
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extern void
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ia64_native_set_rr0_to_rr4_func(unsigned long val0, unsigned long val1,
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unsigned long val2, unsigned long val3,
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unsigned long val4);
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__DEFINE_FUNC(set_rr0_to_rr4,
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"mov rr[r0] = r8\n"
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"movl r2 = 0x2000000000000000\n"
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";;\n"
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"mov rr[r2] = r9\n"
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"shl r3 = r2, 1\n" /* movl r3 = 0x4000000000000000 */
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";;\n"
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"add r2 = r2, r3\n" /* movl r2 = 0x6000000000000000 */
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"mov rr[r3] = r10\n"
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";;\n"
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"mov rr[r2] = r11\n"
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"shl r3 = r3, 1\n" /* movl r3 = 0x8000000000000000 */
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";;\n"
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"mov rr[r3] = r14\n");
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extern unsigned long ia64_native_getreg_func(int regnum);
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asm(".global ia64_native_getreg_func\n");
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#define __DEFINE_GET_REG(id, reg) \
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"mov r2 = " __stringify(_IA64_REG_ ## id) "\n" \
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";;\n" \
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"cmp.eq p6, p0 = r2, r8\n" \
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";;\n" \
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"(p6) mov r8 = " #reg "\n" \
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"(p6) br.cond.sptk.many b6\n" \
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";;\n"
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#define __DEFINE_GET_AR(id, reg) __DEFINE_GET_REG(AR_ ## id, ar.reg)
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#define __DEFINE_GET_CR(id, reg) __DEFINE_GET_REG(CR_ ## id, cr.reg)
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__DEFINE_FUNC(getreg,
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__DEFINE_GET_REG(GP, gp)
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/*__DEFINE_GET_REG(IP, ip)*/ /* returned ip value shouldn't be constant */
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__DEFINE_GET_REG(PSR, psr)
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__DEFINE_GET_REG(TP, tp)
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__DEFINE_GET_REG(SP, sp)
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__DEFINE_GET_REG(AR_KR0, ar0)
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__DEFINE_GET_REG(AR_KR1, ar1)
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__DEFINE_GET_REG(AR_KR2, ar2)
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__DEFINE_GET_REG(AR_KR3, ar3)
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__DEFINE_GET_REG(AR_KR4, ar4)
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__DEFINE_GET_REG(AR_KR5, ar5)
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__DEFINE_GET_REG(AR_KR6, ar6)
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__DEFINE_GET_REG(AR_KR7, ar7)
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__DEFINE_GET_AR(RSC, rsc)
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__DEFINE_GET_AR(BSP, bsp)
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__DEFINE_GET_AR(BSPSTORE, bspstore)
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__DEFINE_GET_AR(RNAT, rnat)
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__DEFINE_GET_AR(FCR, fcr)
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__DEFINE_GET_AR(EFLAG, eflag)
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__DEFINE_GET_AR(CSD, csd)
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__DEFINE_GET_AR(SSD, ssd)
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__DEFINE_GET_REG(AR_CFLAG, ar27)
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__DEFINE_GET_AR(FSR, fsr)
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__DEFINE_GET_AR(FIR, fir)
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__DEFINE_GET_AR(FDR, fdr)
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__DEFINE_GET_AR(CCV, ccv)
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__DEFINE_GET_AR(UNAT, unat)
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__DEFINE_GET_AR(FPSR, fpsr)
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__DEFINE_GET_AR(ITC, itc)
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__DEFINE_GET_AR(PFS, pfs)
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__DEFINE_GET_AR(LC, lc)
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__DEFINE_GET_AR(EC, ec)
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__DEFINE_GET_CR(DCR, dcr)
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__DEFINE_GET_CR(ITM, itm)
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__DEFINE_GET_CR(IVA, iva)
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__DEFINE_GET_CR(PTA, pta)
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__DEFINE_GET_CR(IPSR, ipsr)
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__DEFINE_GET_CR(ISR, isr)
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__DEFINE_GET_CR(IIP, iip)
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__DEFINE_GET_CR(IFA, ifa)
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__DEFINE_GET_CR(ITIR, itir)
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__DEFINE_GET_CR(IIPA, iipa)
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__DEFINE_GET_CR(IFS, ifs)
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__DEFINE_GET_CR(IIM, iim)
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__DEFINE_GET_CR(IHA, iha)
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__DEFINE_GET_CR(LID, lid)
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__DEFINE_GET_CR(IVR, ivr)
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__DEFINE_GET_CR(TPR, tpr)
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__DEFINE_GET_CR(EOI, eoi)
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__DEFINE_GET_CR(IRR0, irr0)
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__DEFINE_GET_CR(IRR1, irr1)
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__DEFINE_GET_CR(IRR2, irr2)
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__DEFINE_GET_CR(IRR3, irr3)
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__DEFINE_GET_CR(ITV, itv)
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__DEFINE_GET_CR(PMV, pmv)
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__DEFINE_GET_CR(CMCV, cmcv)
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__DEFINE_GET_CR(LRR0, lrr0)
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__DEFINE_GET_CR(LRR1, lrr1)
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"mov r8 = -1\n" /* unsupported case */
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);
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extern void ia64_native_setreg_func(int regnum, unsigned long val);
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asm(".global ia64_native_setreg_func\n");
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#define __DEFINE_SET_REG(id, reg) \
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"mov r2 = " __stringify(_IA64_REG_ ## id) "\n" \
|
|
";;\n" \
|
|
"cmp.eq p6, p0 = r2, r9\n" \
|
|
";;\n" \
|
|
"(p6) mov " #reg " = r8\n" \
|
|
"(p6) br.cond.sptk.many b6\n" \
|
|
";;\n"
|
|
#define __DEFINE_SET_AR(id, reg) __DEFINE_SET_REG(AR_ ## id, ar.reg)
|
|
#define __DEFINE_SET_CR(id, reg) __DEFINE_SET_REG(CR_ ## id, cr.reg)
|
|
__DEFINE_FUNC(setreg,
|
|
"mov r2 = " __stringify(_IA64_REG_PSR_L) "\n"
|
|
";;\n"
|
|
"cmp.eq p6, p0 = r2, r9\n"
|
|
";;\n"
|
|
"(p6) mov psr.l = r8\n"
|
|
#ifdef HAVE_SERIALIZE_DIRECTIVE
|
|
".serialize.data\n"
|
|
#endif
|
|
"(p6) br.cond.sptk.many b6\n"
|
|
__DEFINE_SET_REG(GP, gp)
|
|
__DEFINE_SET_REG(SP, sp)
|
|
|
|
__DEFINE_SET_REG(AR_KR0, ar0)
|
|
__DEFINE_SET_REG(AR_KR1, ar1)
|
|
__DEFINE_SET_REG(AR_KR2, ar2)
|
|
__DEFINE_SET_REG(AR_KR3, ar3)
|
|
__DEFINE_SET_REG(AR_KR4, ar4)
|
|
__DEFINE_SET_REG(AR_KR5, ar5)
|
|
__DEFINE_SET_REG(AR_KR6, ar6)
|
|
__DEFINE_SET_REG(AR_KR7, ar7)
|
|
__DEFINE_SET_AR(RSC, rsc)
|
|
__DEFINE_SET_AR(BSP, bsp)
|
|
__DEFINE_SET_AR(BSPSTORE, bspstore)
|
|
__DEFINE_SET_AR(RNAT, rnat)
|
|
__DEFINE_SET_AR(FCR, fcr)
|
|
__DEFINE_SET_AR(EFLAG, eflag)
|
|
__DEFINE_SET_AR(CSD, csd)
|
|
__DEFINE_SET_AR(SSD, ssd)
|
|
__DEFINE_SET_REG(AR_CFLAG, ar27)
|
|
__DEFINE_SET_AR(FSR, fsr)
|
|
__DEFINE_SET_AR(FIR, fir)
|
|
__DEFINE_SET_AR(FDR, fdr)
|
|
__DEFINE_SET_AR(CCV, ccv)
|
|
__DEFINE_SET_AR(UNAT, unat)
|
|
__DEFINE_SET_AR(FPSR, fpsr)
|
|
__DEFINE_SET_AR(ITC, itc)
|
|
__DEFINE_SET_AR(PFS, pfs)
|
|
__DEFINE_SET_AR(LC, lc)
|
|
__DEFINE_SET_AR(EC, ec)
|
|
|
|
__DEFINE_SET_CR(DCR, dcr)
|
|
__DEFINE_SET_CR(ITM, itm)
|
|
__DEFINE_SET_CR(IVA, iva)
|
|
__DEFINE_SET_CR(PTA, pta)
|
|
__DEFINE_SET_CR(IPSR, ipsr)
|
|
__DEFINE_SET_CR(ISR, isr)
|
|
__DEFINE_SET_CR(IIP, iip)
|
|
__DEFINE_SET_CR(IFA, ifa)
|
|
__DEFINE_SET_CR(ITIR, itir)
|
|
__DEFINE_SET_CR(IIPA, iipa)
|
|
__DEFINE_SET_CR(IFS, ifs)
|
|
__DEFINE_SET_CR(IIM, iim)
|
|
__DEFINE_SET_CR(IHA, iha)
|
|
__DEFINE_SET_CR(LID, lid)
|
|
__DEFINE_SET_CR(IVR, ivr)
|
|
__DEFINE_SET_CR(TPR, tpr)
|
|
__DEFINE_SET_CR(EOI, eoi)
|
|
__DEFINE_SET_CR(IRR0, irr0)
|
|
__DEFINE_SET_CR(IRR1, irr1)
|
|
__DEFINE_SET_CR(IRR2, irr2)
|
|
__DEFINE_SET_CR(IRR3, irr3)
|
|
__DEFINE_SET_CR(ITV, itv)
|
|
__DEFINE_SET_CR(PMV, pmv)
|
|
__DEFINE_SET_CR(CMCV, cmcv)
|
|
__DEFINE_SET_CR(LRR0, lrr0)
|
|
__DEFINE_SET_CR(LRR1, lrr1)
|
|
);
|
|
#endif
|
|
|
|
struct pv_cpu_ops pv_cpu_ops = {
|
|
.fc = ia64_native_fc_func,
|
|
.thash = ia64_native_thash_func,
|
|
.get_cpuid = ia64_native_get_cpuid_func,
|
|
.get_pmd = ia64_native_get_pmd_func,
|
|
.ptcga = ia64_native_ptcga_func,
|
|
.get_rr = ia64_native_get_rr_func,
|
|
.set_rr = ia64_native_set_rr_func,
|
|
.set_rr0_to_rr4 = ia64_native_set_rr0_to_rr4_func,
|
|
.ssm_i = ia64_native_ssm_i_func,
|
|
.getreg = ia64_native_getreg_func,
|
|
.setreg = ia64_native_setreg_func,
|
|
.rsm_i = ia64_native_rsm_i_func,
|
|
.get_psr_i = ia64_native_get_psr_i_func,
|
|
.intrin_local_irq_restore
|
|
= ia64_native_intrin_local_irq_restore_func,
|
|
};
|
|
EXPORT_SYMBOL(pv_cpu_ops);
|
|
|
|
/******************************************************************************
|
|
* replacement of hand written assembly codes.
|
|
*/
|
|
|
|
void
|
|
paravirt_cpu_asm_init(const struct pv_cpu_asm_switch *cpu_asm_switch)
|
|
{
|
|
extern unsigned long paravirt_switch_to_targ;
|
|
extern unsigned long paravirt_leave_syscall_targ;
|
|
extern unsigned long paravirt_work_processed_syscall_targ;
|
|
extern unsigned long paravirt_leave_kernel_targ;
|
|
|
|
paravirt_switch_to_targ = cpu_asm_switch->switch_to;
|
|
paravirt_leave_syscall_targ = cpu_asm_switch->leave_syscall;
|
|
paravirt_work_processed_syscall_targ =
|
|
cpu_asm_switch->work_processed_syscall;
|
|
paravirt_leave_kernel_targ = cpu_asm_switch->leave_kernel;
|
|
}
|
|
|
|
/***************************************************************************
|
|
* pv_iosapic_ops
|
|
* iosapic read/write hooks.
|
|
*/
|
|
|
|
static unsigned int
|
|
ia64_native_iosapic_read(char __iomem *iosapic, unsigned int reg)
|
|
{
|
|
return __ia64_native_iosapic_read(iosapic, reg);
|
|
}
|
|
|
|
static void
|
|
ia64_native_iosapic_write(char __iomem *iosapic, unsigned int reg, u32 val)
|
|
{
|
|
__ia64_native_iosapic_write(iosapic, reg, val);
|
|
}
|
|
|
|
struct pv_iosapic_ops pv_iosapic_ops = {
|
|
.pcat_compat_init = ia64_native_iosapic_pcat_compat_init,
|
|
.__get_irq_chip = ia64_native_iosapic_get_irq_chip,
|
|
|
|
.__read = ia64_native_iosapic_read,
|
|
.__write = ia64_native_iosapic_write,
|
|
};
|
|
|
|
/***************************************************************************
|
|
* pv_irq_ops
|
|
* irq operations
|
|
*/
|
|
|
|
struct pv_irq_ops pv_irq_ops = {
|
|
.register_ipi = ia64_native_register_ipi,
|
|
|
|
.assign_irq_vector = ia64_native_assign_irq_vector,
|
|
.free_irq_vector = ia64_native_free_irq_vector,
|
|
.register_percpu_irq = ia64_native_register_percpu_irq,
|
|
|
|
.resend_irq = ia64_native_resend_irq,
|
|
};
|
|
|
|
/***************************************************************************
|
|
* pv_time_ops
|
|
* time operations
|
|
*/
|
|
struct static_key paravirt_steal_enabled;
|
|
struct static_key paravirt_steal_rq_enabled;
|
|
|
|
static int
|
|
ia64_native_do_steal_accounting(unsigned long *new_itm)
|
|
{
|
|
return 0;
|
|
}
|
|
|
|
struct pv_time_ops pv_time_ops = {
|
|
.do_steal_accounting = ia64_native_do_steal_accounting,
|
|
.sched_clock = ia64_native_sched_clock,
|
|
};
|
|
|
|
/***************************************************************************
|
|
* binary pacthing
|
|
* pv_init_ops.patch_bundle
|
|
*/
|
|
|
|
#ifdef ASM_SUPPORTED
|
|
#define IA64_NATIVE_PATCH_DEFINE_GET_REG(name, reg) \
|
|
__DEFINE_FUNC(get_ ## name, \
|
|
";;\n" \
|
|
"mov r8 = " #reg "\n" \
|
|
";;\n")
|
|
|
|
#define IA64_NATIVE_PATCH_DEFINE_SET_REG(name, reg) \
|
|
__DEFINE_FUNC(set_ ## name, \
|
|
";;\n" \
|
|
"mov " #reg " = r8\n" \
|
|
";;\n")
|
|
|
|
#define IA64_NATIVE_PATCH_DEFINE_REG(name, reg) \
|
|
IA64_NATIVE_PATCH_DEFINE_GET_REG(name, reg); \
|
|
IA64_NATIVE_PATCH_DEFINE_SET_REG(name, reg) \
|
|
|
|
#define IA64_NATIVE_PATCH_DEFINE_AR(name, reg) \
|
|
IA64_NATIVE_PATCH_DEFINE_REG(ar_ ## name, ar.reg)
|
|
|
|
#define IA64_NATIVE_PATCH_DEFINE_CR(name, reg) \
|
|
IA64_NATIVE_PATCH_DEFINE_REG(cr_ ## name, cr.reg)
|
|
|
|
|
|
IA64_NATIVE_PATCH_DEFINE_GET_REG(psr, psr);
|
|
IA64_NATIVE_PATCH_DEFINE_GET_REG(tp, tp);
|
|
|
|
/* IA64_NATIVE_PATCH_DEFINE_SET_REG(psr_l, psr.l); */
|
|
__DEFINE_FUNC(set_psr_l,
|
|
";;\n"
|
|
"mov psr.l = r8\n"
|
|
#ifdef HAVE_SERIALIZE_DIRECTIVE
|
|
".serialize.data\n"
|
|
#endif
|
|
";;\n");
|
|
|
|
IA64_NATIVE_PATCH_DEFINE_REG(gp, gp);
|
|
IA64_NATIVE_PATCH_DEFINE_REG(sp, sp);
|
|
|
|
IA64_NATIVE_PATCH_DEFINE_REG(kr0, ar0);
|
|
IA64_NATIVE_PATCH_DEFINE_REG(kr1, ar1);
|
|
IA64_NATIVE_PATCH_DEFINE_REG(kr2, ar2);
|
|
IA64_NATIVE_PATCH_DEFINE_REG(kr3, ar3);
|
|
IA64_NATIVE_PATCH_DEFINE_REG(kr4, ar4);
|
|
IA64_NATIVE_PATCH_DEFINE_REG(kr5, ar5);
|
|
IA64_NATIVE_PATCH_DEFINE_REG(kr6, ar6);
|
|
IA64_NATIVE_PATCH_DEFINE_REG(kr7, ar7);
|
|
|
|
IA64_NATIVE_PATCH_DEFINE_AR(rsc, rsc);
|
|
IA64_NATIVE_PATCH_DEFINE_AR(bsp, bsp);
|
|
IA64_NATIVE_PATCH_DEFINE_AR(bspstore, bspstore);
|
|
IA64_NATIVE_PATCH_DEFINE_AR(rnat, rnat);
|
|
IA64_NATIVE_PATCH_DEFINE_AR(fcr, fcr);
|
|
IA64_NATIVE_PATCH_DEFINE_AR(eflag, eflag);
|
|
IA64_NATIVE_PATCH_DEFINE_AR(csd, csd);
|
|
IA64_NATIVE_PATCH_DEFINE_AR(ssd, ssd);
|
|
IA64_NATIVE_PATCH_DEFINE_REG(ar27, ar27);
|
|
IA64_NATIVE_PATCH_DEFINE_AR(fsr, fsr);
|
|
IA64_NATIVE_PATCH_DEFINE_AR(fir, fir);
|
|
IA64_NATIVE_PATCH_DEFINE_AR(fdr, fdr);
|
|
IA64_NATIVE_PATCH_DEFINE_AR(ccv, ccv);
|
|
IA64_NATIVE_PATCH_DEFINE_AR(unat, unat);
|
|
IA64_NATIVE_PATCH_DEFINE_AR(fpsr, fpsr);
|
|
IA64_NATIVE_PATCH_DEFINE_AR(itc, itc);
|
|
IA64_NATIVE_PATCH_DEFINE_AR(pfs, pfs);
|
|
IA64_NATIVE_PATCH_DEFINE_AR(lc, lc);
|
|
IA64_NATIVE_PATCH_DEFINE_AR(ec, ec);
|
|
|
|
IA64_NATIVE_PATCH_DEFINE_CR(dcr, dcr);
|
|
IA64_NATIVE_PATCH_DEFINE_CR(itm, itm);
|
|
IA64_NATIVE_PATCH_DEFINE_CR(iva, iva);
|
|
IA64_NATIVE_PATCH_DEFINE_CR(pta, pta);
|
|
IA64_NATIVE_PATCH_DEFINE_CR(ipsr, ipsr);
|
|
IA64_NATIVE_PATCH_DEFINE_CR(isr, isr);
|
|
IA64_NATIVE_PATCH_DEFINE_CR(iip, iip);
|
|
IA64_NATIVE_PATCH_DEFINE_CR(ifa, ifa);
|
|
IA64_NATIVE_PATCH_DEFINE_CR(itir, itir);
|
|
IA64_NATIVE_PATCH_DEFINE_CR(iipa, iipa);
|
|
IA64_NATIVE_PATCH_DEFINE_CR(ifs, ifs);
|
|
IA64_NATIVE_PATCH_DEFINE_CR(iim, iim);
|
|
IA64_NATIVE_PATCH_DEFINE_CR(iha, iha);
|
|
IA64_NATIVE_PATCH_DEFINE_CR(lid, lid);
|
|
IA64_NATIVE_PATCH_DEFINE_CR(ivr, ivr);
|
|
IA64_NATIVE_PATCH_DEFINE_CR(tpr, tpr);
|
|
IA64_NATIVE_PATCH_DEFINE_CR(eoi, eoi);
|
|
IA64_NATIVE_PATCH_DEFINE_CR(irr0, irr0);
|
|
IA64_NATIVE_PATCH_DEFINE_CR(irr1, irr1);
|
|
IA64_NATIVE_PATCH_DEFINE_CR(irr2, irr2);
|
|
IA64_NATIVE_PATCH_DEFINE_CR(irr3, irr3);
|
|
IA64_NATIVE_PATCH_DEFINE_CR(itv, itv);
|
|
IA64_NATIVE_PATCH_DEFINE_CR(pmv, pmv);
|
|
IA64_NATIVE_PATCH_DEFINE_CR(cmcv, cmcv);
|
|
IA64_NATIVE_PATCH_DEFINE_CR(lrr0, lrr0);
|
|
IA64_NATIVE_PATCH_DEFINE_CR(lrr1, lrr1);
|
|
|
|
static const struct paravirt_patch_bundle_elem ia64_native_patch_bundle_elems[]
|
|
__initdata_or_module =
|
|
{
|
|
#define IA64_NATIVE_PATCH_BUNDLE_ELEM(name, type) \
|
|
{ \
|
|
(void*)ia64_native_ ## name ## _direct_start, \
|
|
(void*)ia64_native_ ## name ## _direct_end, \
|
|
PARAVIRT_PATCH_TYPE_ ## type, \
|
|
}
|
|
|
|
IA64_NATIVE_PATCH_BUNDLE_ELEM(fc, FC),
|
|
IA64_NATIVE_PATCH_BUNDLE_ELEM(thash, THASH),
|
|
IA64_NATIVE_PATCH_BUNDLE_ELEM(get_cpuid, GET_CPUID),
|
|
IA64_NATIVE_PATCH_BUNDLE_ELEM(get_pmd, GET_PMD),
|
|
IA64_NATIVE_PATCH_BUNDLE_ELEM(ptcga, PTCGA),
|
|
IA64_NATIVE_PATCH_BUNDLE_ELEM(get_rr, GET_RR),
|
|
IA64_NATIVE_PATCH_BUNDLE_ELEM(set_rr, SET_RR),
|
|
IA64_NATIVE_PATCH_BUNDLE_ELEM(set_rr0_to_rr4, SET_RR0_TO_RR4),
|
|
IA64_NATIVE_PATCH_BUNDLE_ELEM(ssm_i, SSM_I),
|
|
IA64_NATIVE_PATCH_BUNDLE_ELEM(rsm_i, RSM_I),
|
|
IA64_NATIVE_PATCH_BUNDLE_ELEM(get_psr_i, GET_PSR_I),
|
|
IA64_NATIVE_PATCH_BUNDLE_ELEM(intrin_local_irq_restore,
|
|
INTRIN_LOCAL_IRQ_RESTORE),
|
|
|
|
#define IA64_NATIVE_PATCH_BUNDLE_ELEM_GETREG(name, reg) \
|
|
{ \
|
|
(void*)ia64_native_get_ ## name ## _direct_start, \
|
|
(void*)ia64_native_get_ ## name ## _direct_end, \
|
|
PARAVIRT_PATCH_TYPE_GETREG + _IA64_REG_ ## reg, \
|
|
}
|
|
|
|
#define IA64_NATIVE_PATCH_BUNDLE_ELEM_SETREG(name, reg) \
|
|
{ \
|
|
(void*)ia64_native_set_ ## name ## _direct_start, \
|
|
(void*)ia64_native_set_ ## name ## _direct_end, \
|
|
PARAVIRT_PATCH_TYPE_SETREG + _IA64_REG_ ## reg, \
|
|
}
|
|
|
|
#define IA64_NATIVE_PATCH_BUNDLE_ELEM_REG(name, reg) \
|
|
IA64_NATIVE_PATCH_BUNDLE_ELEM_GETREG(name, reg), \
|
|
IA64_NATIVE_PATCH_BUNDLE_ELEM_SETREG(name, reg) \
|
|
|
|
#define IA64_NATIVE_PATCH_BUNDLE_ELEM_AR(name, reg) \
|
|
IA64_NATIVE_PATCH_BUNDLE_ELEM_REG(ar_ ## name, AR_ ## reg)
|
|
|
|
#define IA64_NATIVE_PATCH_BUNDLE_ELEM_CR(name, reg) \
|
|
IA64_NATIVE_PATCH_BUNDLE_ELEM_REG(cr_ ## name, CR_ ## reg)
|
|
|
|
IA64_NATIVE_PATCH_BUNDLE_ELEM_GETREG(psr, PSR),
|
|
IA64_NATIVE_PATCH_BUNDLE_ELEM_GETREG(tp, TP),
|
|
|
|
IA64_NATIVE_PATCH_BUNDLE_ELEM_SETREG(psr_l, PSR_L),
|
|
|
|
IA64_NATIVE_PATCH_BUNDLE_ELEM_REG(gp, GP),
|
|
IA64_NATIVE_PATCH_BUNDLE_ELEM_REG(sp, SP),
|
|
|
|
IA64_NATIVE_PATCH_BUNDLE_ELEM_REG(kr0, AR_KR0),
|
|
IA64_NATIVE_PATCH_BUNDLE_ELEM_REG(kr1, AR_KR1),
|
|
IA64_NATIVE_PATCH_BUNDLE_ELEM_REG(kr2, AR_KR2),
|
|
IA64_NATIVE_PATCH_BUNDLE_ELEM_REG(kr3, AR_KR3),
|
|
IA64_NATIVE_PATCH_BUNDLE_ELEM_REG(kr4, AR_KR4),
|
|
IA64_NATIVE_PATCH_BUNDLE_ELEM_REG(kr5, AR_KR5),
|
|
IA64_NATIVE_PATCH_BUNDLE_ELEM_REG(kr6, AR_KR6),
|
|
IA64_NATIVE_PATCH_BUNDLE_ELEM_REG(kr7, AR_KR7),
|
|
|
|
IA64_NATIVE_PATCH_BUNDLE_ELEM_AR(rsc, RSC),
|
|
IA64_NATIVE_PATCH_BUNDLE_ELEM_AR(bsp, BSP),
|
|
IA64_NATIVE_PATCH_BUNDLE_ELEM_AR(bspstore, BSPSTORE),
|
|
IA64_NATIVE_PATCH_BUNDLE_ELEM_AR(rnat, RNAT),
|
|
IA64_NATIVE_PATCH_BUNDLE_ELEM_AR(fcr, FCR),
|
|
IA64_NATIVE_PATCH_BUNDLE_ELEM_AR(eflag, EFLAG),
|
|
IA64_NATIVE_PATCH_BUNDLE_ELEM_AR(csd, CSD),
|
|
IA64_NATIVE_PATCH_BUNDLE_ELEM_AR(ssd, SSD),
|
|
IA64_NATIVE_PATCH_BUNDLE_ELEM_REG(ar27, AR_CFLAG),
|
|
IA64_NATIVE_PATCH_BUNDLE_ELEM_AR(fsr, FSR),
|
|
IA64_NATIVE_PATCH_BUNDLE_ELEM_AR(fir, FIR),
|
|
IA64_NATIVE_PATCH_BUNDLE_ELEM_AR(fdr, FDR),
|
|
IA64_NATIVE_PATCH_BUNDLE_ELEM_AR(ccv, CCV),
|
|
IA64_NATIVE_PATCH_BUNDLE_ELEM_AR(unat, UNAT),
|
|
IA64_NATIVE_PATCH_BUNDLE_ELEM_AR(fpsr, FPSR),
|
|
IA64_NATIVE_PATCH_BUNDLE_ELEM_AR(itc, ITC),
|
|
IA64_NATIVE_PATCH_BUNDLE_ELEM_AR(pfs, PFS),
|
|
IA64_NATIVE_PATCH_BUNDLE_ELEM_AR(lc, LC),
|
|
IA64_NATIVE_PATCH_BUNDLE_ELEM_AR(ec, EC),
|
|
|
|
IA64_NATIVE_PATCH_BUNDLE_ELEM_CR(dcr, DCR),
|
|
IA64_NATIVE_PATCH_BUNDLE_ELEM_CR(itm, ITM),
|
|
IA64_NATIVE_PATCH_BUNDLE_ELEM_CR(iva, IVA),
|
|
IA64_NATIVE_PATCH_BUNDLE_ELEM_CR(pta, PTA),
|
|
IA64_NATIVE_PATCH_BUNDLE_ELEM_CR(ipsr, IPSR),
|
|
IA64_NATIVE_PATCH_BUNDLE_ELEM_CR(isr, ISR),
|
|
IA64_NATIVE_PATCH_BUNDLE_ELEM_CR(iip, IIP),
|
|
IA64_NATIVE_PATCH_BUNDLE_ELEM_CR(ifa, IFA),
|
|
IA64_NATIVE_PATCH_BUNDLE_ELEM_CR(itir, ITIR),
|
|
IA64_NATIVE_PATCH_BUNDLE_ELEM_CR(iipa, IIPA),
|
|
IA64_NATIVE_PATCH_BUNDLE_ELEM_CR(ifs, IFS),
|
|
IA64_NATIVE_PATCH_BUNDLE_ELEM_CR(iim, IIM),
|
|
IA64_NATIVE_PATCH_BUNDLE_ELEM_CR(iha, IHA),
|
|
IA64_NATIVE_PATCH_BUNDLE_ELEM_CR(lid, LID),
|
|
IA64_NATIVE_PATCH_BUNDLE_ELEM_CR(ivr, IVR),
|
|
IA64_NATIVE_PATCH_BUNDLE_ELEM_CR(tpr, TPR),
|
|
IA64_NATIVE_PATCH_BUNDLE_ELEM_CR(eoi, EOI),
|
|
IA64_NATIVE_PATCH_BUNDLE_ELEM_CR(irr0, IRR0),
|
|
IA64_NATIVE_PATCH_BUNDLE_ELEM_CR(irr1, IRR1),
|
|
IA64_NATIVE_PATCH_BUNDLE_ELEM_CR(irr2, IRR2),
|
|
IA64_NATIVE_PATCH_BUNDLE_ELEM_CR(irr3, IRR3),
|
|
IA64_NATIVE_PATCH_BUNDLE_ELEM_CR(itv, ITV),
|
|
IA64_NATIVE_PATCH_BUNDLE_ELEM_CR(pmv, PMV),
|
|
IA64_NATIVE_PATCH_BUNDLE_ELEM_CR(cmcv, CMCV),
|
|
IA64_NATIVE_PATCH_BUNDLE_ELEM_CR(lrr0, LRR0),
|
|
IA64_NATIVE_PATCH_BUNDLE_ELEM_CR(lrr1, LRR1),
|
|
};
|
|
|
|
unsigned long __init_or_module
|
|
ia64_native_patch_bundle(void *sbundle, void *ebundle, unsigned long type)
|
|
{
|
|
const unsigned long nelems = sizeof(ia64_native_patch_bundle_elems) /
|
|
sizeof(ia64_native_patch_bundle_elems[0]);
|
|
|
|
return __paravirt_patch_apply_bundle(sbundle, ebundle, type,
|
|
ia64_native_patch_bundle_elems,
|
|
nelems, NULL);
|
|
}
|
|
#endif /* ASM_SUPPOTED */
|
|
|
|
extern const char ia64_native_switch_to[];
|
|
extern const char ia64_native_leave_syscall[];
|
|
extern const char ia64_native_work_processed_syscall[];
|
|
extern const char ia64_native_leave_kernel[];
|
|
|
|
const struct paravirt_patch_branch_target ia64_native_branch_target[]
|
|
__initconst = {
|
|
#define PARAVIRT_BR_TARGET(name, type) \
|
|
{ \
|
|
ia64_native_ ## name, \
|
|
PARAVIRT_PATCH_TYPE_BR_ ## type, \
|
|
}
|
|
PARAVIRT_BR_TARGET(switch_to, SWITCH_TO),
|
|
PARAVIRT_BR_TARGET(leave_syscall, LEAVE_SYSCALL),
|
|
PARAVIRT_BR_TARGET(work_processed_syscall, WORK_PROCESSED_SYSCALL),
|
|
PARAVIRT_BR_TARGET(leave_kernel, LEAVE_KERNEL),
|
|
};
|
|
|
|
static void __init
|
|
ia64_native_patch_branch(unsigned long tag, unsigned long type)
|
|
{
|
|
const unsigned long nelem =
|
|
sizeof(ia64_native_branch_target) /
|
|
sizeof(ia64_native_branch_target[0]);
|
|
__paravirt_patch_apply_branch(tag, type,
|
|
ia64_native_branch_target, nelem);
|
|
}
|