82 lines
1.8 KiB
C
82 lines
1.8 KiB
C
/*
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* Copyright (C) 2009 Hans J. Koch <hjk@linutronix.de>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#include <linux/delay.h>
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#include <linux/init.h>
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#include <linux/kernel.h>
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#include <linux/platform_device.h>
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#include <asm/mach-types.h>
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#include <asm/mach/arch.h>
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#include <asm/mach/map.h>
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#include <asm/mach/time.h>
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#include <mach/clock.h>
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#include <mach/tcc-nand.h>
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#include <mach/tcc8k-regs.h>
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#include "common.h"
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#define XI_FREQUENCY 12000000
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#define XTI_FREQUENCY 32768
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#ifdef CONFIG_MTD_NAND_TCC
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/* NAND */
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static struct tcc_nand_platform_data tcc8k_sdk_nand_data = {
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.width = 1,
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.hw_ecc = 0,
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};
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#endif
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static void __init tcc8k_init(void)
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{
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#ifdef CONFIG_MTD_NAND_TCC
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tcc_nand_device.dev.platform_data = &tcc8k_sdk_nand_data;
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platform_device_register(&tcc_nand_device);
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#endif
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}
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static void __init tcc8k_init_timer(void)
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{
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tcc_clocks_init(XI_FREQUENCY, XTI_FREQUENCY);
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}
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static struct sys_timer tcc8k_timer = {
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.init = tcc8k_init_timer,
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};
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static void __init tcc8k_map_io(void)
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{
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tcc8k_map_common_io();
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/* set PLL0 clock to 96MHz, adapt UART0 divisor */
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__raw_writel(0x00026003, CKC_BASE + PLL0CFG_OFFS);
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__raw_writel(0x10000001, CKC_BASE + ACLKUART0_OFFS);
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/* set PLL1 clock to 192MHz */
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__raw_writel(0x00016003, CKC_BASE + PLL1CFG_OFFS);
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/* set PLL2 clock to 48MHz */
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__raw_writel(0x00036003, CKC_BASE + PLL2CFG_OFFS);
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/* with CPU freq higher than 150 MHz, need extra DTCM wait */
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__raw_writel(0x00000001, SCFG_BASE + DTCMWAIT_OFFS);
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/* PLL locking time as specified */
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udelay(300);
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}
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MACHINE_START(TCC8000_SDK, "Telechips TCC8000-SDK Demo Board")
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.atag_offset = 0x100,
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.map_io = tcc8k_map_io,
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.init_irq = tcc8k_init_irq,
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.init_machine = tcc8k_init,
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.timer = &tcc8k_timer,
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MACHINE_END
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