185 lines
5.5 KiB
C
185 lines
5.5 KiB
C
/*
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* arch/arm/include/asm/hardware/clps7111.h
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*
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* This file contains the hardware definitions of the CLPS7111 internal
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* registers.
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*
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* Copyright (C) 2000 Deep Blue Solutions Ltd.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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*/
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#ifndef __ASM_HARDWARE_CLPS7111_H
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#define __ASM_HARDWARE_CLPS7111_H
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#define CLPS7111_PHYS_BASE (0x80000000)
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#ifndef __ASSEMBLY__
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#define clps_readb(off) __raw_readb(CLPS7111_BASE + (off))
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#define clps_readw(off) __raw_readw(CLPS7111_BASE + (off))
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#define clps_readl(off) __raw_readl(CLPS7111_BASE + (off))
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#define clps_writeb(val,off) __raw_writeb(val, CLPS7111_BASE + (off))
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#define clps_writew(val,off) __raw_writew(val, CLPS7111_BASE + (off))
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#define clps_writel(val,off) __raw_writel(val, CLPS7111_BASE + (off))
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#endif
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#define PADR (0x0000)
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#define PBDR (0x0001)
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#define PDDR (0x0003)
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#define PADDR (0x0040)
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#define PBDDR (0x0041)
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#define PDDDR (0x0043)
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#define PEDR (0x0080)
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#define PEDDR (0x00c0)
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#define SYSCON1 (0x0100)
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#define SYSFLG1 (0x0140)
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#define MEMCFG1 (0x0180)
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#define MEMCFG2 (0x01c0)
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#define DRFPR (0x0200)
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#define INTSR1 (0x0240)
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#define INTMR1 (0x0280)
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#define LCDCON (0x02c0)
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#define TC1D (0x0300)
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#define TC2D (0x0340)
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#define RTCDR (0x0380)
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#define RTCMR (0x03c0)
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#define PMPCON (0x0400)
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#define CODR (0x0440)
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#define UARTDR1 (0x0480)
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#define UBRLCR1 (0x04c0)
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#define SYNCIO (0x0500)
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#define PALLSW (0x0540)
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#define PALMSW (0x0580)
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#define STFCLR (0x05c0)
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#define BLEOI (0x0600)
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#define MCEOI (0x0640)
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#define TEOI (0x0680)
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#define TC1EOI (0x06c0)
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#define TC2EOI (0x0700)
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#define RTCEOI (0x0740)
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#define UMSEOI (0x0780)
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#define COEOI (0x07c0)
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#define HALT (0x0800)
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#define STDBY (0x0840)
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#define FBADDR (0x1000)
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#define SYSCON2 (0x1100)
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#define SYSFLG2 (0x1140)
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#define INTSR2 (0x1240)
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#define INTMR2 (0x1280)
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#define UARTDR2 (0x1480)
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#define UBRLCR2 (0x14c0)
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#define SS2DR (0x1500)
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#define SRXEOF (0x1600)
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#define SS2POP (0x16c0)
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#define KBDEOI (0x1700)
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/* common bits: SYSCON1 / SYSCON2 */
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#define SYSCON_UARTEN (1 << 8)
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#define SYSCON1_KBDSCAN(x) ((x) & 15)
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#define SYSCON1_KBDSCANMASK (15)
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#define SYSCON1_TC1M (1 << 4)
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#define SYSCON1_TC1S (1 << 5)
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#define SYSCON1_TC2M (1 << 6)
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#define SYSCON1_TC2S (1 << 7)
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#define SYSCON1_UART1EN SYSCON_UARTEN
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#define SYSCON1_BZTOG (1 << 9)
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#define SYSCON1_BZMOD (1 << 10)
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#define SYSCON1_DBGEN (1 << 11)
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#define SYSCON1_LCDEN (1 << 12)
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#define SYSCON1_CDENTX (1 << 13)
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#define SYSCON1_CDENRX (1 << 14)
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#define SYSCON1_SIREN (1 << 15)
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#define SYSCON1_ADCKSEL(x) (((x) & 3) << 16)
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#define SYSCON1_ADCKSEL_MASK (3 << 16)
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#define SYSCON1_EXCKEN (1 << 18)
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#define SYSCON1_WAKEDIS (1 << 19)
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#define SYSCON1_IRTXM (1 << 20)
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/* common bits: SYSFLG1 / SYSFLG2 */
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#define SYSFLG_UBUSY (1 << 11)
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#define SYSFLG_URXFE (1 << 22)
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#define SYSFLG_UTXFF (1 << 23)
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#define SYSFLG1_MCDR (1 << 0)
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#define SYSFLG1_DCDET (1 << 1)
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#define SYSFLG1_WUDR (1 << 2)
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#define SYSFLG1_WUON (1 << 3)
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#define SYSFLG1_CTS (1 << 8)
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#define SYSFLG1_DSR (1 << 9)
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#define SYSFLG1_DCD (1 << 10)
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#define SYSFLG1_UBUSY SYSFLG_UBUSY
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#define SYSFLG1_NBFLG (1 << 12)
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#define SYSFLG1_RSTFLG (1 << 13)
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#define SYSFLG1_PFFLG (1 << 14)
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#define SYSFLG1_CLDFLG (1 << 15)
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#define SYSFLG1_URXFE SYSFLG_URXFE
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#define SYSFLG1_UTXFF SYSFLG_UTXFF
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#define SYSFLG1_CRXFE (1 << 24)
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#define SYSFLG1_CTXFF (1 << 25)
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#define SYSFLG1_SSIBUSY (1 << 26)
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#define SYSFLG1_ID (1 << 29)
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#define SYSFLG2_SSRXOF (1 << 0)
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#define SYSFLG2_RESVAL (1 << 1)
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#define SYSFLG2_RESFRM (1 << 2)
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#define SYSFLG2_SS2RXFE (1 << 3)
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#define SYSFLG2_SS2TXFF (1 << 4)
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#define SYSFLG2_SS2TXUF (1 << 5)
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#define SYSFLG2_CKMODE (1 << 6)
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#define SYSFLG2_UBUSY SYSFLG_UBUSY
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#define SYSFLG2_URXFE SYSFLG_URXFE
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#define SYSFLG2_UTXFF SYSFLG_UTXFF
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#define LCDCON_GSEN (1 << 30)
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#define LCDCON_GSMD (1 << 31)
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#define SYSCON2_SERSEL (1 << 0)
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#define SYSCON2_KBD6 (1 << 1)
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#define SYSCON2_DRAMZ (1 << 2)
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#define SYSCON2_KBWEN (1 << 3)
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#define SYSCON2_SS2TXEN (1 << 4)
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#define SYSCON2_PCCARD1 (1 << 5)
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#define SYSCON2_PCCARD2 (1 << 6)
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#define SYSCON2_SS2RXEN (1 << 7)
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#define SYSCON2_UART2EN SYSCON_UARTEN
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#define SYSCON2_SS2MAEN (1 << 9)
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#define SYSCON2_OSTB (1 << 12)
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#define SYSCON2_CLKENSL (1 << 13)
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#define SYSCON2_BUZFREQ (1 << 14)
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/* common bits: UARTDR1 / UARTDR2 */
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#define UARTDR_FRMERR (1 << 8)
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#define UARTDR_PARERR (1 << 9)
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#define UARTDR_OVERR (1 << 10)
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/* common bits: UBRLCR1 / UBRLCR2 */
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#define UBRLCR_BAUD_MASK ((1 << 12) - 1)
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#define UBRLCR_BREAK (1 << 12)
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#define UBRLCR_PRTEN (1 << 13)
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#define UBRLCR_EVENPRT (1 << 14)
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#define UBRLCR_XSTOP (1 << 15)
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#define UBRLCR_FIFOEN (1 << 16)
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#define UBRLCR_WRDLEN5 (0 << 17)
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#define UBRLCR_WRDLEN6 (1 << 17)
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#define UBRLCR_WRDLEN7 (2 << 17)
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#define UBRLCR_WRDLEN8 (3 << 17)
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#define UBRLCR_WRDLEN_MASK (3 << 17)
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#define SYNCIO_SMCKEN (1 << 13)
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#define SYNCIO_TXFRMEN (1 << 14)
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#endif /* __ASM_HARDWARE_CLPS7111_H */
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