697 lines
16 KiB
C
697 lines
16 KiB
C
/*
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* linux/arch/sparc64/kernel/setup.c
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*
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* Copyright (C) 1995,1996 David S. Miller (davem@caip.rutgers.edu)
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* Copyright (C) 1997 Jakub Jelinek (jj@sunsite.mff.cuni.cz)
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*/
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#include <linux/errno.h>
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#include <linux/sched.h>
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#include <linux/kernel.h>
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#include <linux/mm.h>
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#include <linux/stddef.h>
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#include <linux/unistd.h>
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#include <linux/ptrace.h>
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#include <asm/smp.h>
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#include <linux/user.h>
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#include <linux/screen_info.h>
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#include <linux/delay.h>
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#include <linux/fs.h>
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#include <linux/seq_file.h>
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#include <linux/syscalls.h>
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#include <linux/kdev_t.h>
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#include <linux/major.h>
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#include <linux/string.h>
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#include <linux/init.h>
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#include <linux/inet.h>
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#include <linux/console.h>
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#include <linux/root_dev.h>
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#include <linux/interrupt.h>
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#include <linux/cpu.h>
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#include <linux/initrd.h>
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#include <linux/module.h>
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#include <linux/start_kernel.h>
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#include <linux/bootmem.h>
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#include <asm/io.h>
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#include <asm/processor.h>
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#include <asm/oplib.h>
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#include <asm/page.h>
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#include <asm/pgtable.h>
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#include <asm/idprom.h>
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#include <asm/head.h>
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#include <asm/starfire.h>
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#include <asm/mmu_context.h>
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#include <asm/timer.h>
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#include <asm/sections.h>
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#include <asm/setup.h>
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#include <asm/mmu.h>
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#include <asm/ns87303.h>
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#include <asm/btext.h>
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#include <asm/elf.h>
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#include <asm/mdesc.h>
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#include <asm/cacheflush.h>
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#include <asm/dma.h>
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#include <asm/irq.h>
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#ifdef CONFIG_IP_PNP
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#include <net/ipconfig.h>
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#endif
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#include "entry.h"
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#include "kernel.h"
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/* Used to synchronize accesses to NatSemi SUPER I/O chip configure
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* operations in asm/ns87303.h
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*/
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DEFINE_SPINLOCK(ns87303_lock);
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EXPORT_SYMBOL(ns87303_lock);
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struct screen_info screen_info = {
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0, 0, /* orig-x, orig-y */
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0, /* unused */
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0, /* orig-video-page */
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0, /* orig-video-mode */
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128, /* orig-video-cols */
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0, 0, 0, /* unused, ega_bx, unused */
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54, /* orig-video-lines */
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0, /* orig-video-isVGA */
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16 /* orig-video-points */
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};
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static void
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prom_console_write(struct console *con, const char *s, unsigned int n)
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{
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prom_write(s, n);
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}
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/* Exported for mm/init.c:paging_init. */
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unsigned long cmdline_memory_size = 0;
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static struct console prom_early_console = {
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.name = "earlyprom",
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.write = prom_console_write,
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.flags = CON_PRINTBUFFER | CON_BOOT | CON_ANYTIME,
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.index = -1,
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};
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/*
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* Process kernel command line switches that are specific to the
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* SPARC or that require special low-level processing.
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*/
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static void __init process_switch(char c)
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{
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switch (c) {
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case 'd':
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case 's':
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break;
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case 'h':
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prom_printf("boot_flags_init: Halt!\n");
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prom_halt();
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break;
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case 'p':
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prom_early_console.flags &= ~CON_BOOT;
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break;
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case 'P':
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/* Force UltraSPARC-III P-Cache on. */
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if (tlb_type != cheetah) {
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printk("BOOT: Ignoring P-Cache force option.\n");
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break;
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}
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cheetah_pcache_forced_on = 1;
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add_taint(TAINT_MACHINE_CHECK, LOCKDEP_NOW_UNRELIABLE);
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cheetah_enable_pcache();
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break;
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default:
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printk("Unknown boot switch (-%c)\n", c);
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break;
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}
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}
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static void __init boot_flags_init(char *commands)
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{
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while (*commands) {
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/* Move to the start of the next "argument". */
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while (*commands && *commands == ' ')
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commands++;
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/* Process any command switches, otherwise skip it. */
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if (*commands == '\0')
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break;
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if (*commands == '-') {
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commands++;
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while (*commands && *commands != ' ')
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process_switch(*commands++);
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continue;
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}
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if (!strncmp(commands, "mem=", 4))
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cmdline_memory_size = memparse(commands + 4, &commands);
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while (*commands && *commands != ' ')
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commands++;
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}
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}
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extern unsigned short root_flags;
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extern unsigned short root_dev;
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extern unsigned short ram_flags;
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#define RAMDISK_IMAGE_START_MASK 0x07FF
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#define RAMDISK_PROMPT_FLAG 0x8000
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#define RAMDISK_LOAD_FLAG 0x4000
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extern int root_mountflags;
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char reboot_command[COMMAND_LINE_SIZE];
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static struct pt_regs fake_swapper_regs = { { 0, }, 0, 0, 0, 0 };
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static void __init per_cpu_patch(void)
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{
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struct cpuid_patch_entry *p;
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unsigned long ver;
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int is_jbus;
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if (tlb_type == spitfire && !this_is_starfire)
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return;
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is_jbus = 0;
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if (tlb_type != hypervisor) {
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__asm__ ("rdpr %%ver, %0" : "=r" (ver));
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is_jbus = ((ver >> 32UL) == __JALAPENO_ID ||
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(ver >> 32UL) == __SERRANO_ID);
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}
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p = &__cpuid_patch;
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while (p < &__cpuid_patch_end) {
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unsigned long addr = p->addr;
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unsigned int *insns;
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switch (tlb_type) {
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case spitfire:
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insns = &p->starfire[0];
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break;
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case cheetah:
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case cheetah_plus:
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if (is_jbus)
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insns = &p->cheetah_jbus[0];
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else
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insns = &p->cheetah_safari[0];
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break;
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case hypervisor:
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insns = &p->sun4v[0];
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break;
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default:
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prom_printf("Unknown cpu type, halting.\n");
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prom_halt();
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}
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*(unsigned int *) (addr + 0) = insns[0];
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wmb();
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__asm__ __volatile__("flush %0" : : "r" (addr + 0));
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*(unsigned int *) (addr + 4) = insns[1];
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wmb();
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__asm__ __volatile__("flush %0" : : "r" (addr + 4));
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*(unsigned int *) (addr + 8) = insns[2];
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wmb();
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__asm__ __volatile__("flush %0" : : "r" (addr + 8));
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*(unsigned int *) (addr + 12) = insns[3];
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wmb();
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__asm__ __volatile__("flush %0" : : "r" (addr + 12));
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p++;
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}
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}
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void sun4v_patch_1insn_range(struct sun4v_1insn_patch_entry *start,
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struct sun4v_1insn_patch_entry *end)
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{
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while (start < end) {
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unsigned long addr = start->addr;
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*(unsigned int *) (addr + 0) = start->insn;
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wmb();
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__asm__ __volatile__("flush %0" : : "r" (addr + 0));
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start++;
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}
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}
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void sun4v_patch_2insn_range(struct sun4v_2insn_patch_entry *start,
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struct sun4v_2insn_patch_entry *end)
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{
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while (start < end) {
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unsigned long addr = start->addr;
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*(unsigned int *) (addr + 0) = start->insns[0];
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wmb();
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__asm__ __volatile__("flush %0" : : "r" (addr + 0));
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*(unsigned int *) (addr + 4) = start->insns[1];
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wmb();
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__asm__ __volatile__("flush %0" : : "r" (addr + 4));
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start++;
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}
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}
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void sun_m7_patch_2insn_range(struct sun4v_2insn_patch_entry *start,
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struct sun4v_2insn_patch_entry *end)
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{
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while (start < end) {
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unsigned long addr = start->addr;
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*(unsigned int *) (addr + 0) = start->insns[0];
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wmb();
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__asm__ __volatile__("flush %0" : : "r" (addr + 0));
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*(unsigned int *) (addr + 4) = start->insns[1];
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wmb();
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__asm__ __volatile__("flush %0" : : "r" (addr + 4));
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start++;
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}
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}
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static void __init sun4v_patch(void)
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{
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extern void sun4v_hvapi_init(void);
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if (tlb_type != hypervisor)
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return;
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sun4v_patch_1insn_range(&__sun4v_1insn_patch,
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&__sun4v_1insn_patch_end);
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sun4v_patch_2insn_range(&__sun4v_2insn_patch,
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&__sun4v_2insn_patch_end);
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if (sun4v_chip_type == SUN4V_CHIP_SPARC_M7 ||
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sun4v_chip_type == SUN4V_CHIP_SPARC_SN)
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sun_m7_patch_2insn_range(&__sun_m7_2insn_patch,
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&__sun_m7_2insn_patch_end);
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sun4v_hvapi_init();
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}
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static void __init popc_patch(void)
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{
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struct popc_3insn_patch_entry *p3;
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struct popc_6insn_patch_entry *p6;
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p3 = &__popc_3insn_patch;
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while (p3 < &__popc_3insn_patch_end) {
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unsigned long i, addr = p3->addr;
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for (i = 0; i < 3; i++) {
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*(unsigned int *) (addr + (i * 4)) = p3->insns[i];
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wmb();
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__asm__ __volatile__("flush %0"
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: : "r" (addr + (i * 4)));
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}
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p3++;
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}
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p6 = &__popc_6insn_patch;
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while (p6 < &__popc_6insn_patch_end) {
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unsigned long i, addr = p6->addr;
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for (i = 0; i < 6; i++) {
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*(unsigned int *) (addr + (i * 4)) = p6->insns[i];
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wmb();
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__asm__ __volatile__("flush %0"
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: : "r" (addr + (i * 4)));
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}
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p6++;
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}
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}
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static void __init pause_patch(void)
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{
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struct pause_patch_entry *p;
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p = &__pause_3insn_patch;
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while (p < &__pause_3insn_patch_end) {
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unsigned long i, addr = p->addr;
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for (i = 0; i < 3; i++) {
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*(unsigned int *) (addr + (i * 4)) = p->insns[i];
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wmb();
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__asm__ __volatile__("flush %0"
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: : "r" (addr + (i * 4)));
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}
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p++;
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}
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}
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void __init start_early_boot(void)
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{
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int cpu;
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check_if_starfire();
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per_cpu_patch();
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sun4v_patch();
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cpu = hard_smp_processor_id();
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if (cpu >= NR_CPUS) {
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prom_printf("Serious problem, boot cpu id (%d) >= NR_CPUS (%d)\n",
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cpu, NR_CPUS);
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prom_halt();
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}
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current_thread_info()->cpu = cpu;
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prom_init_report();
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start_kernel();
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}
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/* On Ultra, we support all of the v8 capabilities. */
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unsigned long sparc64_elf_hwcap = (HWCAP_SPARC_FLUSH | HWCAP_SPARC_STBAR |
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HWCAP_SPARC_SWAP | HWCAP_SPARC_MULDIV |
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HWCAP_SPARC_V9);
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EXPORT_SYMBOL(sparc64_elf_hwcap);
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static const char *hwcaps[] = {
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"flush", "stbar", "swap", "muldiv", "v9",
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"ultra3", "blkinit", "n2",
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/* These strings are as they appear in the machine description
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* 'hwcap-list' property for cpu nodes.
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*/
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"mul32", "div32", "fsmuld", "v8plus", "popc", "vis", "vis2",
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"ASIBlkInit", "fmaf", "vis3", "hpc", "random", "trans", "fjfmau",
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"ima", "cspare", "pause", "cbcond", NULL /*reserved for crypto */,
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"adp",
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};
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static const char *crypto_hwcaps[] = {
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"aes", "des", "kasumi", "camellia", "md5", "sha1", "sha256",
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"sha512", "mpmul", "montmul", "montsqr", "crc32c",
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};
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void cpucap_info(struct seq_file *m)
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{
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unsigned long caps = sparc64_elf_hwcap;
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int i, printed = 0;
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seq_puts(m, "cpucaps\t\t: ");
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for (i = 0; i < ARRAY_SIZE(hwcaps); i++) {
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unsigned long bit = 1UL << i;
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if (hwcaps[i] && (caps & bit)) {
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seq_printf(m, "%s%s",
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printed ? "," : "", hwcaps[i]);
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printed++;
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}
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}
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if (caps & HWCAP_SPARC_CRYPTO) {
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unsigned long cfr;
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__asm__ __volatile__("rd %%asr26, %0" : "=r" (cfr));
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for (i = 0; i < ARRAY_SIZE(crypto_hwcaps); i++) {
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unsigned long bit = 1UL << i;
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if (cfr & bit) {
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seq_printf(m, "%s%s",
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printed ? "," : "", crypto_hwcaps[i]);
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printed++;
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}
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}
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}
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seq_putc(m, '\n');
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}
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static void __init report_one_hwcap(int *printed, const char *name)
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{
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if ((*printed) == 0)
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printk(KERN_INFO "CPU CAPS: [");
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printk(KERN_CONT "%s%s",
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(*printed) ? "," : "", name);
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if (++(*printed) == 8) {
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printk(KERN_CONT "]\n");
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*printed = 0;
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}
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}
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static void __init report_crypto_hwcaps(int *printed)
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{
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unsigned long cfr;
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int i;
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__asm__ __volatile__("rd %%asr26, %0" : "=r" (cfr));
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for (i = 0; i < ARRAY_SIZE(crypto_hwcaps); i++) {
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unsigned long bit = 1UL << i;
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if (cfr & bit)
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report_one_hwcap(printed, crypto_hwcaps[i]);
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}
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}
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static void __init report_hwcaps(unsigned long caps)
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{
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int i, printed = 0;
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for (i = 0; i < ARRAY_SIZE(hwcaps); i++) {
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unsigned long bit = 1UL << i;
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if (hwcaps[i] && (caps & bit))
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report_one_hwcap(&printed, hwcaps[i]);
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}
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if (caps & HWCAP_SPARC_CRYPTO)
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report_crypto_hwcaps(&printed);
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if (printed != 0)
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printk(KERN_CONT "]\n");
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}
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static unsigned long __init mdesc_cpu_hwcap_list(void)
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{
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struct mdesc_handle *hp;
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unsigned long caps = 0;
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const char *prop;
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int len;
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u64 pn;
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hp = mdesc_grab();
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if (!hp)
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return 0;
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pn = mdesc_node_by_name(hp, MDESC_NODE_NULL, "cpu");
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if (pn == MDESC_NODE_NULL)
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goto out;
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prop = mdesc_get_property(hp, pn, "hwcap-list", &len);
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if (!prop)
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goto out;
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while (len) {
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int i, plen;
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for (i = 0; i < ARRAY_SIZE(hwcaps); i++) {
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unsigned long bit = 1UL << i;
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if (hwcaps[i] && !strcmp(prop, hwcaps[i])) {
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caps |= bit;
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break;
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}
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}
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for (i = 0; i < ARRAY_SIZE(crypto_hwcaps); i++) {
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if (!strcmp(prop, crypto_hwcaps[i]))
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caps |= HWCAP_SPARC_CRYPTO;
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}
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plen = strlen(prop) + 1;
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prop += plen;
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len -= plen;
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}
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out:
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mdesc_release(hp);
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return caps;
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}
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/* This yields a mask that user programs can use to figure out what
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* instruction set this cpu supports.
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*/
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static void __init init_sparc64_elf_hwcap(void)
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{
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unsigned long cap = sparc64_elf_hwcap;
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unsigned long mdesc_caps;
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if (tlb_type == cheetah || tlb_type == cheetah_plus)
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cap |= HWCAP_SPARC_ULTRA3;
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else if (tlb_type == hypervisor) {
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if (sun4v_chip_type == SUN4V_CHIP_NIAGARA1 ||
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sun4v_chip_type == SUN4V_CHIP_NIAGARA2 ||
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sun4v_chip_type == SUN4V_CHIP_NIAGARA3 ||
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sun4v_chip_type == SUN4V_CHIP_NIAGARA4 ||
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|
sun4v_chip_type == SUN4V_CHIP_NIAGARA5 ||
|
|
sun4v_chip_type == SUN4V_CHIP_SPARC_M6 ||
|
|
sun4v_chip_type == SUN4V_CHIP_SPARC_M7 ||
|
|
sun4v_chip_type == SUN4V_CHIP_SPARC_SN ||
|
|
sun4v_chip_type == SUN4V_CHIP_SPARC64X)
|
|
cap |= HWCAP_SPARC_BLKINIT;
|
|
if (sun4v_chip_type == SUN4V_CHIP_NIAGARA2 ||
|
|
sun4v_chip_type == SUN4V_CHIP_NIAGARA3 ||
|
|
sun4v_chip_type == SUN4V_CHIP_NIAGARA4 ||
|
|
sun4v_chip_type == SUN4V_CHIP_NIAGARA5 ||
|
|
sun4v_chip_type == SUN4V_CHIP_SPARC_M6 ||
|
|
sun4v_chip_type == SUN4V_CHIP_SPARC_M7 ||
|
|
sun4v_chip_type == SUN4V_CHIP_SPARC_SN ||
|
|
sun4v_chip_type == SUN4V_CHIP_SPARC64X)
|
|
cap |= HWCAP_SPARC_N2;
|
|
}
|
|
|
|
cap |= (AV_SPARC_MUL32 | AV_SPARC_DIV32 | AV_SPARC_V8PLUS);
|
|
|
|
mdesc_caps = mdesc_cpu_hwcap_list();
|
|
if (!mdesc_caps) {
|
|
if (tlb_type == spitfire)
|
|
cap |= AV_SPARC_VIS;
|
|
if (tlb_type == cheetah || tlb_type == cheetah_plus)
|
|
cap |= AV_SPARC_VIS | AV_SPARC_VIS2;
|
|
if (tlb_type == cheetah_plus) {
|
|
unsigned long impl, ver;
|
|
|
|
__asm__ __volatile__("rdpr %%ver, %0" : "=r" (ver));
|
|
impl = ((ver >> 32) & 0xffff);
|
|
if (impl == PANTHER_IMPL)
|
|
cap |= AV_SPARC_POPC;
|
|
}
|
|
if (tlb_type == hypervisor) {
|
|
if (sun4v_chip_type == SUN4V_CHIP_NIAGARA1)
|
|
cap |= AV_SPARC_ASI_BLK_INIT;
|
|
if (sun4v_chip_type == SUN4V_CHIP_NIAGARA2 ||
|
|
sun4v_chip_type == SUN4V_CHIP_NIAGARA3 ||
|
|
sun4v_chip_type == SUN4V_CHIP_NIAGARA4 ||
|
|
sun4v_chip_type == SUN4V_CHIP_NIAGARA5 ||
|
|
sun4v_chip_type == SUN4V_CHIP_SPARC_M6 ||
|
|
sun4v_chip_type == SUN4V_CHIP_SPARC_M7 ||
|
|
sun4v_chip_type == SUN4V_CHIP_SPARC_SN ||
|
|
sun4v_chip_type == SUN4V_CHIP_SPARC64X)
|
|
cap |= (AV_SPARC_VIS | AV_SPARC_VIS2 |
|
|
AV_SPARC_ASI_BLK_INIT |
|
|
AV_SPARC_POPC);
|
|
if (sun4v_chip_type == SUN4V_CHIP_NIAGARA3 ||
|
|
sun4v_chip_type == SUN4V_CHIP_NIAGARA4 ||
|
|
sun4v_chip_type == SUN4V_CHIP_NIAGARA5 ||
|
|
sun4v_chip_type == SUN4V_CHIP_SPARC_M6 ||
|
|
sun4v_chip_type == SUN4V_CHIP_SPARC_M7 ||
|
|
sun4v_chip_type == SUN4V_CHIP_SPARC_SN ||
|
|
sun4v_chip_type == SUN4V_CHIP_SPARC64X)
|
|
cap |= (AV_SPARC_VIS3 | AV_SPARC_HPC |
|
|
AV_SPARC_FMAF);
|
|
}
|
|
}
|
|
sparc64_elf_hwcap = cap | mdesc_caps;
|
|
|
|
report_hwcaps(sparc64_elf_hwcap);
|
|
|
|
if (sparc64_elf_hwcap & AV_SPARC_POPC)
|
|
popc_patch();
|
|
if (sparc64_elf_hwcap & AV_SPARC_PAUSE)
|
|
pause_patch();
|
|
}
|
|
|
|
void __init alloc_irqstack_bootmem(void)
|
|
{
|
|
unsigned int i, node;
|
|
|
|
for_each_possible_cpu(i) {
|
|
node = cpu_to_node(i);
|
|
|
|
softirq_stack[i] = __alloc_bootmem_node(NODE_DATA(node),
|
|
THREAD_SIZE,
|
|
THREAD_SIZE, 0);
|
|
hardirq_stack[i] = __alloc_bootmem_node(NODE_DATA(node),
|
|
THREAD_SIZE,
|
|
THREAD_SIZE, 0);
|
|
}
|
|
}
|
|
|
|
void __init setup_arch(char **cmdline_p)
|
|
{
|
|
/* Initialize PROM console and command line. */
|
|
*cmdline_p = prom_getbootargs();
|
|
strlcpy(boot_command_line, *cmdline_p, COMMAND_LINE_SIZE);
|
|
parse_early_param();
|
|
|
|
boot_flags_init(*cmdline_p);
|
|
#ifdef CONFIG_EARLYFB
|
|
if (btext_find_display())
|
|
#endif
|
|
register_console(&prom_early_console);
|
|
|
|
if (tlb_type == hypervisor)
|
|
printk("ARCH: SUN4V\n");
|
|
else
|
|
printk("ARCH: SUN4U\n");
|
|
|
|
#ifdef CONFIG_DUMMY_CONSOLE
|
|
conswitchp = &dummy_con;
|
|
#endif
|
|
|
|
idprom_init();
|
|
|
|
if (!root_flags)
|
|
root_mountflags &= ~MS_RDONLY;
|
|
ROOT_DEV = old_decode_dev(root_dev);
|
|
#ifdef CONFIG_BLK_DEV_RAM
|
|
rd_image_start = ram_flags & RAMDISK_IMAGE_START_MASK;
|
|
rd_prompt = ((ram_flags & RAMDISK_PROMPT_FLAG) != 0);
|
|
rd_doload = ((ram_flags & RAMDISK_LOAD_FLAG) != 0);
|
|
#endif
|
|
|
|
task_thread_info(&init_task)->kregs = &fake_swapper_regs;
|
|
|
|
#ifdef CONFIG_IP_PNP
|
|
if (!ic_set_manually) {
|
|
phandle chosen = prom_finddevice("/chosen");
|
|
u32 cl, sv, gw;
|
|
|
|
cl = prom_getintdefault (chosen, "client-ip", 0);
|
|
sv = prom_getintdefault (chosen, "server-ip", 0);
|
|
gw = prom_getintdefault (chosen, "gateway-ip", 0);
|
|
if (cl && sv) {
|
|
ic_myaddr = cl;
|
|
ic_servaddr = sv;
|
|
if (gw)
|
|
ic_gateway = gw;
|
|
#if defined(CONFIG_IP_PNP_BOOTP) || defined(CONFIG_IP_PNP_RARP)
|
|
ic_proto_enabled = 0;
|
|
#endif
|
|
}
|
|
}
|
|
#endif
|
|
|
|
/* Get boot processor trap_block[] setup. */
|
|
init_cur_cpu_trap(current_thread_info());
|
|
|
|
paging_init();
|
|
init_sparc64_elf_hwcap();
|
|
smp_fill_in_cpu_possible_map();
|
|
/*
|
|
* Once the OF device tree and MDESC have been setup and nr_cpus has
|
|
* been parsed, we know the list of possible cpus. Therefore we can
|
|
* allocate the IRQ stacks.
|
|
*/
|
|
alloc_irqstack_bootmem();
|
|
}
|
|
|
|
extern int stop_a_enabled;
|
|
|
|
void sun_do_break(void)
|
|
{
|
|
if (!stop_a_enabled)
|
|
return;
|
|
|
|
prom_printf("\n");
|
|
flush_user_windows();
|
|
|
|
prom_cmdline();
|
|
}
|
|
EXPORT_SYMBOL(sun_do_break);
|
|
|
|
int stop_a_enabled = 1;
|
|
EXPORT_SYMBOL(stop_a_enabled);
|