138 lines
3.8 KiB
C
138 lines
3.8 KiB
C
/*
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* Address map functions for Marvell 370 / XP SoCs
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*
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* Copyright (C) 2012 Marvell
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*
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* Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
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*
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* This file is licensed under the terms of the GNU General Public
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* License version 2. This program is licensed "as is" without any
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* warranty of any kind, whether express or implied.
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*/
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#include <linux/kernel.h>
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#include <linux/init.h>
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#include <linux/mbus.h>
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#include <linux/io.h>
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#include <linux/of.h>
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#include <linux/of_address.h>
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#include <plat/addr-map.h>
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/*
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* Generic Address Decode Windows bit settings
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*/
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#define ARMADA_XP_TARGET_DEV_BUS 1
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#define ARMADA_XP_ATTR_DEV_BOOTROM 0x1D
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#define ARMADA_XP_TARGET_ETH1 3
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#define ARMADA_XP_TARGET_PCIE_0_2 4
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#define ARMADA_XP_TARGET_ETH0 7
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#define ARMADA_XP_TARGET_PCIE_1_3 8
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#define ARMADA_370_TARGET_DEV_BUS 1
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#define ARMADA_370_ATTR_DEV_BOOTROM 0x1D
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#define ARMADA_370_TARGET_PCIE_0 4
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#define ARMADA_370_TARGET_PCIE_1 8
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#define ARMADA_WINDOW_8_PLUS_OFFSET 0x90
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#define ARMADA_SDRAM_ADDR_DECODING_OFFSET 0x180
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static const struct __initdata orion_addr_map_info
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armada_xp_addr_map_info[] = {
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/*
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* Window for the BootROM, needed for SMP on Armada XP
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*/
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{ 0, 0xfff00000, SZ_1M, ARMADA_XP_TARGET_DEV_BUS,
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ARMADA_XP_ATTR_DEV_BOOTROM, -1 },
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/* End marker */
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{ -1, 0, 0, 0, 0, 0 },
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};
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static const struct __initdata orion_addr_map_info
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armada_370_addr_map_info[] = {
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/* End marker */
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{ -1, 0, 0, 0, 0, 0 },
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};
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static struct of_device_id of_addr_decoding_controller_table[] = {
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{ .compatible = "marvell,armada-addr-decoding-controller" },
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{ /* end of list */ },
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};
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static void __iomem *
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armada_cfg_base(const struct orion_addr_map_cfg *cfg, int win)
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{
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unsigned int offset;
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/* The register layout is a bit annoying and the below code
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* tries to cope with it.
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* - At offset 0x0, there are the registers for the first 8
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* windows, with 4 registers of 32 bits per window (ctrl,
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* base, remap low, remap high)
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* - Then at offset 0x80, there is a hole of 0x10 bytes for
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* the internal registers base address and internal units
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* sync barrier register.
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* - Then at offset 0x90, there the registers for 12
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* windows, with only 2 registers of 32 bits per window
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* (ctrl, base).
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*/
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if (win < 8)
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offset = (win << 4);
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else
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offset = ARMADA_WINDOW_8_PLUS_OFFSET + ((win - 8) << 3);
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return cfg->bridge_virt_base + offset;
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}
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static struct __initdata orion_addr_map_cfg addr_map_cfg = {
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.num_wins = 20,
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.remappable_wins = 8,
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.win_cfg_base = armada_cfg_base,
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};
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static int __init armada_setup_cpu_mbus(void)
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{
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struct device_node *np;
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void __iomem *mbus_unit_addr_decoding_base;
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void __iomem *sdram_addr_decoding_base;
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np = of_find_matching_node(NULL, of_addr_decoding_controller_table);
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if (!np)
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return -ENODEV;
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mbus_unit_addr_decoding_base = of_iomap(np, 0);
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BUG_ON(!mbus_unit_addr_decoding_base);
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sdram_addr_decoding_base =
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mbus_unit_addr_decoding_base +
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ARMADA_SDRAM_ADDR_DECODING_OFFSET;
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addr_map_cfg.bridge_virt_base = mbus_unit_addr_decoding_base;
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if (of_find_compatible_node(NULL, NULL, "marvell,coherency-fabric"))
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addr_map_cfg.hw_io_coherency = 1;
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/*
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* Disable, clear and configure windows.
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*/
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if (of_machine_is_compatible("marvell,armadaxp"))
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orion_config_wins(&addr_map_cfg, armada_xp_addr_map_info);
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else if (of_machine_is_compatible("marvell,armada370"))
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orion_config_wins(&addr_map_cfg, armada_370_addr_map_info);
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else {
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pr_err("Unsupported SoC\n");
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return -EINVAL;
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}
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/*
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* Setup MBUS dram target info.
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*/
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orion_setup_cpu_mbus_target(&addr_map_cfg,
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sdram_addr_decoding_base);
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return 0;
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}
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/* Using a early_initcall is needed so that this initialization gets
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* done before the SMP initialization, which requires the BootROM to
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* be remapped. */
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early_initcall(armada_setup_cpu_mbus);
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