238 lines
10 KiB
C
238 lines
10 KiB
C
/*****************************************************************************
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* Copyright 2005 - 2008 Broadcom Corporation. All rights reserved.
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*
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* Unless you and Broadcom execute a separate written software license
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* agreement governing use of this software, this software is licensed to you
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* under the terms of the GNU General Public License version 2, available at
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* http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
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*
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* Notwithstanding the above, under no circumstances may you combine this
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* software in any way with any other Broadcom software provided under a
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* license other than the GPL, without Broadcom's express prior written
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* consent.
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*****************************************************************************/
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/*
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*
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*****************************************************************************
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*
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* REG_UMI.h
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*
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* PURPOSE:
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*
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* This file contains definitions for the nand registers:
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*
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* NOTES:
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*
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*****************************************************************************/
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#if !defined(__ASM_ARCH_REG_UMI_H)
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#define __ASM_ARCH_REG_UMI_H
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/* ---- Include Files ---------------------------------------------------- */
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#include <csp/reg.h>
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#include <mach/csp/mm_io.h>
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/* ---- Constants and Types ---------------------------------------------- */
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/* Unified Memory Interface Ctrl Register */
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#define HW_UMI_BASE MM_IO_BASE_UMI
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/* Flash bank 0 timing and control register */
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#define REG_UMI_FLASH0_TCR __REG32(HW_UMI_BASE + 0x00)
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/* Flash bank 1 timing and control register */
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#define REG_UMI_FLASH1_TCR __REG32(HW_UMI_BASE + 0x04)
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/* Flash bank 2 timing and control register */
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#define REG_UMI_FLASH2_TCR __REG32(HW_UMI_BASE + 0x08)
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/* MMD interface and control register */
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#define REG_UMI_MMD_ICR __REG32(HW_UMI_BASE + 0x0c)
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/* NAND timing and control register */
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#define REG_UMI_NAND_TCR __REG32(HW_UMI_BASE + 0x18)
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/* NAND ready/chip select register */
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#define REG_UMI_NAND_RCSR __REG32(HW_UMI_BASE + 0x1c)
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/* NAND ECC control & status register */
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#define REG_UMI_NAND_ECC_CSR __REG32(HW_UMI_BASE + 0x20)
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/* NAND ECC data register XXB2B1B0 */
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#define REG_UMI_NAND_ECC_DATA __REG32(HW_UMI_BASE + 0x24)
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/* BCH ECC Parameter N */
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#define REG_UMI_BCH_N __REG32(HW_UMI_BASE + 0x40)
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/* BCH ECC Parameter T */
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#define REG_UMI_BCH_K __REG32(HW_UMI_BASE + 0x44)
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/* BCH ECC Parameter K */
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#define REG_UMI_BCH_T __REG32(HW_UMI_BASE + 0x48)
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/* BCH ECC Contro Status */
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#define REG_UMI_BCH_CTRL_STATUS __REG32(HW_UMI_BASE + 0x4C)
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/* BCH WR ECC 31:0 */
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#define REG_UMI_BCH_WR_ECC_0 __REG32(HW_UMI_BASE + 0x50)
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/* BCH WR ECC 63:32 */
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#define REG_UMI_BCH_WR_ECC_1 __REG32(HW_UMI_BASE + 0x54)
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/* BCH WR ECC 95:64 */
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#define REG_UMI_BCH_WR_ECC_2 __REG32(HW_UMI_BASE + 0x58)
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/* BCH WR ECC 127:96 */
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#define REG_UMI_BCH_WR_ECC_3 __REG32(HW_UMI_BASE + 0x5c)
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/* BCH WR ECC 155:128 */
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#define REG_UMI_BCH_WR_ECC_4 __REG32(HW_UMI_BASE + 0x60)
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/* BCH Read Error Location 1,0 */
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#define REG_UMI_BCH_RD_ERR_LOC_1_0 __REG32(HW_UMI_BASE + 0x64)
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/* BCH Read Error Location 3,2 */
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#define REG_UMI_BCH_RD_ERR_LOC_3_2 __REG32(HW_UMI_BASE + 0x68)
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/* BCH Read Error Location 5,4 */
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#define REG_UMI_BCH_RD_ERR_LOC_5_4 __REG32(HW_UMI_BASE + 0x6c)
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/* BCH Read Error Location 7,6 */
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#define REG_UMI_BCH_RD_ERR_LOC_7_6 __REG32(HW_UMI_BASE + 0x70)
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/* BCH Read Error Location 9,8 */
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#define REG_UMI_BCH_RD_ERR_LOC_9_8 __REG32(HW_UMI_BASE + 0x74)
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/* BCH Read Error Location 11,10 */
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#define REG_UMI_BCH_RD_ERR_LOC_B_A __REG32(HW_UMI_BASE + 0x78)
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/* REG_UMI_FLASH0/1/2_TCR, REG_UMI_SRAM0/1_TCR bits */
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/* Enable wait pin during burst write or read */
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#define REG_UMI_TCR_WAITEN 0x80000000
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/* Enable mem ctrlr to work iwth ext mem of lower freq than AHB clk */
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#define REG_UMI_TCR_LOWFREQ 0x40000000
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/* 1=synch write, 0=async write */
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#define REG_UMI_TCR_MEMTYPE_SYNCWRITE 0x20000000
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/* 1=synch read, 0=async read */
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#define REG_UMI_TCR_MEMTYPE_SYNCREAD 0x10000000
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/* 1=page mode read, 0=normal mode read */
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#define REG_UMI_TCR_MEMTYPE_PAGEREAD 0x08000000
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/* page size/burst size (wrap only) */
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#define REG_UMI_TCR_MEMTYPE_PGSZ_MASK 0x07000000
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/* 4 word */
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#define REG_UMI_TCR_MEMTYPE_PGSZ_4 0x00000000
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/* 8 word */
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#define REG_UMI_TCR_MEMTYPE_PGSZ_8 0x01000000
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/* 16 word */
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#define REG_UMI_TCR_MEMTYPE_PGSZ_16 0x02000000
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/* 32 word */
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#define REG_UMI_TCR_MEMTYPE_PGSZ_32 0x03000000
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/* 64 word */
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#define REG_UMI_TCR_MEMTYPE_PGSZ_64 0x04000000
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/* 128 word */
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#define REG_UMI_TCR_MEMTYPE_PGSZ_128 0x05000000
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/* 256 word */
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#define REG_UMI_TCR_MEMTYPE_PGSZ_256 0x06000000
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/* 512 word */
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#define REG_UMI_TCR_MEMTYPE_PGSZ_512 0x07000000
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/* Page read access cycle / Burst write latency (n+2 / n+1) */
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#define REG_UMI_TCR_TPRC_TWLC_MASK 0x00f80000
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/* Bus turnaround cycle (n) */
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#define REG_UMI_TCR_TBTA_MASK 0x00070000
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/* Write pulse width cycle (n+1) */
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#define REG_UMI_TCR_TWP_MASK 0x0000f800
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/* Write recovery cycle (n+1) */
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#define REG_UMI_TCR_TWR_MASK 0x00000600
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/* Write address setup cycle (n+1) */
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#define REG_UMI_TCR_TAS_MASK 0x00000180
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/* Output enable delay cycle (n) */
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#define REG_UMI_TCR_TOE_MASK 0x00000060
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/* Read access cycle / Burst read latency (n+2 / n+1) */
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#define REG_UMI_TCR_TRC_TLC_MASK 0x0000001f
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/* REG_UMI_MMD_ICR bits */
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/* Flash write protection pin control */
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#define REG_UMI_MMD_ICR_FLASH_WP 0x8000
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/* Extend hold time for sram0, sram1 csn (39 MHz operation) */
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#define REG_UMI_MMD_ICR_XHCS 0x4000
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/* Enable SDRAM 2 interface control */
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#define REG_UMI_MMD_ICR_SDRAM2EN 0x2000
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/* Enable merge of flash banks 0/1 to 512 MBit bank */
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#define REG_UMI_MMD_ICR_INST512 0x1000
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/* Enable merge of flash banks 1/2 to 512 MBit bank */
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#define REG_UMI_MMD_ICR_DATA512 0x0800
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/* Enable SDRAM interface control */
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#define REG_UMI_MMD_ICR_SDRAMEN 0x0400
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/* Polarity of busy state of Burst Wait Signal */
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#define REG_UMI_MMD_ICR_WAITPOL 0x0200
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/* Enable burst clock stopped when not accessing external burst flash/sram */
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#define REG_UMI_MMD_ICR_BCLKSTOP 0x0100
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/* Enable the peri1_csn to replace flash1_csn in 512 Mb flash mode */
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#define REG_UMI_MMD_ICR_PERI1EN 0x0080
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/* Enable the peri2_csn to replace sdram_csn */
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#define REG_UMI_MMD_ICR_PERI2EN 0x0040
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/* Enable the peri3_csn to replace sdram2_csn */
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#define REG_UMI_MMD_ICR_PERI3EN 0x0020
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/* Enable sram bank1 for H/W controlled MRS */
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#define REG_UMI_MMD_ICR_MRSB1 0x0010
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/* Enable sram bank0 for H/W controlled MRS */
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#define REG_UMI_MMD_ICR_MRSB0 0x0008
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/* Polarity for assert3ed state of H/W controlled MRS */
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#define REG_UMI_MMD_ICR_MRSPOL 0x0004
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/* 0: S/W controllable ZZ/MRS/CRE/P-Mode pin */
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/* 1: H/W controlled ZZ/MRS/CRE/P-Mode, same timing as CS */
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#define REG_UMI_MMD_ICR_MRSMODE 0x0002
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/* MRS state for S/W controlled mode */
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#define REG_UMI_MMD_ICR_MRSSTATE 0x0001
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/* REG_UMI_NAND_TCR bits */
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/* Enable software to control CS */
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#define REG_UMI_NAND_TCR_CS_SWCTRL 0x80000000
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/* 16-bit nand wordsize if set */
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#define REG_UMI_NAND_TCR_WORD16 0x40000000
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/* Bus turnaround cycle (n) */
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#define REG_UMI_NAND_TCR_TBTA_MASK 0x00070000
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/* Write pulse width cycle (n+1) */
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#define REG_UMI_NAND_TCR_TWP_MASK 0x0000f800
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/* Write recovery cycle (n+1) */
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#define REG_UMI_NAND_TCR_TWR_MASK 0x00000600
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/* Write address setup cycle (n+1) */
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#define REG_UMI_NAND_TCR_TAS_MASK 0x00000180
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/* Output enable delay cycle (n) */
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#define REG_UMI_NAND_TCR_TOE_MASK 0x00000060
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/* Read access cycle (n+2) */
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#define REG_UMI_NAND_TCR_TRC_TLC_MASK 0x0000001f
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/* REG_UMI_NAND_RCSR bits */
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/* Status: Ready=1, Busy=0 */
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#define REG_UMI_NAND_RCSR_RDY 0x02
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/* Keep CS asserted during operation */
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#define REG_UMI_NAND_RCSR_CS_ASSERTED 0x01
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/* REG_UMI_NAND_ECC_CSR bits */
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/* Interrupt status - read-only */
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#define REG_UMI_NAND_ECC_CSR_NANDINT 0x80000000
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/* Read: Status of ECC done, Write: clear ECC interrupt */
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#define REG_UMI_NAND_ECC_CSR_ECCINT_RAW 0x00800000
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/* Read: Status of R/B, Write: clear R/B interrupt */
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#define REG_UMI_NAND_ECC_CSR_RBINT_RAW 0x00400000
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/* 1 = Enable ECC Interrupt */
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#define REG_UMI_NAND_ECC_CSR_ECCINT_ENABLE 0x00008000
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/* 1 = Assert interrupt at rising edge of R/B_ */
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#define REG_UMI_NAND_ECC_CSR_RBINT_ENABLE 0x00004000
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/* Calculate ECC by 0=512 bytes, 1=256 bytes */
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#define REG_UMI_NAND_ECC_CSR_256BYTE 0x00000080
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/* Enable ECC in hardware */
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#define REG_UMI_NAND_ECC_CSR_ECC_ENABLE 0x00000001
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/* REG_UMI_BCH_CTRL_STATUS bits */
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/* Shift to Indicate Number of correctable errors detected */
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#define REG_UMI_BCH_CTRL_STATUS_NB_CORR_ERROR_SHIFT 20
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/* Indicate Number of correctable errors detected */
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#define REG_UMI_BCH_CTRL_STATUS_NB_CORR_ERROR 0x00F00000
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/* Indicate Errors detected during read but uncorrectable */
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#define REG_UMI_BCH_CTRL_STATUS_UNCORR_ERR 0x00080000
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/* Indicate Errors detected during read and are correctable */
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#define REG_UMI_BCH_CTRL_STATUS_CORR_ERR 0x00040000
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/* Flag indicates BCH's ECC status of read process are valid */
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#define REG_UMI_BCH_CTRL_STATUS_RD_ECC_VALID 0x00020000
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/* Flag indicates BCH's ECC status of write process are valid */
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#define REG_UMI_BCH_CTRL_STATUS_WR_ECC_VALID 0x00010000
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/* Pause ECC calculation */
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#define REG_UMI_BCH_CTRL_STATUS_PAUSE_ECC_DEC 0x00000010
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/* Enable Interrupt */
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#define REG_UMI_BCH_CTRL_STATUS_INT_EN 0x00000004
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/* Enable ECC during read */
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#define REG_UMI_BCH_CTRL_STATUS_ECC_RD_EN 0x00000002
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/* Enable ECC during write */
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#define REG_UMI_BCH_CTRL_STATUS_ECC_WR_EN 0x00000001
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/* Mask for location */
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#define REG_UMI_BCH_ERR_LOC_MASK 0x00001FFF
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/* location within a byte */
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#define REG_UMI_BCH_ERR_LOC_BYTE 0x00000007
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/* location within a word */
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#define REG_UMI_BCH_ERR_LOC_WORD 0x00000018
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/* location within a page (512 byte) */
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#define REG_UMI_BCH_ERR_LOC_PAGE 0x00001FE0
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#define REG_UMI_BCH_ERR_LOC_ADDR(index) (__REG32(HW_UMI_BASE + 0x64 + (index / 2)*4) >> ((index % 2) * 16))
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#endif
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