591 lines
13 KiB
C
591 lines
13 KiB
C
/*
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* linux/arch/arm/mach-integrator/integrator_cp.c
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*
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* Copyright (C) 2003 Deep Blue Solutions Ltd
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License.
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*/
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#include <linux/types.h>
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#include <linux/kernel.h>
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#include <linux/init.h>
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#include <linux/list.h>
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#include <linux/platform_device.h>
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#include <linux/dma-mapping.h>
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#include <linux/slab.h>
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#include <linux/string.h>
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#include <linux/sysdev.h>
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#include <linux/amba/bus.h>
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#include <linux/amba/kmi.h>
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#include <linux/amba/clcd.h>
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#include <asm/hardware.h>
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#include <asm/io.h>
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#include <asm/irq.h>
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#include <asm/setup.h>
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#include <asm/mach-types.h>
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#include <asm/hardware/icst525.h>
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#include <asm/arch/cm.h>
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#include <asm/arch/lm.h>
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#include <asm/mach/arch.h>
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#include <asm/mach/flash.h>
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#include <asm/mach/irq.h>
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#include <asm/mach/mmc.h>
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#include <asm/mach/map.h>
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#include <asm/mach/time.h>
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#include "common.h"
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#include "clock.h"
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#define INTCP_PA_MMC_BASE 0x1c000000
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#define INTCP_PA_AACI_BASE 0x1d000000
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#define INTCP_PA_FLASH_BASE 0x24000000
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#define INTCP_FLASH_SIZE SZ_32M
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#define INTCP_PA_CLCD_BASE 0xc0000000
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#define INTCP_VA_CIC_BASE 0xf1000040
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#define INTCP_VA_PIC_BASE 0xf1400000
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#define INTCP_VA_SIC_BASE 0xfca00000
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#define INTCP_PA_ETH_BASE 0xc8000000
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#define INTCP_ETH_SIZE 0x10
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#define INTCP_VA_CTRL_BASE 0xfcb00000
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#define INTCP_FLASHPROG 0x04
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#define CINTEGRATOR_FLASHPROG_FLVPPEN (1 << 0)
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#define CINTEGRATOR_FLASHPROG_FLWREN (1 << 1)
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/*
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* Logical Physical
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* f1000000 10000000 Core module registers
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* f1100000 11000000 System controller registers
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* f1200000 12000000 EBI registers
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* f1300000 13000000 Counter/Timer
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* f1400000 14000000 Interrupt controller
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* f1600000 16000000 UART 0
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* f1700000 17000000 UART 1
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* f1a00000 1a000000 Debug LEDs
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* f1b00000 1b000000 GPIO
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*/
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static struct map_desc intcp_io_desc[] __initdata = {
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{
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.virtual = IO_ADDRESS(INTEGRATOR_HDR_BASE),
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.pfn = __phys_to_pfn(INTEGRATOR_HDR_BASE),
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.length = SZ_4K,
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.type = MT_DEVICE
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}, {
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.virtual = IO_ADDRESS(INTEGRATOR_SC_BASE),
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.pfn = __phys_to_pfn(INTEGRATOR_SC_BASE),
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.length = SZ_4K,
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.type = MT_DEVICE
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}, {
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.virtual = IO_ADDRESS(INTEGRATOR_EBI_BASE),
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.pfn = __phys_to_pfn(INTEGRATOR_EBI_BASE),
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.length = SZ_4K,
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.type = MT_DEVICE
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}, {
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.virtual = IO_ADDRESS(INTEGRATOR_CT_BASE),
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.pfn = __phys_to_pfn(INTEGRATOR_CT_BASE),
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.length = SZ_4K,
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.type = MT_DEVICE
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}, {
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.virtual = IO_ADDRESS(INTEGRATOR_IC_BASE),
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.pfn = __phys_to_pfn(INTEGRATOR_IC_BASE),
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.length = SZ_4K,
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.type = MT_DEVICE
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}, {
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.virtual = IO_ADDRESS(INTEGRATOR_UART0_BASE),
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.pfn = __phys_to_pfn(INTEGRATOR_UART0_BASE),
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.length = SZ_4K,
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.type = MT_DEVICE
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}, {
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.virtual = IO_ADDRESS(INTEGRATOR_UART1_BASE),
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.pfn = __phys_to_pfn(INTEGRATOR_UART1_BASE),
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.length = SZ_4K,
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.type = MT_DEVICE
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}, {
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.virtual = IO_ADDRESS(INTEGRATOR_DBG_BASE),
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.pfn = __phys_to_pfn(INTEGRATOR_DBG_BASE),
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.length = SZ_4K,
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.type = MT_DEVICE
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}, {
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.virtual = IO_ADDRESS(INTEGRATOR_GPIO_BASE),
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.pfn = __phys_to_pfn(INTEGRATOR_GPIO_BASE),
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.length = SZ_4K,
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.type = MT_DEVICE
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}, {
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.virtual = 0xfca00000,
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.pfn = __phys_to_pfn(0xca000000),
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.length = SZ_4K,
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.type = MT_DEVICE
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}, {
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.virtual = 0xfcb00000,
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.pfn = __phys_to_pfn(0xcb000000),
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.length = SZ_4K,
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.type = MT_DEVICE
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}
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};
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static void __init intcp_map_io(void)
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{
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iotable_init(intcp_io_desc, ARRAY_SIZE(intcp_io_desc));
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}
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#define cic_writel __raw_writel
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#define cic_readl __raw_readl
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#define pic_writel __raw_writel
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#define pic_readl __raw_readl
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#define sic_writel __raw_writel
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#define sic_readl __raw_readl
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static void cic_mask_irq(unsigned int irq)
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{
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irq -= IRQ_CIC_START;
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cic_writel(1 << irq, INTCP_VA_CIC_BASE + IRQ_ENABLE_CLEAR);
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}
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static void cic_unmask_irq(unsigned int irq)
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{
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irq -= IRQ_CIC_START;
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cic_writel(1 << irq, INTCP_VA_CIC_BASE + IRQ_ENABLE_SET);
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}
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static struct irq_chip cic_chip = {
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.name = "CIC",
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.ack = cic_mask_irq,
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.mask = cic_mask_irq,
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.unmask = cic_unmask_irq,
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};
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static void pic_mask_irq(unsigned int irq)
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{
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irq -= IRQ_PIC_START;
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pic_writel(1 << irq, INTCP_VA_PIC_BASE + IRQ_ENABLE_CLEAR);
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}
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static void pic_unmask_irq(unsigned int irq)
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{
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irq -= IRQ_PIC_START;
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pic_writel(1 << irq, INTCP_VA_PIC_BASE + IRQ_ENABLE_SET);
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}
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static struct irq_chip pic_chip = {
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.name = "PIC",
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.ack = pic_mask_irq,
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.mask = pic_mask_irq,
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.unmask = pic_unmask_irq,
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};
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static void sic_mask_irq(unsigned int irq)
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{
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irq -= IRQ_SIC_START;
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sic_writel(1 << irq, INTCP_VA_SIC_BASE + IRQ_ENABLE_CLEAR);
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}
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static void sic_unmask_irq(unsigned int irq)
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{
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irq -= IRQ_SIC_START;
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sic_writel(1 << irq, INTCP_VA_SIC_BASE + IRQ_ENABLE_SET);
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}
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static struct irq_chip sic_chip = {
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.name = "SIC",
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.ack = sic_mask_irq,
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.mask = sic_mask_irq,
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.unmask = sic_unmask_irq,
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};
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static void
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sic_handle_irq(unsigned int irq, struct irq_desc *desc)
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{
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unsigned long status = sic_readl(INTCP_VA_SIC_BASE + IRQ_STATUS);
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if (status == 0) {
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do_bad_IRQ(irq, desc);
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return;
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}
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do {
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irq = ffs(status) - 1;
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status &= ~(1 << irq);
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irq += IRQ_SIC_START;
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desc = irq_desc + irq;
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desc_handle_irq(irq, desc);
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} while (status);
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}
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static void __init intcp_init_irq(void)
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{
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unsigned int i;
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/*
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* Disable all interrupt sources
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*/
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pic_writel(0xffffffff, INTCP_VA_PIC_BASE + IRQ_ENABLE_CLEAR);
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pic_writel(0xffffffff, INTCP_VA_PIC_BASE + FIQ_ENABLE_CLEAR);
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for (i = IRQ_PIC_START; i <= IRQ_PIC_END; i++) {
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if (i == 11)
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i = 22;
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if (i == 29)
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break;
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set_irq_chip(i, &pic_chip);
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set_irq_handler(i, handle_level_irq);
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set_irq_flags(i, IRQF_VALID | IRQF_PROBE);
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}
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cic_writel(0xffffffff, INTCP_VA_CIC_BASE + IRQ_ENABLE_CLEAR);
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cic_writel(0xffffffff, INTCP_VA_CIC_BASE + FIQ_ENABLE_CLEAR);
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for (i = IRQ_CIC_START; i <= IRQ_CIC_END; i++) {
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set_irq_chip(i, &cic_chip);
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set_irq_handler(i, handle_level_irq);
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set_irq_flags(i, IRQF_VALID);
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}
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sic_writel(0x00000fff, INTCP_VA_SIC_BASE + IRQ_ENABLE_CLEAR);
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sic_writel(0x00000fff, INTCP_VA_SIC_BASE + FIQ_ENABLE_CLEAR);
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for (i = IRQ_SIC_START; i <= IRQ_SIC_END; i++) {
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set_irq_chip(i, &sic_chip);
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set_irq_handler(i, handle_level_irq);
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set_irq_flags(i, IRQF_VALID | IRQF_PROBE);
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}
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set_irq_chained_handler(IRQ_CP_CPPLDINT, sic_handle_irq);
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}
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/*
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* Clock handling
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*/
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#define CM_LOCK (IO_ADDRESS(INTEGRATOR_HDR_BASE)+INTEGRATOR_HDR_LOCK_OFFSET)
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#define CM_AUXOSC (IO_ADDRESS(INTEGRATOR_HDR_BASE)+0x1c)
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static const struct icst525_params cp_auxvco_params = {
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.ref = 24000,
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.vco_max = 320000,
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.vd_min = 8,
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.vd_max = 263,
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.rd_min = 3,
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.rd_max = 65,
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};
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static void cp_auxvco_set(struct clk *clk, struct icst525_vco vco)
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{
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u32 val;
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val = readl(CM_AUXOSC) & ~0x7ffff;
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val |= vco.v | (vco.r << 9) | (vco.s << 16);
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writel(0xa05f, CM_LOCK);
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writel(val, CM_AUXOSC);
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writel(0, CM_LOCK);
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}
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static struct clk cp_clcd_clk = {
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.name = "CLCDCLK",
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.params = &cp_auxvco_params,
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.setvco = cp_auxvco_set,
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};
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static struct clk cp_mmci_clk = {
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.name = "MCLK",
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.rate = 14745600,
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};
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/*
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* Flash handling.
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*/
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static int intcp_flash_init(void)
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{
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u32 val;
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val = readl(INTCP_VA_CTRL_BASE + INTCP_FLASHPROG);
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val |= CINTEGRATOR_FLASHPROG_FLWREN;
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writel(val, INTCP_VA_CTRL_BASE + INTCP_FLASHPROG);
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return 0;
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}
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static void intcp_flash_exit(void)
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{
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u32 val;
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val = readl(INTCP_VA_CTRL_BASE + INTCP_FLASHPROG);
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val &= ~(CINTEGRATOR_FLASHPROG_FLVPPEN|CINTEGRATOR_FLASHPROG_FLWREN);
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writel(val, INTCP_VA_CTRL_BASE + INTCP_FLASHPROG);
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}
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static void intcp_flash_set_vpp(int on)
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{
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u32 val;
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val = readl(INTCP_VA_CTRL_BASE + INTCP_FLASHPROG);
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if (on)
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val |= CINTEGRATOR_FLASHPROG_FLVPPEN;
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else
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val &= ~CINTEGRATOR_FLASHPROG_FLVPPEN;
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writel(val, INTCP_VA_CTRL_BASE + INTCP_FLASHPROG);
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}
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static struct flash_platform_data intcp_flash_data = {
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.map_name = "cfi_probe",
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.width = 4,
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.init = intcp_flash_init,
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.exit = intcp_flash_exit,
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.set_vpp = intcp_flash_set_vpp,
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};
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static struct resource intcp_flash_resource = {
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.start = INTCP_PA_FLASH_BASE,
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.end = INTCP_PA_FLASH_BASE + INTCP_FLASH_SIZE - 1,
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.flags = IORESOURCE_MEM,
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};
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static struct platform_device intcp_flash_device = {
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.name = "armflash",
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.id = 0,
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.dev = {
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.platform_data = &intcp_flash_data,
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},
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.num_resources = 1,
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.resource = &intcp_flash_resource,
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};
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static struct resource smc91x_resources[] = {
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[0] = {
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.start = INTCP_PA_ETH_BASE,
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.end = INTCP_PA_ETH_BASE + INTCP_ETH_SIZE - 1,
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.flags = IORESOURCE_MEM,
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},
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[1] = {
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.start = IRQ_CP_ETHINT,
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.end = IRQ_CP_ETHINT,
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.flags = IORESOURCE_IRQ,
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},
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};
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static struct platform_device smc91x_device = {
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.name = "smc91x",
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.id = 0,
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.num_resources = ARRAY_SIZE(smc91x_resources),
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.resource = smc91x_resources,
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};
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static struct platform_device *intcp_devs[] __initdata = {
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&intcp_flash_device,
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&smc91x_device,
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};
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/*
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* It seems that the card insertion interrupt remains active after
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* we've acknowledged it. We therefore ignore the interrupt, and
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* rely on reading it from the SIC. This also means that we must
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* clear the latched interrupt.
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*/
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static unsigned int mmc_status(struct device *dev)
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{
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unsigned int status = readl(0xfca00004);
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writel(8, 0xfcb00008);
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return status & 8;
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}
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static struct mmc_platform_data mmc_data = {
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.ocr_mask = MMC_VDD_32_33|MMC_VDD_33_34,
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.status = mmc_status,
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};
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static struct amba_device mmc_device = {
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.dev = {
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.bus_id = "mb:1c",
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.platform_data = &mmc_data,
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},
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.res = {
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.start = INTCP_PA_MMC_BASE,
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.end = INTCP_PA_MMC_BASE + SZ_4K - 1,
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.flags = IORESOURCE_MEM,
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},
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.irq = { IRQ_CP_MMCIINT0, IRQ_CP_MMCIINT1 },
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.periphid = 0,
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};
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static struct amba_device aaci_device = {
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.dev = {
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.bus_id = "mb:1d",
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},
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.res = {
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.start = INTCP_PA_AACI_BASE,
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.end = INTCP_PA_AACI_BASE + SZ_4K - 1,
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.flags = IORESOURCE_MEM,
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},
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.irq = { IRQ_CP_AACIINT, NO_IRQ },
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.periphid = 0,
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};
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/*
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* CLCD support
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*/
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static struct clcd_panel vga = {
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.mode = {
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.name = "VGA",
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.refresh = 60,
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.xres = 640,
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.yres = 480,
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.pixclock = 39721,
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.left_margin = 40,
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.right_margin = 24,
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.upper_margin = 32,
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.lower_margin = 11,
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.hsync_len = 96,
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.vsync_len = 2,
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.sync = 0,
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.vmode = FB_VMODE_NONINTERLACED,
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},
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.width = -1,
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.height = -1,
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.tim2 = TIM2_BCD | TIM2_IPC,
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.cntl = CNTL_LCDTFT | CNTL_LCDVCOMP(1),
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.bpp = 16,
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.grayscale = 0,
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};
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/*
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* Ensure VGA is selected.
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*/
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static void cp_clcd_enable(struct clcd_fb *fb)
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{
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u32 val;
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if (fb->fb.var.bits_per_pixel <= 8)
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val = CM_CTRL_LCDMUXSEL_VGA_8421BPP;
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else if (fb->fb.var.bits_per_pixel <= 16)
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val = CM_CTRL_LCDMUXSEL_VGA_16BPP
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| CM_CTRL_LCDEN0 | CM_CTRL_LCDEN1
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| CM_CTRL_STATIC1 | CM_CTRL_STATIC2;
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else
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val = 0; /* no idea for this, don't trust the docs */
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cm_control(CM_CTRL_LCDMUXSEL_MASK|
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CM_CTRL_LCDEN0|
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CM_CTRL_LCDEN1|
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CM_CTRL_STATIC1|
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CM_CTRL_STATIC2|
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CM_CTRL_STATIC|
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CM_CTRL_n24BITEN, val);
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}
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static unsigned long framesize = SZ_1M;
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static int cp_clcd_setup(struct clcd_fb *fb)
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{
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dma_addr_t dma;
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fb->panel = &vga;
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fb->fb.screen_base = dma_alloc_writecombine(&fb->dev->dev, framesize,
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&dma, GFP_KERNEL);
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if (!fb->fb.screen_base) {
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printk(KERN_ERR "CLCD: unable to map framebuffer\n");
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return -ENOMEM;
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}
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fb->fb.fix.smem_start = dma;
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fb->fb.fix.smem_len = framesize;
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int cp_clcd_mmap(struct clcd_fb *fb, struct vm_area_struct *vma)
|
|
{
|
|
return dma_mmap_writecombine(&fb->dev->dev, vma,
|
|
fb->fb.screen_base,
|
|
fb->fb.fix.smem_start,
|
|
fb->fb.fix.smem_len);
|
|
}
|
|
|
|
static void cp_clcd_remove(struct clcd_fb *fb)
|
|
{
|
|
dma_free_writecombine(&fb->dev->dev, fb->fb.fix.smem_len,
|
|
fb->fb.screen_base, fb->fb.fix.smem_start);
|
|
}
|
|
|
|
static struct clcd_board clcd_data = {
|
|
.name = "Integrator/CP",
|
|
.check = clcdfb_check,
|
|
.decode = clcdfb_decode,
|
|
.enable = cp_clcd_enable,
|
|
.setup = cp_clcd_setup,
|
|
.mmap = cp_clcd_mmap,
|
|
.remove = cp_clcd_remove,
|
|
};
|
|
|
|
static struct amba_device clcd_device = {
|
|
.dev = {
|
|
.bus_id = "mb:c0",
|
|
.coherent_dma_mask = ~0,
|
|
.platform_data = &clcd_data,
|
|
},
|
|
.res = {
|
|
.start = INTCP_PA_CLCD_BASE,
|
|
.end = INTCP_PA_CLCD_BASE + SZ_4K - 1,
|
|
.flags = IORESOURCE_MEM,
|
|
},
|
|
.dma_mask = ~0,
|
|
.irq = { IRQ_CP_CLCDCINT, NO_IRQ },
|
|
.periphid = 0,
|
|
};
|
|
|
|
static struct amba_device *amba_devs[] __initdata = {
|
|
&mmc_device,
|
|
&aaci_device,
|
|
&clcd_device,
|
|
};
|
|
|
|
static void __init intcp_init(void)
|
|
{
|
|
int i;
|
|
|
|
clk_register(&cp_clcd_clk);
|
|
clk_register(&cp_mmci_clk);
|
|
|
|
platform_add_devices(intcp_devs, ARRAY_SIZE(intcp_devs));
|
|
|
|
for (i = 0; i < ARRAY_SIZE(amba_devs); i++) {
|
|
struct amba_device *d = amba_devs[i];
|
|
amba_device_register(d, &iomem_resource);
|
|
}
|
|
}
|
|
|
|
#define TIMER_CTRL_IE (1 << 5) /* Interrupt Enable */
|
|
|
|
static void __init intcp_timer_init(void)
|
|
{
|
|
integrator_time_init(1000000 / HZ, TIMER_CTRL_IE);
|
|
}
|
|
|
|
static struct sys_timer cp_timer = {
|
|
.init = intcp_timer_init,
|
|
.offset = integrator_gettimeoffset,
|
|
};
|
|
|
|
MACHINE_START(CINTEGRATOR, "ARM-IntegratorCP")
|
|
/* Maintainer: ARM Ltd/Deep Blue Solutions Ltd */
|
|
.phys_io = 0x16000000,
|
|
.io_pg_offst = ((0xf1600000) >> 18) & 0xfffc,
|
|
.boot_params = 0x00000100,
|
|
.map_io = intcp_map_io,
|
|
.init_irq = intcp_init_irq,
|
|
.timer = &cp_timer,
|
|
.init_machine = intcp_init,
|
|
MACHINE_END
|