385 lines
9.5 KiB
C
385 lines
9.5 KiB
C
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/* linux/arch/arm/plat-s3c/pm-gpio.c
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*
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* Copyright 2008 Openmoko, Inc.
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* Copyright 2008 Simtec Electronics
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* Ben Dooks <ben@simtec.co.uk>
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* http://armlinux.simtec.co.uk/
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*
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* S3C series GPIO PM code
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#include <linux/kernel.h>
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#include <linux/sysdev.h>
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#include <linux/init.h>
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#include <linux/io.h>
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#include <linux/gpio.h>
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#include <plat/gpio-core.h>
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#include <plat/pm.h>
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/* PM GPIO helpers */
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#define OFFS_CON (0x00)
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#define OFFS_DAT (0x04)
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#define OFFS_UP (0x08)
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static void s3c_gpio_pm_1bit_save(struct s3c_gpio_chip *chip)
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{
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chip->pm_save[0] = __raw_readl(chip->base + OFFS_CON);
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chip->pm_save[1] = __raw_readl(chip->base + OFFS_DAT);
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}
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static void s3c_gpio_pm_1bit_resume(struct s3c_gpio_chip *chip)
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{
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void __iomem *base = chip->base;
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u32 old_gpcon = __raw_readl(base + OFFS_CON);
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u32 old_gpdat = __raw_readl(base + OFFS_DAT);
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u32 gps_gpcon = chip->pm_save[0];
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u32 gps_gpdat = chip->pm_save[1];
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u32 gpcon;
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/* GPACON only has one bit per control / data and no PULLUPs.
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* GPACON[x] = 0 => Output, 1 => SFN */
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/* first set all SFN bits to SFN */
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gpcon = old_gpcon | gps_gpcon;
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__raw_writel(gpcon, base + OFFS_CON);
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/* now set all the other bits */
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__raw_writel(gps_gpdat, base + OFFS_DAT);
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__raw_writel(gps_gpcon, base + OFFS_CON);
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S3C_PMDBG("%s: CON %08x => %08x, DAT %08x => %08x\n",
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chip->chip.label, old_gpcon, gps_gpcon, old_gpdat, gps_gpdat);
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}
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struct s3c_gpio_pm s3c_gpio_pm_1bit = {
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.save = s3c_gpio_pm_1bit_save,
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.resume = s3c_gpio_pm_1bit_resume,
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};
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static void s3c_gpio_pm_2bit_save(struct s3c_gpio_chip *chip)
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{
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chip->pm_save[0] = __raw_readl(chip->base + OFFS_CON);
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chip->pm_save[1] = __raw_readl(chip->base + OFFS_DAT);
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chip->pm_save[2] = __raw_readl(chip->base + OFFS_UP);
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}
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/* Test whether the given masked+shifted bits of an GPIO configuration
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* are one of the SFN (special function) modes. */
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static inline int is_sfn(unsigned long con)
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{
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return con >= 2;
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}
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/* Test if the given masked+shifted GPIO configuration is an input */
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static inline int is_in(unsigned long con)
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{
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return con == 0;
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}
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/* Test if the given masked+shifted GPIO configuration is an output */
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static inline int is_out(unsigned long con)
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{
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return con == 1;
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}
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/**
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* s3c_gpio_pm_2bit_resume() - restore the given GPIO bank
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* @chip: The chip information to resume.
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*
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* Restore one of the GPIO banks that was saved during suspend. This is
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* not as simple as once thought, due to the possibility of glitches
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* from the order that the CON and DAT registers are set in.
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*
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* The three states the pin can be are {IN,OUT,SFN} which gives us 9
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* combinations of changes to check. Three of these, if the pin stays
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* in the same configuration can be discounted. This leaves us with
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* the following:
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*
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* { IN => OUT } Change DAT first
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* { IN => SFN } Change CON first
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* { OUT => SFN } Change CON first, so new data will not glitch
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* { OUT => IN } Change CON first, so new data will not glitch
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* { SFN => IN } Change CON first
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* { SFN => OUT } Change DAT first, so new data will not glitch [1]
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*
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* We do not currently deal with the UP registers as these control
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* weak resistors, so a small delay in change should not need to bring
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* these into the calculations.
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*
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* [1] this assumes that writing to a pin DAT whilst in SFN will set the
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* state for when it is next output.
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*/
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static void s3c_gpio_pm_2bit_resume(struct s3c_gpio_chip *chip)
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{
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void __iomem *base = chip->base;
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u32 old_gpcon = __raw_readl(base + OFFS_CON);
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u32 old_gpdat = __raw_readl(base + OFFS_DAT);
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u32 gps_gpcon = chip->pm_save[0];
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u32 gps_gpdat = chip->pm_save[1];
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u32 gpcon, old, new, mask;
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u32 change_mask = 0x0;
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int nr;
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/* restore GPIO pull-up settings */
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__raw_writel(chip->pm_save[2], base + OFFS_UP);
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/* Create a change_mask of all the items that need to have
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* their CON value changed before their DAT value, so that
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* we minimise the work between the two settings.
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*/
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for (nr = 0, mask = 0x03; nr < 32; nr += 2, mask <<= 2) {
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old = (old_gpcon & mask) >> nr;
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new = (gps_gpcon & mask) >> nr;
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/* If there is no change, then skip */
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if (old == new)
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continue;
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/* If both are special function, then skip */
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if (is_sfn(old) && is_sfn(new))
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continue;
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/* Change is IN => OUT, do not change now */
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if (is_in(old) && is_out(new))
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continue;
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/* Change is SFN => OUT, do not change now */
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if (is_sfn(old) && is_out(new))
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continue;
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/* We should now be at the case of IN=>SFN,
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* OUT=>SFN, OUT=>IN, SFN=>IN. */
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change_mask |= mask;
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}
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/* Write the new CON settings */
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gpcon = old_gpcon & ~change_mask;
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gpcon |= gps_gpcon & change_mask;
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__raw_writel(gpcon, base + OFFS_CON);
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/* Now change any items that require DAT,CON */
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__raw_writel(gps_gpdat, base + OFFS_DAT);
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__raw_writel(gps_gpcon, base + OFFS_CON);
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S3C_PMDBG("%s: CON %08x => %08x, DAT %08x => %08x\n",
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chip->chip.label, old_gpcon, gps_gpcon, old_gpdat, gps_gpdat);
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}
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struct s3c_gpio_pm s3c_gpio_pm_2bit = {
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.save = s3c_gpio_pm_2bit_save,
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.resume = s3c_gpio_pm_2bit_resume,
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};
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#ifdef CONFIG_ARCH_S3C64XX
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static void s3c_gpio_pm_4bit_save(struct s3c_gpio_chip *chip)
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{
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chip->pm_save[1] = __raw_readl(chip->base + OFFS_CON);
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chip->pm_save[2] = __raw_readl(chip->base + OFFS_DAT);
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chip->pm_save[3] = __raw_readl(chip->base + OFFS_UP);
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if (chip->chip.ngpio > 8)
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chip->pm_save[0] = __raw_readl(chip->base - 4);
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}
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static u32 s3c_gpio_pm_4bit_mask(u32 old_gpcon, u32 gps_gpcon)
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{
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u32 old, new, mask;
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u32 change_mask = 0x0;
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int nr;
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for (nr = 0, mask = 0x0f; nr < 16; nr += 4, mask <<= 4) {
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old = (old_gpcon & mask) >> nr;
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new = (gps_gpcon & mask) >> nr;
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/* If there is no change, then skip */
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if (old == new)
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continue;
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/* If both are special function, then skip */
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if (is_sfn(old) && is_sfn(new))
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continue;
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/* Change is IN => OUT, do not change now */
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if (is_in(old) && is_out(new))
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continue;
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/* Change is SFN => OUT, do not change now */
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if (is_sfn(old) && is_out(new))
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continue;
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/* We should now be at the case of IN=>SFN,
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* OUT=>SFN, OUT=>IN, SFN=>IN. */
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change_mask |= mask;
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}
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return change_mask;
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}
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static void s3c_gpio_pm_4bit_con(struct s3c_gpio_chip *chip, int index)
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{
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void __iomem *con = chip->base + (index * 4);
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u32 old_gpcon = __raw_readl(con);
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u32 gps_gpcon = chip->pm_save[index + 1];
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u32 gpcon, mask;
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mask = s3c_gpio_pm_4bit_mask(old_gpcon, gps_gpcon);
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gpcon = old_gpcon & ~mask;
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gpcon |= gps_gpcon & mask;
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__raw_writel(gpcon, con);
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}
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static void s3c_gpio_pm_4bit_resume(struct s3c_gpio_chip *chip)
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{
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void __iomem *base = chip->base;
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u32 old_gpcon[2];
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u32 old_gpdat = __raw_readl(base + OFFS_DAT);
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u32 gps_gpdat = chip->pm_save[2];
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/* First, modify the CON settings */
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old_gpcon[0] = 0;
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old_gpcon[1] = __raw_readl(base + OFFS_CON);
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s3c_gpio_pm_4bit_con(chip, 0);
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if (chip->chip.ngpio > 8) {
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old_gpcon[0] = __raw_readl(base - 4);
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s3c_gpio_pm_4bit_con(chip, -1);
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}
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/* Now change the configurations that require DAT,CON */
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__raw_writel(chip->pm_save[2], base + OFFS_DAT);
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__raw_writel(chip->pm_save[1], base + OFFS_CON);
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if (chip->chip.ngpio > 8)
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__raw_writel(chip->pm_save[0], base - 4);
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__raw_writel(chip->pm_save[2], base + OFFS_DAT);
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__raw_writel(chip->pm_save[3], base + OFFS_UP);
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if (chip->chip.ngpio > 8) {
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S3C_PMDBG("%s: CON4 %08x,%08x => %08x,%08x, DAT %08x => %08x\n",
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chip->chip.label, old_gpcon[0], old_gpcon[1],
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__raw_readl(base - 4),
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__raw_readl(base + OFFS_CON),
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old_gpdat, gps_gpdat);
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} else
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S3C_PMDBG("%s: CON4 %08x => %08x, DAT %08x => %08x\n",
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chip->chip.label, old_gpcon[1],
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__raw_readl(base + OFFS_CON),
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old_gpdat, gps_gpdat);
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}
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struct s3c_gpio_pm s3c_gpio_pm_4bit = {
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.save = s3c_gpio_pm_4bit_save,
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.resume = s3c_gpio_pm_4bit_resume,
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};
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#endif /* CONFIG_ARCH_S3C64XX */
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/**
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* s3c_pm_save_gpio() - save gpio chip data for suspend
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* @ourchip: The chip for suspend.
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*/
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static void s3c_pm_save_gpio(struct s3c_gpio_chip *ourchip)
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{
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struct s3c_gpio_pm *pm = ourchip->pm;
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if (pm == NULL || pm->save == NULL)
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S3C_PMDBG("%s: no pm for %s\n", __func__, ourchip->chip.label);
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else
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pm->save(ourchip);
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}
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/**
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* s3c_pm_save_gpios() - Save the state of the GPIO banks.
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*
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* For all the GPIO banks, save the state of each one ready for going
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* into a suspend mode.
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*/
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void s3c_pm_save_gpios(void)
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{
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struct s3c_gpio_chip *ourchip;
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unsigned int gpio_nr;
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for (gpio_nr = 0; gpio_nr < S3C_GPIO_END;) {
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ourchip = s3c_gpiolib_getchip(gpio_nr);
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if (!ourchip) {
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gpio_nr++;
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continue;
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}
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s3c_pm_save_gpio(ourchip);
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S3C_PMDBG("%s: save %08x,%08x,%08x,%08x\n",
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ourchip->chip.label,
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ourchip->pm_save[0],
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ourchip->pm_save[1],
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ourchip->pm_save[2],
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ourchip->pm_save[3]);
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gpio_nr += ourchip->chip.ngpio;
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gpio_nr += CONFIG_S3C_GPIO_SPACE;
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}
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}
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/**
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* s3c_pm_resume_gpio() - restore gpio chip data after suspend
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* @ourchip: The suspended chip.
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*/
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static void s3c_pm_resume_gpio(struct s3c_gpio_chip *ourchip)
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{
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struct s3c_gpio_pm *pm = ourchip->pm;
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if (pm == NULL || pm->resume == NULL)
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S3C_PMDBG("%s: no pm for %s\n", __func__, ourchip->chip.label);
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else
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pm->resume(ourchip);
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}
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void s3c_pm_restore_gpios(void)
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{
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struct s3c_gpio_chip *ourchip;
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unsigned int gpio_nr;
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for (gpio_nr = 0; gpio_nr < S3C_GPIO_END;) {
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ourchip = s3c_gpiolib_getchip(gpio_nr);
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if (!ourchip) {
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gpio_nr++;
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continue;
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}
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s3c_pm_resume_gpio(ourchip);
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gpio_nr += ourchip->chip.ngpio;
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gpio_nr += CONFIG_S3C_GPIO_SPACE;
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}
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}
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