471 lines
10 KiB
C
471 lines
10 KiB
C
/*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*
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* Copyright (C) 1996, 97, 2000, 2001 by Ralf Baechle
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* Copyright (C) 2001 MIPS Technologies, Inc.
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*/
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#include <linux/kernel.h>
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#include <linux/sched.h>
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#include <linux/signal.h>
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#include <linux/module.h>
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#include <asm/branch.h>
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#include <asm/cpu.h>
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#include <asm/cpu-features.h>
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#include <asm/fpu.h>
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#include <asm/fpu_emulator.h>
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#include <asm/inst.h>
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#include <asm/ptrace.h>
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#include <asm/uaccess.h>
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/*
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* Calculate and return exception PC in case of branch delay slot
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* for microMIPS and MIPS16e. It does not clear the ISA mode bit.
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*/
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int __isa_exception_epc(struct pt_regs *regs)
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{
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unsigned short inst;
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long epc = regs->cp0_epc;
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/* Calculate exception PC in branch delay slot. */
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if (__get_user(inst, (u16 __user *) msk_isa16_mode(epc))) {
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/* This should never happen because delay slot was checked. */
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force_sig(SIGSEGV, current);
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return epc;
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}
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if (cpu_has_mips16) {
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if (((union mips16e_instruction)inst).ri.opcode
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== MIPS16e_jal_op)
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epc += 4;
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else
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epc += 2;
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} else if (mm_insn_16bit(inst))
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epc += 2;
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else
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epc += 4;
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return epc;
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}
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/*
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* Compute return address and emulate branch in microMIPS mode after an
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* exception only. It does not handle compact branches/jumps and cannot
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* be used in interrupt context. (Compact branches/jumps do not cause
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* exceptions.)
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*/
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int __microMIPS_compute_return_epc(struct pt_regs *regs)
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{
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u16 __user *pc16;
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u16 halfword;
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unsigned int word;
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unsigned long contpc;
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struct mm_decoded_insn mminsn = { 0 };
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mminsn.micro_mips_mode = 1;
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/* This load never faults. */
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pc16 = (unsigned short __user *)msk_isa16_mode(regs->cp0_epc);
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__get_user(halfword, pc16);
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pc16++;
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contpc = regs->cp0_epc + 2;
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word = ((unsigned int)halfword << 16);
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mminsn.pc_inc = 2;
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if (!mm_insn_16bit(halfword)) {
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__get_user(halfword, pc16);
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pc16++;
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contpc = regs->cp0_epc + 4;
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mminsn.pc_inc = 4;
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word |= halfword;
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}
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mminsn.insn = word;
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if (get_user(halfword, pc16))
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goto sigsegv;
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mminsn.next_pc_inc = 2;
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word = ((unsigned int)halfword << 16);
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if (!mm_insn_16bit(halfword)) {
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pc16++;
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if (get_user(halfword, pc16))
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goto sigsegv;
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mminsn.next_pc_inc = 4;
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word |= halfword;
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}
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mminsn.next_insn = word;
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mm_isBranchInstr(regs, mminsn, &contpc);
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regs->cp0_epc = contpc;
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return 0;
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sigsegv:
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force_sig(SIGSEGV, current);
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return -EFAULT;
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}
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/*
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* Compute return address and emulate branch in MIPS16e mode after an
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* exception only. It does not handle compact branches/jumps and cannot
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* be used in interrupt context. (Compact branches/jumps do not cause
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* exceptions.)
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*/
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int __MIPS16e_compute_return_epc(struct pt_regs *regs)
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{
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u16 __user *addr;
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union mips16e_instruction inst;
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u16 inst2;
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u32 fullinst;
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long epc;
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epc = regs->cp0_epc;
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/* Read the instruction. */
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addr = (u16 __user *)msk_isa16_mode(epc);
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if (__get_user(inst.full, addr)) {
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force_sig(SIGSEGV, current);
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return -EFAULT;
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}
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switch (inst.ri.opcode) {
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case MIPS16e_extend_op:
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regs->cp0_epc += 4;
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return 0;
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/*
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* JAL and JALX in MIPS16e mode
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*/
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case MIPS16e_jal_op:
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addr += 1;
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if (__get_user(inst2, addr)) {
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force_sig(SIGSEGV, current);
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return -EFAULT;
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}
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fullinst = ((unsigned)inst.full << 16) | inst2;
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regs->regs[31] = epc + 6;
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epc += 4;
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epc >>= 28;
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epc <<= 28;
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/*
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* JAL:5 X:1 TARGET[20-16]:5 TARGET[25:21]:5 TARGET[15:0]:16
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*
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* ......TARGET[15:0].................TARGET[20:16]...........
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* ......TARGET[25:21]
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*/
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epc |=
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((fullinst & 0xffff) << 2) | ((fullinst & 0x3e00000) >> 3) |
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((fullinst & 0x1f0000) << 7);
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if (!inst.jal.x)
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set_isa16_mode(epc); /* Set ISA mode bit. */
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regs->cp0_epc = epc;
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return 0;
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/*
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* J(AL)R(C)
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*/
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case MIPS16e_rr_op:
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if (inst.rr.func == MIPS16e_jr_func) {
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if (inst.rr.ra)
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regs->cp0_epc = regs->regs[31];
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else
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regs->cp0_epc =
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regs->regs[reg16to32[inst.rr.rx]];
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if (inst.rr.l) {
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if (inst.rr.nd)
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regs->regs[31] = epc + 2;
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else
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regs->regs[31] = epc + 4;
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}
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return 0;
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}
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break;
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}
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/*
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* All other cases have no branch delay slot and are 16-bits.
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* Branches do not cause an exception.
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*/
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regs->cp0_epc += 2;
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return 0;
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}
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/**
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* __compute_return_epc_for_insn - Computes the return address and do emulate
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* branch simulation, if required.
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*
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* @regs: Pointer to pt_regs
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* @insn: branch instruction to decode
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* @returns: -EFAULT on error and forces SIGBUS, and on success
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* returns 0 or BRANCH_LIKELY_TAKEN as appropriate after
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* evaluating the branch.
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*/
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int __compute_return_epc_for_insn(struct pt_regs *regs,
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union mips_instruction insn)
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{
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unsigned int bit, fcr31, dspcontrol;
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long epc = regs->cp0_epc;
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int ret = 0;
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switch (insn.i_format.opcode) {
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/*
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* jr and jalr are in r_format format.
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*/
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case spec_op:
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switch (insn.r_format.func) {
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case jalr_op:
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regs->regs[insn.r_format.rd] = epc + 8;
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/* Fall through */
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case jr_op:
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regs->cp0_epc = regs->regs[insn.r_format.rs];
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break;
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}
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break;
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/*
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* This group contains:
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* bltz_op, bgez_op, bltzl_op, bgezl_op,
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* bltzal_op, bgezal_op, bltzall_op, bgezall_op.
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*/
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case bcond_op:
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switch (insn.i_format.rt) {
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case bltz_op:
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case bltzl_op:
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if ((long)regs->regs[insn.i_format.rs] < 0) {
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epc = epc + 4 + (insn.i_format.simmediate << 2);
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if (insn.i_format.rt == bltzl_op)
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ret = BRANCH_LIKELY_TAKEN;
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} else
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epc += 8;
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regs->cp0_epc = epc;
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break;
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case bgez_op:
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case bgezl_op:
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if ((long)regs->regs[insn.i_format.rs] >= 0) {
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epc = epc + 4 + (insn.i_format.simmediate << 2);
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if (insn.i_format.rt == bgezl_op)
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ret = BRANCH_LIKELY_TAKEN;
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} else
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epc += 8;
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regs->cp0_epc = epc;
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break;
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case bltzal_op:
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case bltzall_op:
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regs->regs[31] = epc + 8;
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if ((long)regs->regs[insn.i_format.rs] < 0) {
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epc = epc + 4 + (insn.i_format.simmediate << 2);
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if (insn.i_format.rt == bltzall_op)
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ret = BRANCH_LIKELY_TAKEN;
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} else
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epc += 8;
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regs->cp0_epc = epc;
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break;
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case bgezal_op:
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case bgezall_op:
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regs->regs[31] = epc + 8;
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if ((long)regs->regs[insn.i_format.rs] >= 0) {
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epc = epc + 4 + (insn.i_format.simmediate << 2);
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if (insn.i_format.rt == bgezall_op)
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ret = BRANCH_LIKELY_TAKEN;
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} else
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epc += 8;
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regs->cp0_epc = epc;
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break;
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case bposge32_op:
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if (!cpu_has_dsp)
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goto sigill;
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dspcontrol = rddsp(0x01);
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if (dspcontrol >= 32) {
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epc = epc + 4 + (insn.i_format.simmediate << 2);
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} else
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epc += 8;
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regs->cp0_epc = epc;
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break;
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}
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break;
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/*
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* These are unconditional and in j_format.
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*/
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case jal_op:
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regs->regs[31] = regs->cp0_epc + 8;
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case j_op:
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epc += 4;
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epc >>= 28;
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epc <<= 28;
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epc |= (insn.j_format.target << 2);
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regs->cp0_epc = epc;
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if (insn.i_format.opcode == jalx_op)
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set_isa16_mode(regs->cp0_epc);
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break;
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/*
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* These are conditional and in i_format.
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*/
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case beq_op:
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case beql_op:
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if (regs->regs[insn.i_format.rs] ==
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regs->regs[insn.i_format.rt]) {
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epc = epc + 4 + (insn.i_format.simmediate << 2);
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if (insn.i_format.rt == beql_op)
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ret = BRANCH_LIKELY_TAKEN;
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} else
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epc += 8;
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regs->cp0_epc = epc;
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break;
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case bne_op:
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case bnel_op:
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if (regs->regs[insn.i_format.rs] !=
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regs->regs[insn.i_format.rt]) {
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epc = epc + 4 + (insn.i_format.simmediate << 2);
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if (insn.i_format.rt == bnel_op)
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ret = BRANCH_LIKELY_TAKEN;
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} else
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epc += 8;
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regs->cp0_epc = epc;
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break;
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case blez_op: /* not really i_format */
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case blezl_op:
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/* rt field assumed to be zero */
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if ((long)regs->regs[insn.i_format.rs] <= 0) {
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epc = epc + 4 + (insn.i_format.simmediate << 2);
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if (insn.i_format.rt == bnel_op)
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ret = BRANCH_LIKELY_TAKEN;
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} else
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epc += 8;
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regs->cp0_epc = epc;
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break;
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case bgtz_op:
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case bgtzl_op:
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/* rt field assumed to be zero */
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if ((long)regs->regs[insn.i_format.rs] > 0) {
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epc = epc + 4 + (insn.i_format.simmediate << 2);
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if (insn.i_format.rt == bnel_op)
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ret = BRANCH_LIKELY_TAKEN;
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} else
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epc += 8;
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regs->cp0_epc = epc;
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break;
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/*
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* And now the FPA/cp1 branch instructions.
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*/
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case cop1_op:
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preempt_disable();
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if (is_fpu_owner())
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asm volatile("cfc1\t%0,$31" : "=r" (fcr31));
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else
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fcr31 = current->thread.fpu.fcr31;
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preempt_enable();
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bit = (insn.i_format.rt >> 2);
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bit += (bit != 0);
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bit += 23;
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switch (insn.i_format.rt & 3) {
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case 0: /* bc1f */
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case 2: /* bc1fl */
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if (~fcr31 & (1 << bit)) {
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epc = epc + 4 + (insn.i_format.simmediate << 2);
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if (insn.i_format.rt == 2)
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ret = BRANCH_LIKELY_TAKEN;
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} else
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epc += 8;
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regs->cp0_epc = epc;
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break;
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case 1: /* bc1t */
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case 3: /* bc1tl */
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if (fcr31 & (1 << bit)) {
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epc = epc + 4 + (insn.i_format.simmediate << 2);
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if (insn.i_format.rt == 3)
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ret = BRANCH_LIKELY_TAKEN;
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} else
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epc += 8;
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regs->cp0_epc = epc;
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break;
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}
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break;
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#ifdef CONFIG_CPU_CAVIUM_OCTEON
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case lwc2_op: /* This is bbit0 on Octeon */
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if ((regs->regs[insn.i_format.rs] & (1ull<<insn.i_format.rt))
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== 0)
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epc = epc + 4 + (insn.i_format.simmediate << 2);
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else
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epc += 8;
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regs->cp0_epc = epc;
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break;
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case ldc2_op: /* This is bbit032 on Octeon */
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if ((regs->regs[insn.i_format.rs] &
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(1ull<<(insn.i_format.rt+32))) == 0)
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epc = epc + 4 + (insn.i_format.simmediate << 2);
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else
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epc += 8;
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regs->cp0_epc = epc;
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break;
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case swc2_op: /* This is bbit1 on Octeon */
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if (regs->regs[insn.i_format.rs] & (1ull<<insn.i_format.rt))
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epc = epc + 4 + (insn.i_format.simmediate << 2);
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else
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epc += 8;
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regs->cp0_epc = epc;
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break;
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case sdc2_op: /* This is bbit132 on Octeon */
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if (regs->regs[insn.i_format.rs] &
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(1ull<<(insn.i_format.rt+32)))
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epc = epc + 4 + (insn.i_format.simmediate << 2);
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else
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epc += 8;
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regs->cp0_epc = epc;
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break;
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#endif
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}
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return ret;
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sigill:
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printk("%s: DSP branch but not DSP ASE - sending SIGBUS.\n", current->comm);
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force_sig(SIGBUS, current);
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return -EFAULT;
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}
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EXPORT_SYMBOL_GPL(__compute_return_epc_for_insn);
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int __compute_return_epc(struct pt_regs *regs)
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{
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unsigned int __user *addr;
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long epc;
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union mips_instruction insn;
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epc = regs->cp0_epc;
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if (epc & 3)
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goto unaligned;
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/*
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* Read the instruction
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*/
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addr = (unsigned int __user *) epc;
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if (__get_user(insn.word, addr)) {
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force_sig(SIGSEGV, current);
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return -EFAULT;
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}
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return __compute_return_epc_for_insn(regs, insn);
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unaligned:
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printk("%s: unaligned epc - sending SIGBUS.\n", current->comm);
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force_sig(SIGBUS, current);
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return -EFAULT;
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}
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