630 lines
16 KiB
C
630 lines
16 KiB
C
/* Copyright (c) 2010,2015, The Linux Foundation. All rights reserved.
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* Copyright (C) 2015 Linaro Ltd.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 and
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* only version 2 as published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
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* 02110-1301, USA.
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*/
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#include <linux/slab.h>
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#include <linux/io.h>
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#include <linux/module.h>
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#include <linux/mutex.h>
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#include <linux/errno.h>
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#include <linux/err.h>
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#include <linux/qcom_scm.h>
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#include <linux/dma-mapping.h>
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#include "qcom_scm.h"
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#define QCOM_SCM_FLAG_COLDBOOT_CPU0 0x00
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#define QCOM_SCM_FLAG_COLDBOOT_CPU1 0x01
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#define QCOM_SCM_FLAG_COLDBOOT_CPU2 0x08
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#define QCOM_SCM_FLAG_COLDBOOT_CPU3 0x20
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#define QCOM_SCM_FLAG_WARMBOOT_CPU0 0x04
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#define QCOM_SCM_FLAG_WARMBOOT_CPU1 0x02
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#define QCOM_SCM_FLAG_WARMBOOT_CPU2 0x10
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#define QCOM_SCM_FLAG_WARMBOOT_CPU3 0x40
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struct qcom_scm_entry {
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int flag;
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void *entry;
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};
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static struct qcom_scm_entry qcom_scm_wb[] = {
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{ .flag = QCOM_SCM_FLAG_WARMBOOT_CPU0 },
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{ .flag = QCOM_SCM_FLAG_WARMBOOT_CPU1 },
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{ .flag = QCOM_SCM_FLAG_WARMBOOT_CPU2 },
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{ .flag = QCOM_SCM_FLAG_WARMBOOT_CPU3 },
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};
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static DEFINE_MUTEX(qcom_scm_lock);
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/**
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* struct qcom_scm_command - one SCM command buffer
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* @len: total available memory for command and response
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* @buf_offset: start of command buffer
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* @resp_hdr_offset: start of response buffer
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* @id: command to be executed
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* @buf: buffer returned from qcom_scm_get_command_buffer()
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*
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* An SCM command is laid out in memory as follows:
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*
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* ------------------- <--- struct qcom_scm_command
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* | command header |
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* ------------------- <--- qcom_scm_get_command_buffer()
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* | command buffer |
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* ------------------- <--- struct qcom_scm_response and
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* | response header | qcom_scm_command_to_response()
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* ------------------- <--- qcom_scm_get_response_buffer()
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* | response buffer |
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* -------------------
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*
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* There can be arbitrary padding between the headers and buffers so
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* you should always use the appropriate qcom_scm_get_*_buffer() routines
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* to access the buffers in a safe manner.
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*/
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struct qcom_scm_command {
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__le32 len;
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__le32 buf_offset;
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__le32 resp_hdr_offset;
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__le32 id;
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__le32 buf[0];
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};
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/**
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* struct qcom_scm_response - one SCM response buffer
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* @len: total available memory for response
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* @buf_offset: start of response data relative to start of qcom_scm_response
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* @is_complete: indicates if the command has finished processing
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*/
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struct qcom_scm_response {
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__le32 len;
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__le32 buf_offset;
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__le32 is_complete;
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};
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/**
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* qcom_scm_command_to_response() - Get a pointer to a qcom_scm_response
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* @cmd: command
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*
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* Returns a pointer to a response for a command.
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*/
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static inline struct qcom_scm_response *qcom_scm_command_to_response(
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const struct qcom_scm_command *cmd)
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{
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return (void *)cmd + le32_to_cpu(cmd->resp_hdr_offset);
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}
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/**
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* qcom_scm_get_command_buffer() - Get a pointer to a command buffer
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* @cmd: command
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*
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* Returns a pointer to the command buffer of a command.
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*/
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static inline void *qcom_scm_get_command_buffer(const struct qcom_scm_command *cmd)
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{
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return (void *)cmd->buf;
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}
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/**
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* qcom_scm_get_response_buffer() - Get a pointer to a response buffer
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* @rsp: response
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*
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* Returns a pointer to a response buffer of a response.
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*/
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static inline void *qcom_scm_get_response_buffer(const struct qcom_scm_response *rsp)
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{
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return (void *)rsp + le32_to_cpu(rsp->buf_offset);
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}
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static u32 smc(u32 cmd_addr)
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{
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int context_id;
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register u32 r0 asm("r0") = 1;
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register u32 r1 asm("r1") = (u32)&context_id;
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register u32 r2 asm("r2") = cmd_addr;
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do {
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asm volatile(
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__asmeq("%0", "r0")
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__asmeq("%1", "r0")
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__asmeq("%2", "r1")
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__asmeq("%3", "r2")
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#ifdef REQUIRES_SEC
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".arch_extension sec\n"
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#endif
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"smc #0 @ switch to secure world\n"
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: "=r" (r0)
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: "r" (r0), "r" (r1), "r" (r2)
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: "r3", "r12");
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} while (r0 == QCOM_SCM_INTERRUPTED);
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return r0;
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}
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/**
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* qcom_scm_call() - Send an SCM command
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* @dev: struct device
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* @svc_id: service identifier
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* @cmd_id: command identifier
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* @cmd_buf: command buffer
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* @cmd_len: length of the command buffer
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* @resp_buf: response buffer
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* @resp_len: length of the response buffer
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*
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* Sends a command to the SCM and waits for the command to finish processing.
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*
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* A note on cache maintenance:
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* Note that any buffers that are expected to be accessed by the secure world
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* must be flushed before invoking qcom_scm_call and invalidated in the cache
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* immediately after qcom_scm_call returns. Cache maintenance on the command
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* and response buffers is taken care of by qcom_scm_call; however, callers are
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* responsible for any other cached buffers passed over to the secure world.
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*/
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static int qcom_scm_call(struct device *dev, u32 svc_id, u32 cmd_id,
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const void *cmd_buf, size_t cmd_len, void *resp_buf,
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size_t resp_len)
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{
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int ret;
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struct qcom_scm_command *cmd;
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struct qcom_scm_response *rsp;
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size_t alloc_len = sizeof(*cmd) + cmd_len + sizeof(*rsp) + resp_len;
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dma_addr_t cmd_phys;
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cmd = kzalloc(PAGE_ALIGN(alloc_len), GFP_KERNEL);
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if (!cmd)
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return -ENOMEM;
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cmd->len = cpu_to_le32(alloc_len);
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cmd->buf_offset = cpu_to_le32(sizeof(*cmd));
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cmd->resp_hdr_offset = cpu_to_le32(sizeof(*cmd) + cmd_len);
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cmd->id = cpu_to_le32((svc_id << 10) | cmd_id);
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if (cmd_buf)
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memcpy(qcom_scm_get_command_buffer(cmd), cmd_buf, cmd_len);
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rsp = qcom_scm_command_to_response(cmd);
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cmd_phys = dma_map_single(dev, cmd, alloc_len, DMA_TO_DEVICE);
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if (dma_mapping_error(dev, cmd_phys)) {
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kfree(cmd);
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return -ENOMEM;
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}
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mutex_lock(&qcom_scm_lock);
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ret = smc(cmd_phys);
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if (ret < 0)
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ret = qcom_scm_remap_error(ret);
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mutex_unlock(&qcom_scm_lock);
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if (ret)
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goto out;
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do {
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dma_sync_single_for_cpu(dev, cmd_phys + sizeof(*cmd) + cmd_len,
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sizeof(*rsp), DMA_FROM_DEVICE);
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} while (!rsp->is_complete);
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if (resp_buf) {
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dma_sync_single_for_cpu(dev, cmd_phys + sizeof(*cmd) + cmd_len +
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le32_to_cpu(rsp->buf_offset),
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resp_len, DMA_FROM_DEVICE);
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memcpy(resp_buf, qcom_scm_get_response_buffer(rsp),
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resp_len);
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}
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out:
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dma_unmap_single(dev, cmd_phys, alloc_len, DMA_TO_DEVICE);
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kfree(cmd);
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return ret;
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}
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#define SCM_CLASS_REGISTER (0x2 << 8)
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#define SCM_MASK_IRQS BIT(5)
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#define SCM_ATOMIC(svc, cmd, n) (((((svc) << 10)|((cmd) & 0x3ff)) << 12) | \
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SCM_CLASS_REGISTER | \
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SCM_MASK_IRQS | \
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(n & 0xf))
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/**
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* qcom_scm_call_atomic1() - Send an atomic SCM command with one argument
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* @svc_id: service identifier
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* @cmd_id: command identifier
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* @arg1: first argument
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*
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* This shall only be used with commands that are guaranteed to be
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* uninterruptable, atomic and SMP safe.
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*/
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static s32 qcom_scm_call_atomic1(u32 svc, u32 cmd, u32 arg1)
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{
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int context_id;
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register u32 r0 asm("r0") = SCM_ATOMIC(svc, cmd, 1);
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register u32 r1 asm("r1") = (u32)&context_id;
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register u32 r2 asm("r2") = arg1;
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asm volatile(
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__asmeq("%0", "r0")
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__asmeq("%1", "r0")
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__asmeq("%2", "r1")
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__asmeq("%3", "r2")
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#ifdef REQUIRES_SEC
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".arch_extension sec\n"
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#endif
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"smc #0 @ switch to secure world\n"
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: "=r" (r0)
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: "r" (r0), "r" (r1), "r" (r2)
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: "r3", "r12");
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return r0;
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}
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/**
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* qcom_scm_call_atomic2() - Send an atomic SCM command with two arguments
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* @svc_id: service identifier
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* @cmd_id: command identifier
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* @arg1: first argument
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* @arg2: second argument
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*
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* This shall only be used with commands that are guaranteed to be
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* uninterruptable, atomic and SMP safe.
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*/
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static s32 qcom_scm_call_atomic2(u32 svc, u32 cmd, u32 arg1, u32 arg2)
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{
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int context_id;
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register u32 r0 asm("r0") = SCM_ATOMIC(svc, cmd, 2);
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register u32 r1 asm("r1") = (u32)&context_id;
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register u32 r2 asm("r2") = arg1;
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register u32 r3 asm("r3") = arg2;
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asm volatile(
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__asmeq("%0", "r0")
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__asmeq("%1", "r0")
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__asmeq("%2", "r1")
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__asmeq("%3", "r2")
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__asmeq("%4", "r3")
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#ifdef REQUIRES_SEC
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".arch_extension sec\n"
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#endif
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"smc #0 @ switch to secure world\n"
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: "=r" (r0)
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: "r" (r0), "r" (r1), "r" (r2), "r" (r3)
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: "r12");
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return r0;
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}
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u32 qcom_scm_get_version(void)
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{
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int context_id;
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static u32 version = -1;
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register u32 r0 asm("r0");
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register u32 r1 asm("r1");
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if (version != -1)
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return version;
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mutex_lock(&qcom_scm_lock);
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r0 = 0x1 << 8;
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r1 = (u32)&context_id;
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do {
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asm volatile(
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__asmeq("%0", "r0")
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__asmeq("%1", "r1")
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__asmeq("%2", "r0")
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__asmeq("%3", "r1")
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#ifdef REQUIRES_SEC
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".arch_extension sec\n"
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#endif
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"smc #0 @ switch to secure world\n"
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: "=r" (r0), "=r" (r1)
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: "r" (r0), "r" (r1)
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: "r2", "r3", "r12");
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} while (r0 == QCOM_SCM_INTERRUPTED);
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version = r1;
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mutex_unlock(&qcom_scm_lock);
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return version;
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}
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EXPORT_SYMBOL(qcom_scm_get_version);
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/**
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* qcom_scm_set_cold_boot_addr() - Set the cold boot address for cpus
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* @entry: Entry point function for the cpus
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* @cpus: The cpumask of cpus that will use the entry point
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*
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* Set the cold boot address of the cpus. Any cpu outside the supported
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* range would be removed from the cpu present mask.
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*/
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int __qcom_scm_set_cold_boot_addr(void *entry, const cpumask_t *cpus)
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{
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int flags = 0;
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int cpu;
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int scm_cb_flags[] = {
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QCOM_SCM_FLAG_COLDBOOT_CPU0,
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QCOM_SCM_FLAG_COLDBOOT_CPU1,
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QCOM_SCM_FLAG_COLDBOOT_CPU2,
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QCOM_SCM_FLAG_COLDBOOT_CPU3,
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};
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if (!cpus || (cpus && cpumask_empty(cpus)))
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return -EINVAL;
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for_each_cpu(cpu, cpus) {
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if (cpu < ARRAY_SIZE(scm_cb_flags))
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flags |= scm_cb_flags[cpu];
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else
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set_cpu_present(cpu, false);
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}
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return qcom_scm_call_atomic2(QCOM_SCM_SVC_BOOT, QCOM_SCM_BOOT_ADDR,
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flags, virt_to_phys(entry));
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}
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/**
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* qcom_scm_set_warm_boot_addr() - Set the warm boot address for cpus
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* @entry: Entry point function for the cpus
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* @cpus: The cpumask of cpus that will use the entry point
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*
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* Set the Linux entry point for the SCM to transfer control to when coming
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* out of a power down. CPU power down may be executed on cpuidle or hotplug.
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*/
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int __qcom_scm_set_warm_boot_addr(struct device *dev, void *entry,
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const cpumask_t *cpus)
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{
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int ret;
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int flags = 0;
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int cpu;
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struct {
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__le32 flags;
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__le32 addr;
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} cmd;
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/*
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* Reassign only if we are switching from hotplug entry point
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* to cpuidle entry point or vice versa.
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*/
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for_each_cpu(cpu, cpus) {
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if (entry == qcom_scm_wb[cpu].entry)
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continue;
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flags |= qcom_scm_wb[cpu].flag;
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}
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/* No change in entry function */
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if (!flags)
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return 0;
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cmd.addr = cpu_to_le32(virt_to_phys(entry));
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cmd.flags = cpu_to_le32(flags);
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ret = qcom_scm_call(dev, QCOM_SCM_SVC_BOOT, QCOM_SCM_BOOT_ADDR,
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&cmd, sizeof(cmd), NULL, 0);
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if (!ret) {
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for_each_cpu(cpu, cpus)
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qcom_scm_wb[cpu].entry = entry;
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}
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return ret;
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}
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/**
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* qcom_scm_cpu_power_down() - Power down the cpu
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* @flags - Flags to flush cache
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*
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* This is an end point to power down cpu. If there was a pending interrupt,
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* the control would return from this function, otherwise, the cpu jumps to the
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* warm boot entry point set for this cpu upon reset.
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*/
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void __qcom_scm_cpu_power_down(u32 flags)
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{
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qcom_scm_call_atomic1(QCOM_SCM_SVC_BOOT, QCOM_SCM_CMD_TERMINATE_PC,
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flags & QCOM_SCM_FLUSH_FLAG_MASK);
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}
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int __qcom_scm_is_call_available(struct device *dev, u32 svc_id, u32 cmd_id)
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{
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int ret;
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__le32 svc_cmd = cpu_to_le32((svc_id << 10) | cmd_id);
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__le32 ret_val = 0;
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ret = qcom_scm_call(dev, QCOM_SCM_SVC_INFO, QCOM_IS_CALL_AVAIL_CMD,
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&svc_cmd, sizeof(svc_cmd), &ret_val,
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sizeof(ret_val));
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if (ret)
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return ret;
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return le32_to_cpu(ret_val);
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}
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int __qcom_scm_hdcp_req(struct device *dev, struct qcom_scm_hdcp_req *req,
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u32 req_cnt, u32 *resp)
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{
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if (req_cnt > QCOM_SCM_HDCP_MAX_REQ_CNT)
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return -ERANGE;
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return qcom_scm_call(dev, QCOM_SCM_SVC_HDCP, QCOM_SCM_CMD_HDCP,
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req, req_cnt * sizeof(*req), resp, sizeof(*resp));
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}
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void __qcom_scm_init(void)
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{
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}
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bool __qcom_scm_pas_supported(struct device *dev, u32 peripheral)
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{
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__le32 out;
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__le32 in;
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int ret;
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in = cpu_to_le32(peripheral);
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ret = qcom_scm_call(dev, QCOM_SCM_SVC_PIL,
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QCOM_SCM_PAS_IS_SUPPORTED_CMD,
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&in, sizeof(in),
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&out, sizeof(out));
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return ret ? false : !!out;
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}
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int __qcom_scm_pas_init_image(struct device *dev, u32 peripheral,
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dma_addr_t metadata_phys)
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{
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__le32 scm_ret;
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int ret;
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struct {
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__le32 proc;
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__le32 image_addr;
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} request;
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|
|
request.proc = cpu_to_le32(peripheral);
|
|
request.image_addr = cpu_to_le32(metadata_phys);
|
|
|
|
ret = qcom_scm_call(dev, QCOM_SCM_SVC_PIL,
|
|
QCOM_SCM_PAS_INIT_IMAGE_CMD,
|
|
&request, sizeof(request),
|
|
&scm_ret, sizeof(scm_ret));
|
|
|
|
return ret ? : le32_to_cpu(scm_ret);
|
|
}
|
|
|
|
int __qcom_scm_pas_mem_setup(struct device *dev, u32 peripheral,
|
|
phys_addr_t addr, phys_addr_t size)
|
|
{
|
|
__le32 scm_ret;
|
|
int ret;
|
|
struct {
|
|
__le32 proc;
|
|
__le32 addr;
|
|
__le32 len;
|
|
} request;
|
|
|
|
request.proc = cpu_to_le32(peripheral);
|
|
request.addr = cpu_to_le32(addr);
|
|
request.len = cpu_to_le32(size);
|
|
|
|
ret = qcom_scm_call(dev, QCOM_SCM_SVC_PIL,
|
|
QCOM_SCM_PAS_MEM_SETUP_CMD,
|
|
&request, sizeof(request),
|
|
&scm_ret, sizeof(scm_ret));
|
|
|
|
return ret ? : le32_to_cpu(scm_ret);
|
|
}
|
|
|
|
int __qcom_scm_pas_auth_and_reset(struct device *dev, u32 peripheral)
|
|
{
|
|
__le32 out;
|
|
__le32 in;
|
|
int ret;
|
|
|
|
in = cpu_to_le32(peripheral);
|
|
ret = qcom_scm_call(dev, QCOM_SCM_SVC_PIL,
|
|
QCOM_SCM_PAS_AUTH_AND_RESET_CMD,
|
|
&in, sizeof(in),
|
|
&out, sizeof(out));
|
|
|
|
return ret ? : le32_to_cpu(out);
|
|
}
|
|
|
|
int __qcom_scm_pas_shutdown(struct device *dev, u32 peripheral)
|
|
{
|
|
__le32 out;
|
|
__le32 in;
|
|
int ret;
|
|
|
|
in = cpu_to_le32(peripheral);
|
|
ret = qcom_scm_call(dev, QCOM_SCM_SVC_PIL,
|
|
QCOM_SCM_PAS_SHUTDOWN_CMD,
|
|
&in, sizeof(in),
|
|
&out, sizeof(out));
|
|
|
|
return ret ? : le32_to_cpu(out);
|
|
}
|
|
|
|
int __qcom_scm_pas_mss_reset(struct device *dev, bool reset)
|
|
{
|
|
__le32 out;
|
|
__le32 in = cpu_to_le32(reset);
|
|
int ret;
|
|
|
|
ret = qcom_scm_call(dev, QCOM_SCM_SVC_PIL, QCOM_SCM_PAS_MSS_RESET,
|
|
&in, sizeof(in),
|
|
&out, sizeof(out));
|
|
|
|
return ret ? : le32_to_cpu(out);
|
|
}
|
|
|
|
int __qcom_scm_set_dload_mode(struct device *dev, bool enable)
|
|
{
|
|
return qcom_scm_call_atomic2(QCOM_SCM_SVC_BOOT, QCOM_SCM_SET_DLOAD_MODE,
|
|
enable ? QCOM_SCM_SET_DLOAD_MODE : 0, 0);
|
|
}
|
|
|
|
int __qcom_scm_set_remote_state(struct device *dev, u32 state, u32 id)
|
|
{
|
|
struct {
|
|
__le32 state;
|
|
__le32 id;
|
|
} req;
|
|
__le32 scm_ret = 0;
|
|
int ret;
|
|
|
|
req.state = cpu_to_le32(state);
|
|
req.id = cpu_to_le32(id);
|
|
|
|
ret = qcom_scm_call(dev, QCOM_SCM_SVC_BOOT, QCOM_SCM_SET_REMOTE_STATE,
|
|
&req, sizeof(req), &scm_ret, sizeof(scm_ret));
|
|
|
|
return ret ? : le32_to_cpu(scm_ret);
|
|
}
|
|
|
|
int __qcom_scm_assign_mem(struct device *dev, phys_addr_t mem_region,
|
|
size_t mem_sz, phys_addr_t src, size_t src_sz,
|
|
phys_addr_t dest, size_t dest_sz)
|
|
{
|
|
return -ENODEV;
|
|
}
|
|
|
|
int __qcom_scm_restore_sec_cfg(struct device *dev, u32 device_id,
|
|
u32 spare)
|
|
{
|
|
return -ENODEV;
|
|
}
|
|
|
|
int __qcom_scm_iommu_secure_ptbl_size(struct device *dev, u32 spare,
|
|
size_t *size)
|
|
{
|
|
return -ENODEV;
|
|
}
|
|
|
|
int __qcom_scm_iommu_secure_ptbl_init(struct device *dev, u64 addr, u32 size,
|
|
u32 spare)
|
|
{
|
|
return -ENODEV;
|
|
}
|
|
|
|
int __qcom_scm_io_readl(struct device *dev, phys_addr_t addr,
|
|
unsigned int *val)
|
|
{
|
|
int ret;
|
|
|
|
ret = qcom_scm_call_atomic1(QCOM_SCM_SVC_IO, QCOM_SCM_IO_READ, addr);
|
|
if (ret >= 0)
|
|
*val = ret;
|
|
|
|
return ret < 0 ? ret : 0;
|
|
}
|
|
|
|
int __qcom_scm_io_writel(struct device *dev, phys_addr_t addr, unsigned int val)
|
|
{
|
|
return qcom_scm_call_atomic2(QCOM_SCM_SVC_IO, QCOM_SCM_IO_WRITE,
|
|
addr, val);
|
|
}
|