224 lines
6.0 KiB
C
224 lines
6.0 KiB
C
/*
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* Copyright (C) 2010, Paul Cercueil <paul@crapouillou.net>
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* JZ4740 Watchdog driver
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or (at your
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* option) any later version.
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*
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* You should have received a copy of the GNU General Public License along
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* with this program; if not, write to the Free Software Foundation, Inc.,
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* 675 Mass Ave, Cambridge, MA 02139, USA.
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*
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*/
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#include <linux/module.h>
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#include <linux/moduleparam.h>
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#include <linux/types.h>
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#include <linux/kernel.h>
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#include <linux/watchdog.h>
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#include <linux/platform_device.h>
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#include <linux/io.h>
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#include <linux/device.h>
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#include <linux/clk.h>
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#include <linux/slab.h>
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#include <linux/err.h>
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#include <asm/mach-jz4740/timer.h>
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#define JZ_REG_WDT_TIMER_DATA 0x0
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#define JZ_REG_WDT_COUNTER_ENABLE 0x4
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#define JZ_REG_WDT_TIMER_COUNTER 0x8
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#define JZ_REG_WDT_TIMER_CONTROL 0xC
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#define JZ_WDT_CLOCK_PCLK 0x1
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#define JZ_WDT_CLOCK_RTC 0x2
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#define JZ_WDT_CLOCK_EXT 0x4
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#define JZ_WDT_CLOCK_DIV_SHIFT 3
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#define JZ_WDT_CLOCK_DIV_1 (0 << JZ_WDT_CLOCK_DIV_SHIFT)
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#define JZ_WDT_CLOCK_DIV_4 (1 << JZ_WDT_CLOCK_DIV_SHIFT)
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#define JZ_WDT_CLOCK_DIV_16 (2 << JZ_WDT_CLOCK_DIV_SHIFT)
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#define JZ_WDT_CLOCK_DIV_64 (3 << JZ_WDT_CLOCK_DIV_SHIFT)
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#define JZ_WDT_CLOCK_DIV_256 (4 << JZ_WDT_CLOCK_DIV_SHIFT)
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#define JZ_WDT_CLOCK_DIV_1024 (5 << JZ_WDT_CLOCK_DIV_SHIFT)
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#define DEFAULT_HEARTBEAT 5
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#define MAX_HEARTBEAT 2048
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static bool nowayout = WATCHDOG_NOWAYOUT;
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module_param(nowayout, bool, 0);
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MODULE_PARM_DESC(nowayout,
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"Watchdog cannot be stopped once started (default="
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__MODULE_STRING(WATCHDOG_NOWAYOUT) ")");
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static unsigned int heartbeat = DEFAULT_HEARTBEAT;
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module_param(heartbeat, uint, 0);
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MODULE_PARM_DESC(heartbeat,
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"Watchdog heartbeat period in seconds from 1 to "
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__MODULE_STRING(MAX_HEARTBEAT) ", default "
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__MODULE_STRING(DEFAULT_HEARTBEAT));
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struct jz4740_wdt_drvdata {
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struct watchdog_device wdt;
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void __iomem *base;
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struct clk *rtc_clk;
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};
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static int jz4740_wdt_ping(struct watchdog_device *wdt_dev)
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{
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struct jz4740_wdt_drvdata *drvdata = watchdog_get_drvdata(wdt_dev);
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writew(0x0, drvdata->base + JZ_REG_WDT_TIMER_COUNTER);
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return 0;
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}
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static int jz4740_wdt_set_timeout(struct watchdog_device *wdt_dev,
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unsigned int new_timeout)
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{
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struct jz4740_wdt_drvdata *drvdata = watchdog_get_drvdata(wdt_dev);
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unsigned int rtc_clk_rate;
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unsigned int timeout_value;
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unsigned short clock_div = JZ_WDT_CLOCK_DIV_1;
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rtc_clk_rate = clk_get_rate(drvdata->rtc_clk);
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timeout_value = rtc_clk_rate * new_timeout;
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while (timeout_value > 0xffff) {
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if (clock_div == JZ_WDT_CLOCK_DIV_1024) {
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/* Requested timeout too high;
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* use highest possible value. */
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timeout_value = 0xffff;
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break;
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}
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timeout_value >>= 2;
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clock_div += (1 << JZ_WDT_CLOCK_DIV_SHIFT);
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}
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writeb(0x0, drvdata->base + JZ_REG_WDT_COUNTER_ENABLE);
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writew(clock_div, drvdata->base + JZ_REG_WDT_TIMER_CONTROL);
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writew((u16)timeout_value, drvdata->base + JZ_REG_WDT_TIMER_DATA);
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writew(0x0, drvdata->base + JZ_REG_WDT_TIMER_COUNTER);
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writew(clock_div | JZ_WDT_CLOCK_RTC,
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drvdata->base + JZ_REG_WDT_TIMER_CONTROL);
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writeb(0x1, drvdata->base + JZ_REG_WDT_COUNTER_ENABLE);
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wdt_dev->timeout = new_timeout;
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return 0;
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}
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static int jz4740_wdt_start(struct watchdog_device *wdt_dev)
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{
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jz4740_timer_enable_watchdog();
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jz4740_wdt_set_timeout(wdt_dev, wdt_dev->timeout);
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return 0;
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}
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static int jz4740_wdt_stop(struct watchdog_device *wdt_dev)
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{
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struct jz4740_wdt_drvdata *drvdata = watchdog_get_drvdata(wdt_dev);
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jz4740_timer_disable_watchdog();
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writeb(0x0, drvdata->base + JZ_REG_WDT_COUNTER_ENABLE);
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return 0;
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}
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static const struct watchdog_info jz4740_wdt_info = {
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.options = WDIOF_SETTIMEOUT | WDIOF_KEEPALIVEPING | WDIOF_MAGICCLOSE,
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.identity = "jz4740 Watchdog",
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};
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static const struct watchdog_ops jz4740_wdt_ops = {
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.owner = THIS_MODULE,
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.start = jz4740_wdt_start,
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.stop = jz4740_wdt_stop,
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.ping = jz4740_wdt_ping,
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.set_timeout = jz4740_wdt_set_timeout,
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};
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static int jz4740_wdt_probe(struct platform_device *pdev)
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{
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struct jz4740_wdt_drvdata *drvdata;
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struct watchdog_device *jz4740_wdt;
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struct resource *res;
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int ret;
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drvdata = devm_kzalloc(&pdev->dev, sizeof(struct jz4740_wdt_drvdata),
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GFP_KERNEL);
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if (!drvdata) {
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dev_err(&pdev->dev, "Unable to alloacate watchdog device\n");
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return -ENOMEM;
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}
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if (heartbeat < 1 || heartbeat > MAX_HEARTBEAT)
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heartbeat = DEFAULT_HEARTBEAT;
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jz4740_wdt = &drvdata->wdt;
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jz4740_wdt->info = &jz4740_wdt_info;
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jz4740_wdt->ops = &jz4740_wdt_ops;
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jz4740_wdt->timeout = heartbeat;
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jz4740_wdt->min_timeout = 1;
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jz4740_wdt->max_timeout = MAX_HEARTBEAT;
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watchdog_set_nowayout(jz4740_wdt, nowayout);
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watchdog_set_drvdata(jz4740_wdt, drvdata);
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res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
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drvdata->base = devm_ioremap_resource(&pdev->dev, res);
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if (IS_ERR(drvdata->base)) {
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ret = PTR_ERR(drvdata->base);
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goto err_out;
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}
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drvdata->rtc_clk = clk_get(&pdev->dev, "rtc");
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if (IS_ERR(drvdata->rtc_clk)) {
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dev_err(&pdev->dev, "cannot find RTC clock\n");
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ret = PTR_ERR(drvdata->rtc_clk);
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goto err_out;
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}
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ret = watchdog_register_device(&drvdata->wdt);
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if (ret < 0)
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goto err_disable_clk;
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platform_set_drvdata(pdev, drvdata);
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return 0;
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err_disable_clk:
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clk_put(drvdata->rtc_clk);
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err_out:
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return ret;
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}
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static int jz4740_wdt_remove(struct platform_device *pdev)
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{
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struct jz4740_wdt_drvdata *drvdata = platform_get_drvdata(pdev);
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jz4740_wdt_stop(&drvdata->wdt);
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watchdog_unregister_device(&drvdata->wdt);
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clk_put(drvdata->rtc_clk);
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return 0;
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}
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static struct platform_driver jz4740_wdt_driver = {
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.probe = jz4740_wdt_probe,
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.remove = jz4740_wdt_remove,
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.driver = {
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.name = "jz4740-wdt",
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.owner = THIS_MODULE,
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},
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};
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module_platform_driver(jz4740_wdt_driver);
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MODULE_AUTHOR("Paul Cercueil <paul@crapouillou.net>");
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MODULE_DESCRIPTION("jz4740 Watchdog Driver");
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MODULE_LICENSE("GPL");
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MODULE_ALIAS("platform:jz4740-wdt");
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