235 lines
5.3 KiB
C
235 lines
5.3 KiB
C
/*
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* Copyright (C) Freescale Semicondutor, Inc. 2006-2007. All rights reserved.
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*
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* Author: Andy Fleming <afleming@freescale.com>
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*
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* Based on 83xx/mpc8360e_pb.c by:
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* Li Yang <LeoLi@freescale.com>
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* Yin Olivia <Hong-hua.Yin@freescale.com>
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*
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* Description:
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* MPC85xx MDS board specific routines.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or (at your
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* option) any later version.
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*/
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#include <linux/stddef.h>
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#include <linux/kernel.h>
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#include <linux/init.h>
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#include <linux/errno.h>
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#include <linux/reboot.h>
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#include <linux/pci.h>
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#include <linux/kdev_t.h>
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#include <linux/major.h>
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#include <linux/console.h>
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#include <linux/delay.h>
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#include <linux/seq_file.h>
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#include <linux/initrd.h>
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#include <linux/module.h>
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#include <linux/fsl_devices.h>
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#include <asm/of_device.h>
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#include <asm/of_platform.h>
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#include <asm/system.h>
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#include <asm/atomic.h>
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#include <asm/time.h>
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#include <asm/io.h>
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#include <asm/machdep.h>
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#include <asm/bootinfo.h>
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#include <asm/pci-bridge.h>
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#include <asm/mpc85xx.h>
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#include <asm/irq.h>
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#include <mm/mmu_decl.h>
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#include <asm/prom.h>
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#include <asm/udbg.h>
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#include <sysdev/fsl_soc.h>
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#include <asm/qe.h>
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#include <asm/qe_ic.h>
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#include <asm/mpic.h>
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#include "mpc85xx.h"
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#undef DEBUG
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#ifdef DEBUG
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#define DBG(fmt...) udbg_printf(fmt)
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#else
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#define DBG(fmt...)
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#endif
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#ifndef CONFIG_PCI
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unsigned long isa_io_base = 0;
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unsigned long isa_mem_base = 0;
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#endif
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/* ************************************************************************
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*
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* Setup the architecture
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*
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*/
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static void __init mpc85xx_mds_setup_arch(void)
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{
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struct device_node *np;
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static u8 *bcsr_regs = NULL;
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if (ppc_md.progress)
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ppc_md.progress("mpc85xx_mds_setup_arch()", 0);
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np = of_find_node_by_type(NULL, "cpu");
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if (np != NULL) {
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const unsigned int *fp =
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get_property(np, "clock-frequency", NULL);
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if (fp != NULL)
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loops_per_jiffy = *fp / HZ;
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else
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loops_per_jiffy = 50000000 / HZ;
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of_node_put(np);
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}
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/* Map BCSR area */
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np = of_find_node_by_name(NULL, "bcsr");
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if (np != NULL) {
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struct resource res;
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of_address_to_resource(np, 0, &res);
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bcsr_regs = ioremap(res.start, res.end - res.start +1);
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of_node_put(np);
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}
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#ifdef CONFIG_PCI
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for (np = NULL; (np = of_find_node_by_type(np, "pci")) != NULL;) {
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add_bridge(np);
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}
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of_node_put(np);
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#endif
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#ifdef CONFIG_QUICC_ENGINE
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if ((np = of_find_node_by_name(NULL, "qe")) != NULL) {
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qe_reset();
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of_node_put(np);
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}
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if ((np = of_find_node_by_name(NULL, "par_io")) != NULL) {
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struct device_node *ucc = NULL;
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par_io_init(np);
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of_node_put(np);
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for ( ;(ucc = of_find_node_by_name(ucc, "ucc")) != NULL;)
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par_io_of_config(ucc);
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of_node_put(ucc);
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}
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if (bcsr_regs) {
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u8 bcsr_phy;
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/* Reset the Ethernet PHY */
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bcsr_phy = in_be8(&bcsr_regs[9]);
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bcsr_phy &= ~0x20;
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out_be8(&bcsr_regs[9], bcsr_phy);
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udelay(1000);
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bcsr_phy = in_be8(&bcsr_regs[9]);
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bcsr_phy |= 0x20;
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out_be8(&bcsr_regs[9], bcsr_phy);
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iounmap(bcsr_regs);
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}
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#endif /* CONFIG_QUICC_ENGINE */
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}
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static struct of_device_id mpc85xx_ids[] = {
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{ .type = "soc", },
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{ .compatible = "soc", },
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{ .type = "qe", },
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{},
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};
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static int __init mpc85xx_publish_devices(void)
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{
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if (!machine_is(mpc85xx_mds))
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return 0;
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/* Publish the QE devices */
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of_platform_bus_probe(NULL,mpc85xx_ids,NULL);
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return 0;
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}
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device_initcall(mpc85xx_publish_devices);
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static void __init mpc85xx_mds_pic_init(void)
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{
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struct mpic *mpic;
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struct resource r;
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struct device_node *np = NULL;
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np = of_find_node_by_type(NULL, "open-pic");
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if (!np)
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return;
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if (of_address_to_resource(np, 0, &r)) {
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printk(KERN_ERR "Failed to map mpic register space\n");
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of_node_put(np);
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return;
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}
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mpic = mpic_alloc(np, r.start,
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MPIC_PRIMARY | MPIC_WANTS_RESET | MPIC_BIG_ENDIAN,
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4, 0, " OpenPIC ");
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BUG_ON(mpic == NULL);
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of_node_put(np);
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/* Internal Interrupts */
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mpic_assign_isu(mpic, 0, r.start + 0x10200);
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mpic_assign_isu(mpic, 1, r.start + 0x10280);
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mpic_assign_isu(mpic, 2, r.start + 0x10300);
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mpic_assign_isu(mpic, 3, r.start + 0x10380);
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mpic_assign_isu(mpic, 4, r.start + 0x10400);
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mpic_assign_isu(mpic, 5, r.start + 0x10480);
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mpic_assign_isu(mpic, 6, r.start + 0x10500);
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mpic_assign_isu(mpic, 7, r.start + 0x10580);
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mpic_assign_isu(mpic, 8, r.start + 0x10600);
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mpic_assign_isu(mpic, 9, r.start + 0x10680);
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mpic_assign_isu(mpic, 10, r.start + 0x10700);
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mpic_assign_isu(mpic, 11, r.start + 0x10780);
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/* External Interrupts */
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mpic_assign_isu(mpic, 12, r.start + 0x10000);
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mpic_assign_isu(mpic, 13, r.start + 0x10080);
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mpic_assign_isu(mpic, 14, r.start + 0x10100);
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mpic_init(mpic);
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#ifdef CONFIG_QUICC_ENGINE
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np = of_find_node_by_type(NULL, "qeic");
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if (!np)
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return;
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qe_ic_init(np, 0);
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of_node_put(np);
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#endif /* CONFIG_QUICC_ENGINE */
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}
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static int __init mpc85xx_mds_probe(void)
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{
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unsigned long root = of_get_flat_dt_root();
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return of_flat_dt_is_compatible(root, "MPC85xxMDS");
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}
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define_machine(mpc85xx_mds) {
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.name = "MPC85xx MDS",
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.probe = mpc85xx_mds_probe,
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.setup_arch = mpc85xx_mds_setup_arch,
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.init_IRQ = mpc85xx_mds_pic_init,
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.get_irq = mpic_get_irq,
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.restart = mpc85xx_restart,
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.calibrate_decr = generic_calibrate_decr,
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.progress = udbg_progress,
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};
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