37 lines
988 B
Plaintext
37 lines
988 B
Plaintext
/* Linker script for the sim85e2c simulator, which is a verilog simulation of
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the V850E2 NA85E2C cpu core (CONFIG_V850E2_SIM85E2C). */
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MEMORY {
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/* 1MB of `instruction RAM', starting at 0.
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Instruction fetches are much faster from IRAM than from DRAM. */
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IRAM : ORIGIN = IRAM_ADDR, LENGTH = IRAM_SIZE
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/* 1MB of `data RAM', below and contiguous with the I/O space.
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Data fetches are much faster from DRAM than from IRAM. */
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DRAM : ORIGIN = DRAM_ADDR, LENGTH = DRAM_SIZE
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/* `external ram' (CS1 area), comes after IRAM. */
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ERAM : ORIGIN = ERAM_ADDR, LENGTH = ERAM_SIZE
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/* Dynamic RAM; uses memory controller. */
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SDRAM : ORIGIN = SDRAM_ADDR, LENGTH = SDRAM_SIZE
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}
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SECTIONS {
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.iram : {
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INTV_CONTENTS
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*arch/v850/kernel/head.o
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*(.early.text)
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} > IRAM
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.dram : {
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_memcons_output = . ;
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. = . + 0x8000 ;
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_memcons_output_end = . ;
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} > DRAM
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.sdram : {
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/* We stick console output into a buffer here. */
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RAMK_KRAM_CONTENTS
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ROOT_FS_CONTENTS
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} > SDRAM
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}
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