444 lines
14 KiB
C
444 lines
14 KiB
C
/*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*
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* Inline assembly cache operations.
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*
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* Copyright (C) 1996 David S. Miller (dm@engr.sgi.com)
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* Copyright (C) 1997 - 2002 Ralf Baechle (ralf@gnu.org)
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* Copyright (C) 2004 Ralf Baechle (ralf@linux-mips.org)
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*/
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#ifndef _ASM_R4KCACHE_H
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#define _ASM_R4KCACHE_H
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#include <asm/asm.h>
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#include <asm/cacheops.h>
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#include <asm/cpu-features.h>
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#include <asm/mipsmtregs.h>
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/*
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* This macro return a properly sign-extended address suitable as base address
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* for indexed cache operations. Two issues here:
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*
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* - The MIPS32 and MIPS64 specs permit an implementation to directly derive
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* the index bits from the virtual address. This breaks with tradition
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* set by the R4000. To keep unpleasant surprises from happening we pick
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* an address in KSEG0 / CKSEG0.
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* - We need a properly sign extended address for 64-bit code. To get away
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* without ifdefs we let the compiler do it by a type cast.
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*/
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#define INDEX_BASE CKSEG0
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#define cache_op(op,addr) \
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__asm__ __volatile__( \
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" .set push \n" \
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" .set noreorder \n" \
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" .set mips3\n\t \n" \
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" cache %0, %1 \n" \
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" .set pop \n" \
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: \
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: "i" (op), "R" (*(unsigned char *)(addr)))
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#ifdef CONFIG_MIPS_MT
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/*
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* Temporary hacks for SMTC debug. Optionally force single-threaded
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* execution during I-cache flushes.
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*/
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#define PROTECT_CACHE_FLUSHES 1
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#ifdef PROTECT_CACHE_FLUSHES
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extern int mt_protiflush;
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extern int mt_protdflush;
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extern void mt_cflush_lockdown(void);
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extern void mt_cflush_release(void);
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#define BEGIN_MT_IPROT \
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unsigned long flags = 0; \
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unsigned long mtflags = 0; \
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if(mt_protiflush) { \
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local_irq_save(flags); \
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ehb(); \
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mtflags = dvpe(); \
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mt_cflush_lockdown(); \
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}
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#define END_MT_IPROT \
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if(mt_protiflush) { \
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mt_cflush_release(); \
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evpe(mtflags); \
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local_irq_restore(flags); \
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}
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#define BEGIN_MT_DPROT \
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unsigned long flags = 0; \
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unsigned long mtflags = 0; \
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if(mt_protdflush) { \
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local_irq_save(flags); \
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ehb(); \
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mtflags = dvpe(); \
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mt_cflush_lockdown(); \
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}
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#define END_MT_DPROT \
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if(mt_protdflush) { \
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mt_cflush_release(); \
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evpe(mtflags); \
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local_irq_restore(flags); \
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}
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#else
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#define BEGIN_MT_IPROT
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#define BEGIN_MT_DPROT
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#define END_MT_IPROT
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#define END_MT_DPROT
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#endif /* PROTECT_CACHE_FLUSHES */
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#define __iflush_prologue \
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unsigned long redundance; \
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extern int mt_n_iflushes; \
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BEGIN_MT_IPROT \
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for (redundance = 0; redundance < mt_n_iflushes; redundance++) {
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#define __iflush_epilogue \
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END_MT_IPROT \
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}
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#define __dflush_prologue \
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unsigned long redundance; \
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extern int mt_n_dflushes; \
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BEGIN_MT_DPROT \
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for (redundance = 0; redundance < mt_n_dflushes; redundance++) {
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#define __dflush_epilogue \
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END_MT_DPROT \
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}
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#define __inv_dflush_prologue __dflush_prologue
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#define __inv_dflush_epilogue __dflush_epilogue
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#define __sflush_prologue {
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#define __sflush_epilogue }
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#define __inv_sflush_prologue __sflush_prologue
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#define __inv_sflush_epilogue __sflush_epilogue
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#else /* CONFIG_MIPS_MT */
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#define __iflush_prologue {
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#define __iflush_epilogue }
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#define __dflush_prologue {
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#define __dflush_epilogue }
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#define __inv_dflush_prologue {
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#define __inv_dflush_epilogue }
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#define __sflush_prologue {
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#define __sflush_epilogue }
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#define __inv_sflush_prologue {
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#define __inv_sflush_epilogue }
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#endif /* CONFIG_MIPS_MT */
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static inline void flush_icache_line_indexed(unsigned long addr)
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{
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__iflush_prologue
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cache_op(Index_Invalidate_I, addr);
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__iflush_epilogue
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}
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static inline void flush_dcache_line_indexed(unsigned long addr)
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{
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__dflush_prologue
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cache_op(Index_Writeback_Inv_D, addr);
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__dflush_epilogue
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}
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static inline void flush_scache_line_indexed(unsigned long addr)
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{
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cache_op(Index_Writeback_Inv_SD, addr);
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}
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static inline void flush_icache_line(unsigned long addr)
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{
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__iflush_prologue
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cache_op(Hit_Invalidate_I, addr);
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__iflush_epilogue
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}
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static inline void flush_dcache_line(unsigned long addr)
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{
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__dflush_prologue
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cache_op(Hit_Writeback_Inv_D, addr);
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__dflush_epilogue
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}
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static inline void invalidate_dcache_line(unsigned long addr)
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{
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__dflush_prologue
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cache_op(Hit_Invalidate_D, addr);
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__dflush_epilogue
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}
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static inline void invalidate_scache_line(unsigned long addr)
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{
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cache_op(Hit_Invalidate_SD, addr);
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}
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static inline void flush_scache_line(unsigned long addr)
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{
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cache_op(Hit_Writeback_Inv_SD, addr);
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}
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#define protected_cache_op(op,addr) \
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__asm__ __volatile__( \
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" .set push \n" \
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" .set noreorder \n" \
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" .set mips3 \n" \
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"1: cache %0, (%1) \n" \
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"2: .set pop \n" \
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" .section __ex_table,\"a\" \n" \
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" "STR(PTR)" 1b, 2b \n" \
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" .previous" \
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: \
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: "i" (op), "r" (addr))
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/*
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* The next two are for badland addresses like signal trampolines.
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*/
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static inline void protected_flush_icache_line(unsigned long addr)
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{
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protected_cache_op(Hit_Invalidate_I, addr);
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}
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/*
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* R10000 / R12000 hazard - these processors don't support the Hit_Writeback_D
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* cacheop so we use Hit_Writeback_Inv_D which is supported by all R4000-style
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* caches. We're talking about one cacheline unnecessarily getting invalidated
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* here so the penalty isn't overly hard.
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*/
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static inline void protected_writeback_dcache_line(unsigned long addr)
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{
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protected_cache_op(Hit_Writeback_Inv_D, addr);
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}
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static inline void protected_writeback_scache_line(unsigned long addr)
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{
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protected_cache_op(Hit_Writeback_Inv_SD, addr);
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}
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/*
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* This one is RM7000-specific
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*/
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static inline void invalidate_tcache_page(unsigned long addr)
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{
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cache_op(Page_Invalidate_T, addr);
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}
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#define cache16_unroll32(base,op) \
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__asm__ __volatile__( \
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" .set push \n" \
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" .set noreorder \n" \
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" .set mips3 \n" \
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" cache %1, 0x000(%0); cache %1, 0x010(%0) \n" \
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" cache %1, 0x020(%0); cache %1, 0x030(%0) \n" \
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" cache %1, 0x040(%0); cache %1, 0x050(%0) \n" \
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" cache %1, 0x060(%0); cache %1, 0x070(%0) \n" \
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" cache %1, 0x080(%0); cache %1, 0x090(%0) \n" \
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" cache %1, 0x0a0(%0); cache %1, 0x0b0(%0) \n" \
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" cache %1, 0x0c0(%0); cache %1, 0x0d0(%0) \n" \
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" cache %1, 0x0e0(%0); cache %1, 0x0f0(%0) \n" \
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" cache %1, 0x100(%0); cache %1, 0x110(%0) \n" \
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" cache %1, 0x120(%0); cache %1, 0x130(%0) \n" \
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" cache %1, 0x140(%0); cache %1, 0x150(%0) \n" \
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" cache %1, 0x160(%0); cache %1, 0x170(%0) \n" \
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" cache %1, 0x180(%0); cache %1, 0x190(%0) \n" \
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" cache %1, 0x1a0(%0); cache %1, 0x1b0(%0) \n" \
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" cache %1, 0x1c0(%0); cache %1, 0x1d0(%0) \n" \
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" cache %1, 0x1e0(%0); cache %1, 0x1f0(%0) \n" \
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" .set pop \n" \
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: \
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: "r" (base), \
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"i" (op));
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#define cache32_unroll32(base,op) \
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__asm__ __volatile__( \
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" .set push \n" \
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" .set noreorder \n" \
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" .set mips3 \n" \
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" cache %1, 0x000(%0); cache %1, 0x020(%0) \n" \
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" cache %1, 0x040(%0); cache %1, 0x060(%0) \n" \
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" cache %1, 0x080(%0); cache %1, 0x0a0(%0) \n" \
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" cache %1, 0x0c0(%0); cache %1, 0x0e0(%0) \n" \
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" cache %1, 0x100(%0); cache %1, 0x120(%0) \n" \
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" cache %1, 0x140(%0); cache %1, 0x160(%0) \n" \
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" cache %1, 0x180(%0); cache %1, 0x1a0(%0) \n" \
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" cache %1, 0x1c0(%0); cache %1, 0x1e0(%0) \n" \
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" cache %1, 0x200(%0); cache %1, 0x220(%0) \n" \
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" cache %1, 0x240(%0); cache %1, 0x260(%0) \n" \
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" cache %1, 0x280(%0); cache %1, 0x2a0(%0) \n" \
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" cache %1, 0x2c0(%0); cache %1, 0x2e0(%0) \n" \
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" cache %1, 0x300(%0); cache %1, 0x320(%0) \n" \
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" cache %1, 0x340(%0); cache %1, 0x360(%0) \n" \
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" cache %1, 0x380(%0); cache %1, 0x3a0(%0) \n" \
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" cache %1, 0x3c0(%0); cache %1, 0x3e0(%0) \n" \
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" .set pop \n" \
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: \
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: "r" (base), \
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"i" (op));
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#define cache64_unroll32(base,op) \
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__asm__ __volatile__( \
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" .set push \n" \
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" .set noreorder \n" \
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" .set mips3 \n" \
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" cache %1, 0x000(%0); cache %1, 0x040(%0) \n" \
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" cache %1, 0x080(%0); cache %1, 0x0c0(%0) \n" \
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" cache %1, 0x100(%0); cache %1, 0x140(%0) \n" \
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" cache %1, 0x180(%0); cache %1, 0x1c0(%0) \n" \
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" cache %1, 0x200(%0); cache %1, 0x240(%0) \n" \
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" cache %1, 0x280(%0); cache %1, 0x2c0(%0) \n" \
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" cache %1, 0x300(%0); cache %1, 0x340(%0) \n" \
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" cache %1, 0x380(%0); cache %1, 0x3c0(%0) \n" \
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" cache %1, 0x400(%0); cache %1, 0x440(%0) \n" \
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" cache %1, 0x480(%0); cache %1, 0x4c0(%0) \n" \
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" cache %1, 0x500(%0); cache %1, 0x540(%0) \n" \
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" cache %1, 0x580(%0); cache %1, 0x5c0(%0) \n" \
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" cache %1, 0x600(%0); cache %1, 0x640(%0) \n" \
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" cache %1, 0x680(%0); cache %1, 0x6c0(%0) \n" \
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" cache %1, 0x700(%0); cache %1, 0x740(%0) \n" \
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" cache %1, 0x780(%0); cache %1, 0x7c0(%0) \n" \
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" .set pop \n" \
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: \
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: "r" (base), \
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"i" (op));
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#define cache128_unroll32(base,op) \
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__asm__ __volatile__( \
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" .set push \n" \
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" .set noreorder \n" \
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" .set mips3 \n" \
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" cache %1, 0x000(%0); cache %1, 0x080(%0) \n" \
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" cache %1, 0x100(%0); cache %1, 0x180(%0) \n" \
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" cache %1, 0x200(%0); cache %1, 0x280(%0) \n" \
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" cache %1, 0x300(%0); cache %1, 0x380(%0) \n" \
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" cache %1, 0x400(%0); cache %1, 0x480(%0) \n" \
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" cache %1, 0x500(%0); cache %1, 0x580(%0) \n" \
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" cache %1, 0x600(%0); cache %1, 0x680(%0) \n" \
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" cache %1, 0x700(%0); cache %1, 0x780(%0) \n" \
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" cache %1, 0x800(%0); cache %1, 0x880(%0) \n" \
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" cache %1, 0x900(%0); cache %1, 0x980(%0) \n" \
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" cache %1, 0xa00(%0); cache %1, 0xa80(%0) \n" \
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" cache %1, 0xb00(%0); cache %1, 0xb80(%0) \n" \
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" cache %1, 0xc00(%0); cache %1, 0xc80(%0) \n" \
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" cache %1, 0xd00(%0); cache %1, 0xd80(%0) \n" \
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" cache %1, 0xe00(%0); cache %1, 0xe80(%0) \n" \
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" cache %1, 0xf00(%0); cache %1, 0xf80(%0) \n" \
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" .set pop \n" \
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: \
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: "r" (base), \
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"i" (op));
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/* build blast_xxx, blast_xxx_page, blast_xxx_page_indexed */
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#define __BUILD_BLAST_CACHE(pfx, desc, indexop, hitop, lsize) \
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static inline void blast_##pfx##cache##lsize(void) \
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{ \
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unsigned long start = INDEX_BASE; \
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unsigned long end = start + current_cpu_data.desc.waysize; \
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unsigned long ws_inc = 1UL << current_cpu_data.desc.waybit; \
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unsigned long ws_end = current_cpu_data.desc.ways << \
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current_cpu_data.desc.waybit; \
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unsigned long ws, addr; \
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\
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__##pfx##flush_prologue \
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\
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for (ws = 0; ws < ws_end; ws += ws_inc) \
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for (addr = start; addr < end; addr += lsize * 32) \
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cache##lsize##_unroll32(addr|ws, indexop); \
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\
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__##pfx##flush_epilogue \
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} \
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\
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static inline void blast_##pfx##cache##lsize##_page(unsigned long page) \
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{ \
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unsigned long start = page; \
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unsigned long end = page + PAGE_SIZE; \
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\
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__##pfx##flush_prologue \
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\
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do { \
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cache##lsize##_unroll32(start, hitop); \
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start += lsize * 32; \
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} while (start < end); \
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\
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__##pfx##flush_epilogue \
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} \
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\
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static inline void blast_##pfx##cache##lsize##_page_indexed(unsigned long page) \
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{ \
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unsigned long indexmask = current_cpu_data.desc.waysize - 1; \
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unsigned long start = INDEX_BASE + (page & indexmask); \
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unsigned long end = start + PAGE_SIZE; \
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unsigned long ws_inc = 1UL << current_cpu_data.desc.waybit; \
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unsigned long ws_end = current_cpu_data.desc.ways << \
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current_cpu_data.desc.waybit; \
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unsigned long ws, addr; \
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\
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__##pfx##flush_prologue \
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\
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for (ws = 0; ws < ws_end; ws += ws_inc) \
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for (addr = start; addr < end; addr += lsize * 32) \
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cache##lsize##_unroll32(addr|ws, indexop); \
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\
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__##pfx##flush_epilogue \
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}
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__BUILD_BLAST_CACHE(d, dcache, Index_Writeback_Inv_D, Hit_Writeback_Inv_D, 16)
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__BUILD_BLAST_CACHE(i, icache, Index_Invalidate_I, Hit_Invalidate_I, 16)
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__BUILD_BLAST_CACHE(s, scache, Index_Writeback_Inv_SD, Hit_Writeback_Inv_SD, 16)
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__BUILD_BLAST_CACHE(d, dcache, Index_Writeback_Inv_D, Hit_Writeback_Inv_D, 32)
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__BUILD_BLAST_CACHE(i, icache, Index_Invalidate_I, Hit_Invalidate_I, 32)
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__BUILD_BLAST_CACHE(s, scache, Index_Writeback_Inv_SD, Hit_Writeback_Inv_SD, 32)
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__BUILD_BLAST_CACHE(i, icache, Index_Invalidate_I, Hit_Invalidate_I, 64)
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__BUILD_BLAST_CACHE(s, scache, Index_Writeback_Inv_SD, Hit_Writeback_Inv_SD, 64)
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__BUILD_BLAST_CACHE(s, scache, Index_Writeback_Inv_SD, Hit_Writeback_Inv_SD, 128)
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__BUILD_BLAST_CACHE(inv_d, dcache, Index_Writeback_Inv_D, Hit_Invalidate_D, 16)
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__BUILD_BLAST_CACHE(inv_d, dcache, Index_Writeback_Inv_D, Hit_Invalidate_D, 32)
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__BUILD_BLAST_CACHE(inv_s, scache, Index_Writeback_Inv_SD, Hit_Invalidate_SD, 16)
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__BUILD_BLAST_CACHE(inv_s, scache, Index_Writeback_Inv_SD, Hit_Invalidate_SD, 32)
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__BUILD_BLAST_CACHE(inv_s, scache, Index_Writeback_Inv_SD, Hit_Invalidate_SD, 64)
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__BUILD_BLAST_CACHE(inv_s, scache, Index_Writeback_Inv_SD, Hit_Invalidate_SD, 128)
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/* build blast_xxx_range, protected_blast_xxx_range */
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#define __BUILD_BLAST_CACHE_RANGE(pfx, desc, hitop, prot) \
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static inline void prot##blast_##pfx##cache##_range(unsigned long start, \
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unsigned long end) \
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{ \
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unsigned long lsize = cpu_##desc##_line_size(); \
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unsigned long addr = start & ~(lsize - 1); \
|
|
unsigned long aend = (end - 1) & ~(lsize - 1); \
|
|
\
|
|
__##pfx##flush_prologue \
|
|
\
|
|
while (1) { \
|
|
prot##cache_op(hitop, addr); \
|
|
if (addr == aend) \
|
|
break; \
|
|
addr += lsize; \
|
|
} \
|
|
\
|
|
__##pfx##flush_epilogue \
|
|
}
|
|
|
|
__BUILD_BLAST_CACHE_RANGE(d, dcache, Hit_Writeback_Inv_D, protected_)
|
|
__BUILD_BLAST_CACHE_RANGE(s, scache, Hit_Writeback_Inv_SD, protected_)
|
|
__BUILD_BLAST_CACHE_RANGE(i, icache, Hit_Invalidate_I, protected_)
|
|
__BUILD_BLAST_CACHE_RANGE(d, dcache, Hit_Writeback_Inv_D, )
|
|
__BUILD_BLAST_CACHE_RANGE(s, scache, Hit_Writeback_Inv_SD, )
|
|
/* blast_inv_dcache_range */
|
|
__BUILD_BLAST_CACHE_RANGE(inv_d, dcache, Hit_Invalidate_D, )
|
|
__BUILD_BLAST_CACHE_RANGE(inv_s, scache, Hit_Invalidate_SD, )
|
|
|
|
#endif /* _ASM_R4KCACHE_H */
|