381 lines
10 KiB
C
381 lines
10 KiB
C
/*
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* Copyright (C) 2012 ARM Ltd.
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* Author: Marc Zyngier <marc.zyngier@arm.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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*/
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#ifndef __ASM_ARM_KVM_VGIC_H
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#define __ASM_ARM_KVM_VGIC_H
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#include <linux/kernel.h>
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#include <linux/kvm.h>
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#include <linux/irqreturn.h>
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#include <linux/spinlock.h>
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#include <linux/types.h>
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#include <kvm/iodev.h>
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#define VGIC_NR_IRQS_LEGACY 256
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#define VGIC_NR_SGIS 16
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#define VGIC_NR_PPIS 16
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#define VGIC_NR_PRIVATE_IRQS (VGIC_NR_SGIS + VGIC_NR_PPIS)
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#define VGIC_V2_MAX_LRS (1 << 6)
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#define VGIC_V3_MAX_LRS 16
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#define VGIC_MAX_IRQS 1024
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#define VGIC_V2_MAX_CPUS 8
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#define VGIC_V3_MAX_CPUS 255
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#if (VGIC_NR_IRQS_LEGACY & 31)
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#error "VGIC_NR_IRQS must be a multiple of 32"
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#endif
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#if (VGIC_NR_IRQS_LEGACY > VGIC_MAX_IRQS)
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#error "VGIC_NR_IRQS must be <= 1024"
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#endif
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/*
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* The GIC distributor registers describing interrupts have two parts:
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* - 32 per-CPU interrupts (SGI + PPI)
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* - a bunch of shared interrupts (SPI)
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*/
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struct vgic_bitmap {
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/*
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* - One UL per VCPU for private interrupts (assumes UL is at
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* least 32 bits)
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* - As many UL as necessary for shared interrupts.
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*
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* The private interrupts are accessed via the "private"
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* field, one UL per vcpu (the state for vcpu n is in
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* private[n]). The shared interrupts are accessed via the
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* "shared" pointer (IRQn state is at bit n-32 in the bitmap).
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*/
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unsigned long *private;
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unsigned long *shared;
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};
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struct vgic_bytemap {
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/*
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* - 8 u32 per VCPU for private interrupts
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* - As many u32 as necessary for shared interrupts.
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*
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* The private interrupts are accessed via the "private"
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* field, (the state for vcpu n is in private[n*8] to
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* private[n*8 + 7]). The shared interrupts are accessed via
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* the "shared" pointer (IRQn state is at byte (n-32)%4 of the
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* shared[(n-32)/4] word).
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*/
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u32 *private;
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u32 *shared;
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};
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struct kvm_vcpu;
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enum vgic_type {
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VGIC_V2, /* Good ol' GICv2 */
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VGIC_V3, /* New fancy GICv3 */
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};
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#define LR_STATE_PENDING (1 << 0)
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#define LR_STATE_ACTIVE (1 << 1)
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#define LR_STATE_MASK (3 << 0)
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#define LR_EOI_INT (1 << 2)
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#define LR_HW (1 << 3)
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struct vgic_lr {
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unsigned irq:10;
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union {
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unsigned hwirq:10;
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unsigned source:3;
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};
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unsigned state:4;
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};
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struct vgic_vmcr {
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u32 ctlr;
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u32 abpr;
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u32 bpr;
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u32 pmr;
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};
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struct vgic_ops {
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struct vgic_lr (*get_lr)(const struct kvm_vcpu *, int);
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void (*set_lr)(struct kvm_vcpu *, int, struct vgic_lr);
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void (*sync_lr_elrsr)(struct kvm_vcpu *, int, struct vgic_lr);
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u64 (*get_elrsr)(const struct kvm_vcpu *vcpu);
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u64 (*get_eisr)(const struct kvm_vcpu *vcpu);
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void (*clear_eisr)(struct kvm_vcpu *vcpu);
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u32 (*get_interrupt_status)(const struct kvm_vcpu *vcpu);
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void (*enable_underflow)(struct kvm_vcpu *vcpu);
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void (*disable_underflow)(struct kvm_vcpu *vcpu);
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void (*get_vmcr)(struct kvm_vcpu *vcpu, struct vgic_vmcr *vmcr);
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void (*set_vmcr)(struct kvm_vcpu *vcpu, struct vgic_vmcr *vmcr);
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void (*enable)(struct kvm_vcpu *vcpu);
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};
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struct vgic_params {
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/* vgic type */
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enum vgic_type type;
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/* Physical address of vgic virtual cpu interface */
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phys_addr_t vcpu_base;
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/* Number of list registers */
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u32 nr_lr;
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/* Interrupt number */
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unsigned int maint_irq;
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/* Virtual control interface base address */
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void __iomem *vctrl_base;
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int max_gic_vcpus;
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/* Only needed for the legacy KVM_CREATE_IRQCHIP */
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bool can_emulate_gicv2;
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};
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struct vgic_vm_ops {
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bool (*queue_sgi)(struct kvm_vcpu *, int irq);
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void (*add_sgi_source)(struct kvm_vcpu *, int irq, int source);
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int (*init_model)(struct kvm *);
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int (*map_resources)(struct kvm *, const struct vgic_params *);
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};
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struct vgic_io_device {
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gpa_t addr;
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int len;
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const struct vgic_io_range *reg_ranges;
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struct kvm_vcpu *redist_vcpu;
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struct kvm_io_device dev;
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};
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struct irq_phys_map {
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u32 virt_irq;
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u32 phys_irq;
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u32 irq;
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bool active;
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};
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struct irq_phys_map_entry {
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struct list_head entry;
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struct rcu_head rcu;
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struct irq_phys_map map;
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};
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struct vgic_dist {
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spinlock_t lock;
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bool in_kernel;
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bool ready;
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/* vGIC model the kernel emulates for the guest (GICv2 or GICv3) */
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u32 vgic_model;
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int nr_cpus;
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int nr_irqs;
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/* Virtual control interface mapping */
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void __iomem *vctrl_base;
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/* Distributor and vcpu interface mapping in the guest */
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phys_addr_t vgic_dist_base;
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/* GICv2 and GICv3 use different mapped register blocks */
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union {
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phys_addr_t vgic_cpu_base;
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phys_addr_t vgic_redist_base;
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};
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/* Distributor enabled */
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u32 enabled;
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/* Interrupt enabled (one bit per IRQ) */
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struct vgic_bitmap irq_enabled;
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/* Level-triggered interrupt external input is asserted */
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struct vgic_bitmap irq_level;
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/*
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* Interrupt state is pending on the distributor
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*/
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struct vgic_bitmap irq_pending;
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/*
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* Tracks writes to GICD_ISPENDRn and GICD_ICPENDRn for level-triggered
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* interrupts. Essentially holds the state of the flip-flop in
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* Figure 4-10 on page 4-101 in ARM IHI 0048B.b.
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* Once set, it is only cleared for level-triggered interrupts on
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* guest ACKs (when we queue it) or writes to GICD_ICPENDRn.
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*/
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struct vgic_bitmap irq_soft_pend;
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/* Level-triggered interrupt queued on VCPU interface */
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struct vgic_bitmap irq_queued;
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/* Interrupt was active when unqueue from VCPU interface */
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struct vgic_bitmap irq_active;
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/* Interrupt priority. Not used yet. */
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struct vgic_bytemap irq_priority;
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/* Level/edge triggered */
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struct vgic_bitmap irq_cfg;
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/*
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* Source CPU per SGI and target CPU:
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*
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* Each byte represent a SGI observable on a VCPU, each bit of
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* this byte indicating if the corresponding VCPU has
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* generated this interrupt. This is a GICv2 feature only.
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*
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* For VCPUn (n < 8), irq_sgi_sources[n*16] to [n*16 + 15] are
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* the SGIs observable on VCPUn.
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*/
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u8 *irq_sgi_sources;
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/*
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* Target CPU for each SPI:
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*
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* Array of available SPI, each byte indicating the target
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* VCPU for SPI. IRQn (n >=32) is at irq_spi_cpu[n-32].
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*/
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u8 *irq_spi_cpu;
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/*
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* Reverse lookup of irq_spi_cpu for faster compute pending:
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*
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* Array of bitmaps, one per VCPU, describing if IRQn is
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* routed to a particular VCPU.
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*/
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struct vgic_bitmap *irq_spi_target;
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/* Target MPIDR for each IRQ (needed for GICv3 IROUTERn) only */
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u32 *irq_spi_mpidr;
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/* Bitmap indicating which CPU has something pending */
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unsigned long *irq_pending_on_cpu;
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/* Bitmap indicating which CPU has active IRQs */
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unsigned long *irq_active_on_cpu;
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struct vgic_vm_ops vm_ops;
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struct vgic_io_device dist_iodev;
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struct vgic_io_device *redist_iodevs;
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/* Virtual irq to hwirq mapping */
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spinlock_t irq_phys_map_lock;
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struct list_head irq_phys_map_list;
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};
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struct vgic_v2_cpu_if {
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u32 vgic_hcr;
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u32 vgic_vmcr;
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u32 vgic_misr; /* Saved only */
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u64 vgic_eisr; /* Saved only */
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u64 vgic_elrsr; /* Saved only */
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u32 vgic_apr;
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u32 vgic_lr[VGIC_V2_MAX_LRS];
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};
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struct vgic_v3_cpu_if {
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#ifdef CONFIG_ARM_GIC_V3
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u32 vgic_hcr;
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u32 vgic_vmcr;
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u32 vgic_sre; /* Restored only, change ignored */
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u32 vgic_misr; /* Saved only */
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u32 vgic_eisr; /* Saved only */
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u32 vgic_elrsr; /* Saved only */
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u32 vgic_ap0r[4];
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u32 vgic_ap1r[4];
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u64 vgic_lr[VGIC_V3_MAX_LRS];
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#endif
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};
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struct vgic_cpu {
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/* per IRQ to LR mapping */
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u8 *vgic_irq_lr_map;
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/* Pending/active/both interrupts on this VCPU */
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DECLARE_BITMAP( pending_percpu, VGIC_NR_PRIVATE_IRQS);
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DECLARE_BITMAP( active_percpu, VGIC_NR_PRIVATE_IRQS);
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DECLARE_BITMAP( pend_act_percpu, VGIC_NR_PRIVATE_IRQS);
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/* Pending/active/both shared interrupts, dynamically sized */
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unsigned long *pending_shared;
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unsigned long *active_shared;
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unsigned long *pend_act_shared;
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/* Bitmap of used/free list registers */
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DECLARE_BITMAP( lr_used, VGIC_V2_MAX_LRS);
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/* Number of list registers on this CPU */
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int nr_lr;
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/* CPU vif control registers for world switch */
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union {
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struct vgic_v2_cpu_if vgic_v2;
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struct vgic_v3_cpu_if vgic_v3;
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};
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/* Protected by the distributor's irq_phys_map_lock */
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struct list_head irq_phys_map_list;
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};
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#define LR_EMPTY 0xff
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#define INT_STATUS_EOI (1 << 0)
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#define INT_STATUS_UNDERFLOW (1 << 1)
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struct kvm;
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struct kvm_vcpu;
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int kvm_vgic_addr(struct kvm *kvm, unsigned long type, u64 *addr, bool write);
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int kvm_vgic_hyp_init(void);
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int kvm_vgic_map_resources(struct kvm *kvm);
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int kvm_vgic_get_max_vcpus(void);
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void kvm_vgic_early_init(struct kvm *kvm);
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int kvm_vgic_create(struct kvm *kvm, u32 type);
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void kvm_vgic_destroy(struct kvm *kvm);
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void kvm_vgic_vcpu_early_init(struct kvm_vcpu *vcpu);
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void kvm_vgic_vcpu_destroy(struct kvm_vcpu *vcpu);
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void kvm_vgic_flush_hwstate(struct kvm_vcpu *vcpu);
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void kvm_vgic_sync_hwstate(struct kvm_vcpu *vcpu);
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int kvm_vgic_inject_irq(struct kvm *kvm, int cpuid, unsigned int irq_num,
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bool level);
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int kvm_vgic_inject_mapped_irq(struct kvm *kvm, int cpuid,
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struct irq_phys_map *map, bool level);
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void vgic_v3_dispatch_sgi(struct kvm_vcpu *vcpu, u64 reg);
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int kvm_vgic_vcpu_pending_irq(struct kvm_vcpu *vcpu);
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int kvm_vgic_vcpu_active_irq(struct kvm_vcpu *vcpu);
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struct irq_phys_map *kvm_vgic_map_phys_irq(struct kvm_vcpu *vcpu,
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int virt_irq, int irq);
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int kvm_vgic_unmap_phys_irq(struct kvm_vcpu *vcpu, struct irq_phys_map *map);
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bool kvm_vgic_get_phys_irq_active(struct irq_phys_map *map);
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void kvm_vgic_set_phys_irq_active(struct irq_phys_map *map, bool active);
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#define irqchip_in_kernel(k) (!!((k)->arch.vgic.in_kernel))
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#define vgic_initialized(k) (!!((k)->arch.vgic.nr_cpus))
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#define vgic_ready(k) ((k)->arch.vgic.ready)
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int vgic_v2_probe(struct device_node *vgic_node,
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const struct vgic_ops **ops,
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const struct vgic_params **params);
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#ifdef CONFIG_ARM_GIC_V3
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int vgic_v3_probe(struct device_node *vgic_node,
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const struct vgic_ops **ops,
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const struct vgic_params **params);
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#else
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static inline int vgic_v3_probe(struct device_node *vgic_node,
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const struct vgic_ops **ops,
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const struct vgic_params **params)
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{
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return -ENODEV;
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}
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#endif
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#endif
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