447 lines
10 KiB
C
447 lines
10 KiB
C
/*
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* Copyright (c) 2009-2011 Samsung Electronics Co., Ltd.
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* http://www.samsung.com
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*
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* Common Codes for S5P64X0 machines
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#include <linux/kernel.h>
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#include <linux/types.h>
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#include <linux/interrupt.h>
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#include <linux/list.h>
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#include <linux/timer.h>
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#include <linux/init.h>
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#include <linux/clk.h>
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#include <linux/io.h>
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#include <linux/device.h>
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#include <linux/serial_core.h>
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#include <linux/platform_device.h>
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#include <linux/sched.h>
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#include <linux/dma-mapping.h>
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#include <linux/gpio.h>
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#include <linux/irq.h>
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#include <asm/irq.h>
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#include <asm/proc-fns.h>
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#include <asm/system_misc.h>
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#include <asm/mach/arch.h>
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#include <asm/mach/map.h>
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#include <asm/mach/irq.h>
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#include <mach/map.h>
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#include <mach/hardware.h>
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#include <mach/regs-clock.h>
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#include <mach/regs-gpio.h>
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#include <plat/cpu.h>
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#include <plat/clock.h>
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#include <plat/devs.h>
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#include <plat/pm.h>
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#include <plat/sdhci.h>
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#include <plat/adc-core.h>
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#include <plat/fb-core.h>
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#include <plat/spi-core.h>
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#include <plat/gpio-cfg.h>
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#include <plat/regs-irqtype.h>
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#include <plat/regs-serial.h>
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#include <plat/watchdog-reset.h>
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#include "common.h"
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static const char name_s5p6440[] = "S5P6440";
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static const char name_s5p6450[] = "S5P6450";
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static struct cpu_table cpu_ids[] __initdata = {
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{
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.idcode = S5P6440_CPU_ID,
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.idmask = S5P64XX_CPU_MASK,
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.map_io = s5p6440_map_io,
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.init_clocks = s5p6440_init_clocks,
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.init_uarts = s5p6440_init_uarts,
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.init = s5p64x0_init,
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.name = name_s5p6440,
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}, {
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.idcode = S5P6450_CPU_ID,
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.idmask = S5P64XX_CPU_MASK,
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.map_io = s5p6450_map_io,
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.init_clocks = s5p6450_init_clocks,
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.init_uarts = s5p6450_init_uarts,
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.init = s5p64x0_init,
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.name = name_s5p6450,
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},
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};
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/* Initial IO mappings */
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static struct map_desc s5p64x0_iodesc[] __initdata = {
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{
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.virtual = (unsigned long)S5P_VA_CHIPID,
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.pfn = __phys_to_pfn(S5P64X0_PA_CHIPID),
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.length = SZ_4K,
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.type = MT_DEVICE,
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}, {
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.virtual = (unsigned long)S3C_VA_SYS,
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.pfn = __phys_to_pfn(S5P64X0_PA_SYSCON),
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.length = SZ_64K,
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.type = MT_DEVICE,
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}, {
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.virtual = (unsigned long)S3C_VA_TIMER,
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.pfn = __phys_to_pfn(S5P64X0_PA_TIMER),
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.length = SZ_16K,
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.type = MT_DEVICE,
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}, {
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.virtual = (unsigned long)S3C_VA_WATCHDOG,
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.pfn = __phys_to_pfn(S5P64X0_PA_WDT),
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.length = SZ_4K,
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.type = MT_DEVICE,
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}, {
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.virtual = (unsigned long)S5P_VA_SROMC,
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.pfn = __phys_to_pfn(S5P64X0_PA_SROMC),
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.length = SZ_4K,
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.type = MT_DEVICE,
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}, {
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.virtual = (unsigned long)S5P_VA_GPIO,
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.pfn = __phys_to_pfn(S5P64X0_PA_GPIO),
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.length = SZ_4K,
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.type = MT_DEVICE,
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}, {
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.virtual = (unsigned long)VA_VIC0,
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.pfn = __phys_to_pfn(S5P64X0_PA_VIC0),
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.length = SZ_16K,
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.type = MT_DEVICE,
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}, {
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.virtual = (unsigned long)VA_VIC1,
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.pfn = __phys_to_pfn(S5P64X0_PA_VIC1),
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.length = SZ_16K,
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.type = MT_DEVICE,
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},
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};
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static struct map_desc s5p6440_iodesc[] __initdata = {
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{
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.virtual = (unsigned long)S3C_VA_UART,
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.pfn = __phys_to_pfn(S5P6440_PA_UART(0)),
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.length = SZ_4K,
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.type = MT_DEVICE,
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},
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};
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static struct map_desc s5p6450_iodesc[] __initdata = {
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{
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.virtual = (unsigned long)S3C_VA_UART,
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.pfn = __phys_to_pfn(S5P6450_PA_UART(0)),
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.length = SZ_512K,
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.type = MT_DEVICE,
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}, {
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.virtual = (unsigned long)S3C_VA_UART + SZ_512K,
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.pfn = __phys_to_pfn(S5P6450_PA_UART(5)),
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.length = SZ_4K,
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.type = MT_DEVICE,
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},
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};
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static void s5p64x0_idle(void)
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{
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unsigned long val;
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val = __raw_readl(S5P64X0_PWR_CFG);
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val &= ~(0x3 << 5);
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val |= (0x1 << 5);
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__raw_writel(val, S5P64X0_PWR_CFG);
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cpu_do_idle();
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}
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/*
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* s5p64x0_map_io
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*
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* register the standard CPU IO areas
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*/
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void __init s5p64x0_init_io(struct map_desc *mach_desc, int size)
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{
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/* initialize the io descriptors we need for initialization */
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iotable_init(s5p64x0_iodesc, ARRAY_SIZE(s5p64x0_iodesc));
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if (mach_desc)
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iotable_init(mach_desc, size);
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/* detect cpu id and rev. */
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s5p_init_cpu(S5P64X0_SYS_ID);
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s3c_init_cpu(samsung_cpu_id, cpu_ids, ARRAY_SIZE(cpu_ids));
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}
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void __init s5p6440_map_io(void)
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{
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/* initialize any device information early */
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s3c_adc_setname("s3c64xx-adc");
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s3c_fb_setname("s5p64x0-fb");
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s3c64xx_spi_setname("s5p64x0-spi");
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s5p64x0_default_sdhci0();
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s5p64x0_default_sdhci1();
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s5p6440_default_sdhci2();
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iotable_init(s5p6440_iodesc, ARRAY_SIZE(s5p6440_iodesc));
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}
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void __init s5p6450_map_io(void)
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{
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/* initialize any device information early */
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s3c_adc_setname("s3c64xx-adc");
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s3c_fb_setname("s5p64x0-fb");
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s3c64xx_spi_setname("s5p64x0-spi");
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s5p64x0_default_sdhci0();
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s5p64x0_default_sdhci1();
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s5p6450_default_sdhci2();
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iotable_init(s5p6450_iodesc, ARRAY_SIZE(s5p6450_iodesc));
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}
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/*
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* s5p64x0_init_clocks
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*
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* register and setup the CPU clocks
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*/
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void __init s5p6440_init_clocks(int xtal)
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{
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printk(KERN_DEBUG "%s: initializing clocks\n", __func__);
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s3c24xx_register_baseclocks(xtal);
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s5p_register_clocks(xtal);
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s5p6440_register_clocks();
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s5p6440_setup_clocks();
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}
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void __init s5p6450_init_clocks(int xtal)
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{
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printk(KERN_DEBUG "%s: initializing clocks\n", __func__);
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s3c24xx_register_baseclocks(xtal);
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s5p_register_clocks(xtal);
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s5p6450_register_clocks();
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s5p6450_setup_clocks();
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}
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/*
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* s5p64x0_init_irq
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*
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* register the CPU interrupts
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*/
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void __init s5p6440_init_irq(void)
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{
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/* S5P6440 supports 2 VIC */
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u32 vic[2];
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/*
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* VIC0 is missing IRQ_VIC0[3, 4, 8, 10, (12-22)]
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* VIC1 is missing IRQ VIC1[1, 3, 4, 10, 11, 12, 14, 15, 22]
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*/
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vic[0] = 0xff800ae7;
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vic[1] = 0xffbf23e5;
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s5p_init_irq(vic, ARRAY_SIZE(vic));
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}
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void __init s5p6450_init_irq(void)
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{
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/* S5P6450 supports only 2 VIC */
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u32 vic[2];
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/*
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* VIC0 is missing IRQ_VIC0[(13-15), (21-22)]
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* VIC1 is missing IRQ VIC1[12, 14, 23]
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*/
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vic[0] = 0xff9f1fff;
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vic[1] = 0xff7fafff;
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s5p_init_irq(vic, ARRAY_SIZE(vic));
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}
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struct bus_type s5p64x0_subsys = {
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.name = "s5p64x0-core",
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.dev_name = "s5p64x0-core",
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};
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static struct device s5p64x0_dev = {
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.bus = &s5p64x0_subsys,
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};
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static int __init s5p64x0_core_init(void)
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{
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return subsys_system_register(&s5p64x0_subsys, NULL);
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}
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core_initcall(s5p64x0_core_init);
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int __init s5p64x0_init(void)
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{
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printk(KERN_INFO "S5P64X0(S5P6440/S5P6450): Initializing architecture\n");
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/* set idle function */
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arm_pm_idle = s5p64x0_idle;
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return device_register(&s5p64x0_dev);
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}
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/* uart registration process */
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void __init s5p6440_init_uarts(struct s3c2410_uartcfg *cfg, int no)
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{
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int uart;
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for (uart = 0; uart < no; uart++) {
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s5p_uart_resources[uart].resources->start = S5P6440_PA_UART(uart);
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s5p_uart_resources[uart].resources->end = S5P6440_PA_UART(uart) + S5P_SZ_UART;
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}
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s3c24xx_init_uartdevs("s3c6400-uart", s5p_uart_resources, cfg, no);
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}
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void __init s5p6450_init_uarts(struct s3c2410_uartcfg *cfg, int no)
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{
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s3c24xx_init_uartdevs("s3c6400-uart", s5p_uart_resources, cfg, no);
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}
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#define eint_offset(irq) ((irq) - IRQ_EINT(0))
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static int s5p64x0_irq_eint_set_type(struct irq_data *data, unsigned int type)
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{
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int offs = eint_offset(data->irq);
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int shift;
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u32 ctrl, mask;
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u32 newvalue = 0;
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if (offs > 15)
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return -EINVAL;
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switch (type) {
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case IRQ_TYPE_NONE:
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printk(KERN_WARNING "No edge setting!\n");
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break;
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case IRQ_TYPE_EDGE_RISING:
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newvalue = S3C2410_EXTINT_RISEEDGE;
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break;
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case IRQ_TYPE_EDGE_FALLING:
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newvalue = S3C2410_EXTINT_FALLEDGE;
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break;
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case IRQ_TYPE_EDGE_BOTH:
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newvalue = S3C2410_EXTINT_BOTHEDGE;
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break;
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case IRQ_TYPE_LEVEL_LOW:
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newvalue = S3C2410_EXTINT_LOWLEV;
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break;
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case IRQ_TYPE_LEVEL_HIGH:
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newvalue = S3C2410_EXTINT_HILEV;
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break;
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default:
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printk(KERN_ERR "No such irq type %d", type);
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return -EINVAL;
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}
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shift = (offs / 2) * 4;
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mask = 0x7 << shift;
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ctrl = __raw_readl(S5P64X0_EINT0CON0) & ~mask;
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ctrl |= newvalue << shift;
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__raw_writel(ctrl, S5P64X0_EINT0CON0);
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/* Configure the GPIO pin for 6450 or 6440 based on CPU ID */
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if (soc_is_s5p6450())
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s3c_gpio_cfgpin(S5P6450_GPN(offs), S3C_GPIO_SFN(2));
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else
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s3c_gpio_cfgpin(S5P6440_GPN(offs), S3C_GPIO_SFN(2));
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return 0;
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}
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/*
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* s5p64x0_irq_demux_eint
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*
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* This function demuxes the IRQ from the group0 external interrupts,
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* from IRQ_EINT(0) to IRQ_EINT(15). It is designed to be inlined into
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* the specific handlers s5p64x0_irq_demux_eintX_Y.
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*/
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static inline void s5p64x0_irq_demux_eint(unsigned int start, unsigned int end)
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{
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u32 status = __raw_readl(S5P64X0_EINT0PEND);
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u32 mask = __raw_readl(S5P64X0_EINT0MASK);
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unsigned int irq;
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status &= ~mask;
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status >>= start;
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status &= (1 << (end - start + 1)) - 1;
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for (irq = IRQ_EINT(start); irq <= IRQ_EINT(end); irq++) {
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if (status & 1)
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generic_handle_irq(irq);
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status >>= 1;
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}
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}
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static void s5p64x0_irq_demux_eint0_3(unsigned int irq, struct irq_desc *desc)
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{
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s5p64x0_irq_demux_eint(0, 3);
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}
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static void s5p64x0_irq_demux_eint4_11(unsigned int irq, struct irq_desc *desc)
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{
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s5p64x0_irq_demux_eint(4, 11);
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}
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static void s5p64x0_irq_demux_eint12_15(unsigned int irq,
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struct irq_desc *desc)
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{
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s5p64x0_irq_demux_eint(12, 15);
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}
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static int s5p64x0_alloc_gc(void)
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{
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struct irq_chip_generic *gc;
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struct irq_chip_type *ct;
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gc = irq_alloc_generic_chip("s5p64x0-eint", 1, S5P_IRQ_EINT_BASE,
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S5P_VA_GPIO, handle_level_irq);
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if (!gc) {
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printk(KERN_ERR "%s: irq_alloc_generic_chip for group 0"
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"external interrupts failed\n", __func__);
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return -EINVAL;
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}
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ct = gc->chip_types;
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ct->chip.irq_ack = irq_gc_ack_set_bit;
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ct->chip.irq_mask = irq_gc_mask_set_bit;
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ct->chip.irq_unmask = irq_gc_mask_clr_bit;
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ct->chip.irq_set_type = s5p64x0_irq_eint_set_type;
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ct->chip.irq_set_wake = s3c_irqext_wake;
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ct->regs.ack = EINT0PEND_OFFSET;
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ct->regs.mask = EINT0MASK_OFFSET;
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irq_setup_generic_chip(gc, IRQ_MSK(16), IRQ_GC_INIT_MASK_CACHE,
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IRQ_NOREQUEST | IRQ_NOPROBE, 0);
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return 0;
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}
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static int __init s5p64x0_init_irq_eint(void)
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{
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int ret = s5p64x0_alloc_gc();
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irq_set_chained_handler(IRQ_EINT0_3, s5p64x0_irq_demux_eint0_3);
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irq_set_chained_handler(IRQ_EINT4_11, s5p64x0_irq_demux_eint4_11);
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irq_set_chained_handler(IRQ_EINT12_15, s5p64x0_irq_demux_eint12_15);
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return ret;
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}
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arch_initcall(s5p64x0_init_irq_eint);
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void s5p64x0_restart(char mode, const char *cmd)
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{
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if (mode != 's')
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arch_wdt_reset();
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soft_restart(0);
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}
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