158 lines
4.1 KiB
C
158 lines
4.1 KiB
C
#ifndef _DMA_REMAPPING_H
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#define _DMA_REMAPPING_H
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/*
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* We need a fixed PAGE_SIZE of 4K irrespective of
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* arch PAGE_SIZE for IOMMU page tables.
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*/
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#define PAGE_SHIFT_4K (12)
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#define PAGE_SIZE_4K (1UL << PAGE_SHIFT_4K)
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#define PAGE_MASK_4K (((u64)-1) << PAGE_SHIFT_4K)
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#define PAGE_ALIGN_4K(addr) (((addr) + PAGE_SIZE_4K - 1) & PAGE_MASK_4K)
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#define IOVA_PFN(addr) ((addr) >> PAGE_SHIFT_4K)
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#define DMA_32BIT_PFN IOVA_PFN(DMA_32BIT_MASK)
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#define DMA_64BIT_PFN IOVA_PFN(DMA_64BIT_MASK)
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/*
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* 0: Present
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* 1-11: Reserved
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* 12-63: Context Ptr (12 - (haw-1))
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* 64-127: Reserved
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*/
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struct root_entry {
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u64 val;
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u64 rsvd1;
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};
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#define ROOT_ENTRY_NR (PAGE_SIZE_4K/sizeof(struct root_entry))
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static inline bool root_present(struct root_entry *root)
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{
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return (root->val & 1);
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}
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static inline void set_root_present(struct root_entry *root)
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{
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root->val |= 1;
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}
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static inline void set_root_value(struct root_entry *root, unsigned long value)
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{
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root->val |= value & PAGE_MASK_4K;
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}
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struct context_entry;
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static inline struct context_entry *
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get_context_addr_from_root(struct root_entry *root)
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{
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return (struct context_entry *)
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(root_present(root)?phys_to_virt(
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root->val & PAGE_MASK_4K):
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NULL);
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}
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/*
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* low 64 bits:
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* 0: present
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* 1: fault processing disable
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* 2-3: translation type
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* 12-63: address space root
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* high 64 bits:
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* 0-2: address width
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* 3-6: aval
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* 8-23: domain id
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*/
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struct context_entry {
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u64 lo;
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u64 hi;
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};
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#define context_present(c) ((c).lo & 1)
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#define context_fault_disable(c) (((c).lo >> 1) & 1)
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#define context_translation_type(c) (((c).lo >> 2) & 3)
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#define context_address_root(c) ((c).lo & PAGE_MASK_4K)
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#define context_address_width(c) ((c).hi & 7)
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#define context_domain_id(c) (((c).hi >> 8) & ((1 << 16) - 1))
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#define context_set_present(c) do {(c).lo |= 1;} while (0)
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#define context_set_fault_enable(c) \
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do {(c).lo &= (((u64)-1) << 2) | 1;} while (0)
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#define context_set_translation_type(c, val) \
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do { \
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(c).lo &= (((u64)-1) << 4) | 3; \
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(c).lo |= ((val) & 3) << 2; \
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} while (0)
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#define CONTEXT_TT_MULTI_LEVEL 0
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#define context_set_address_root(c, val) \
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do {(c).lo |= (val) & PAGE_MASK_4K;} while (0)
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#define context_set_address_width(c, val) do {(c).hi |= (val) & 7;} while (0)
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#define context_set_domain_id(c, val) \
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do {(c).hi |= ((val) & ((1 << 16) - 1)) << 8;} while (0)
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#define context_clear_entry(c) do {(c).lo = 0; (c).hi = 0;} while (0)
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/*
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* 0: readable
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* 1: writable
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* 2-6: reserved
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* 7: super page
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* 8-11: available
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* 12-63: Host physcial address
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*/
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struct dma_pte {
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u64 val;
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};
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#define dma_clear_pte(p) do {(p).val = 0;} while (0)
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#define DMA_PTE_READ (1)
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#define DMA_PTE_WRITE (2)
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#define dma_set_pte_readable(p) do {(p).val |= DMA_PTE_READ;} while (0)
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#define dma_set_pte_writable(p) do {(p).val |= DMA_PTE_WRITE;} while (0)
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#define dma_set_pte_prot(p, prot) \
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do {(p).val = ((p).val & ~3) | ((prot) & 3); } while (0)
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#define dma_pte_addr(p) ((p).val & PAGE_MASK_4K)
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#define dma_set_pte_addr(p, addr) do {\
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(p).val |= ((addr) & PAGE_MASK_4K); } while (0)
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#define dma_pte_present(p) (((p).val & 3) != 0)
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struct intel_iommu;
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struct dmar_domain {
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int id; /* domain id */
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struct intel_iommu *iommu; /* back pointer to owning iommu */
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struct list_head devices; /* all devices' list */
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struct iova_domain iovad; /* iova's that belong to this domain */
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struct dma_pte *pgd; /* virtual address */
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spinlock_t mapping_lock; /* page table lock */
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int gaw; /* max guest address width */
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/* adjusted guest address width, 0 is level 2 30-bit */
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int agaw;
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#define DOMAIN_FLAG_MULTIPLE_DEVICES 1
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int flags;
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};
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/* PCI domain-device relationship */
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struct device_domain_info {
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struct list_head link; /* link to domain siblings */
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struct list_head global; /* link to global list */
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u8 bus; /* PCI bus numer */
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u8 devfn; /* PCI devfn number */
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struct pci_dev *dev; /* it's NULL for PCIE-to-PCI bridge */
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struct dmar_domain *domain; /* pointer to domain */
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};
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extern int init_dmars(void);
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extern void free_dmar_iommu(struct intel_iommu *iommu);
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extern int dmar_disabled;
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#ifndef CONFIG_DMAR_GFX_WA
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static inline void iommu_prepare_gfx_mapping(void)
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{
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return;
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}
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#endif /* !CONFIG_DMAR_GFX_WA */
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#endif
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