269 lines
9.2 KiB
C
269 lines
9.2 KiB
C
/*
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* Copyright 2010 Ben Herrenschmidt, IBM Corporation
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version
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* 2 of the License, or (at your option) any later version.
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*/
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#ifndef __WSP_PCI_H
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#define __WSP_PCI_H
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/* Architected registers */
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#define PCIE_REG_DMA_CHAN_STATUS 0x110
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#define PCIE_REG_CPU_LOADSTORE_STATUS 0x120
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#define PCIE_REG_CONFIG_DATA 0x130
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#define PCIE_REG_LOCK0 0x138
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#define PCIE_REG_CONFIG_ADDRESS 0x140
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#define PCIE_REG_CA_ENABLE 0x8000000000000000ull
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#define PCIE_REG_CA_BUS_MASK 0x0ff0000000000000ull
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#define PCIE_REG_CA_BUS_SHIFT (20+32)
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#define PCIE_REG_CA_DEV_MASK 0x000f800000000000ull
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#define PCIE_REG_CA_DEV_SHIFT (15+32)
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#define PCIE_REG_CA_FUNC_MASK 0x0000700000000000ull
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#define PCIE_REG_CA_FUNC_SHIFT (12+32)
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#define PCIE_REG_CA_REG_MASK 0x00000fff00000000ull
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#define PCIE_REG_CA_REG_SHIFT ( 0+32)
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#define PCIE_REG_CA_BE_MASK 0x00000000f0000000ull
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#define PCIE_REG_CA_BE_SHIFT ( 28)
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#define PCIE_REG_LOCK1 0x148
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#define PCIE_REG_PHB_CONFIG 0x160
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#define PCIE_REG_PHBC_64B_TCE_EN 0x2000000000000000ull
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#define PCIE_REG_PHBC_MMIO_DMA_FREEZE_EN 0x1000000000000000ull
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#define PCIE_REG_PHBC_32BIT_MSI_EN 0x0080000000000000ull
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#define PCIE_REG_PHBC_M64_EN 0x0040000000000000ull
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#define PCIE_REG_PHBC_IO_EN 0x0008000000000000ull
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#define PCIE_REG_PHBC_64BIT_MSI_EN 0x0002000000000000ull
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#define PCIE_REG_PHBC_M32A_EN 0x0000800000000000ull
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#define PCIE_REG_PHBC_M32B_EN 0x0000400000000000ull
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#define PCIE_REG_PHBC_MSI_PE_VALIDATE 0x0000200000000000ull
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#define PCIE_REG_PHBC_DMA_XLATE_BYPASS 0x0000100000000000ull
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#define PCIE_REG_IO_BASE_ADDR 0x170
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#define PCIE_REG_IO_BASE_MASK 0x178
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#define PCIE_REG_IO_START_ADDR 0x180
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#define PCIE_REG_M32A_BASE_ADDR 0x190
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#define PCIE_REG_M32A_BASE_MASK 0x198
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#define PCIE_REG_M32A_START_ADDR 0x1a0
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#define PCIE_REG_M32B_BASE_ADDR 0x1b0
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#define PCIE_REG_M32B_BASE_MASK 0x1b8
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#define PCIE_REG_M32B_START_ADDR 0x1c0
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#define PCIE_REG_M64_BASE_ADDR 0x1e0
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#define PCIE_REG_M64_BASE_MASK 0x1e8
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#define PCIE_REG_M64_START_ADDR 0x1f0
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#define PCIE_REG_TCE_KILL 0x210
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#define PCIE_REG_TCEKILL_SINGLE 0x8000000000000000ull
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#define PCIE_REG_TCEKILL_ADDR_MASK 0x000003fffffffff8ull
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#define PCIE_REG_TCEKILL_PS_4K 0
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#define PCIE_REG_TCEKILL_PS_64K 1
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#define PCIE_REG_TCEKILL_PS_16M 2
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#define PCIE_REG_TCEKILL_PS_16G 3
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#define PCIE_REG_IODA_ADDR 0x220
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#define PCIE_REG_IODA_AD_AUTOINC 0x8000000000000000ull
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#define PCIE_REG_IODA_AD_TBL_MVT 0x0005000000000000ull
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#define PCIE_REG_IODA_AD_TBL_PELT 0x0006000000000000ull
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#define PCIE_REG_IODA_AD_TBL_PESTA 0x0007000000000000ull
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#define PCIE_REG_IODA_AD_TBL_PESTB 0x0008000000000000ull
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#define PCIE_REG_IODA_AD_TBL_TVT 0x0009000000000000ull
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#define PCIE_REG_IODA_AD_TBL_TCE 0x000a000000000000ull
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#define PCIE_REG_IODA_DATA0 0x228
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#define PCIE_REG_IODA_DATA1 0x230
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#define PCIE_REG_LOCK2 0x240
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#define PCIE_REG_PHB_GEN_CAP 0x250
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#define PCIE_REG_PHB_TCE_CAP 0x258
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#define PCIE_REG_PHB_IRQ_CAP 0x260
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#define PCIE_REG_PHB_EEH_CAP 0x268
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#define PCIE_REG_PAPR_ERR_INJ_CONTROL 0x2b0
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#define PCIE_REG_PAPR_ERR_INJ_ADDR 0x2b8
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#define PCIE_REG_PAPR_ERR_INJ_MASK 0x2c0
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#define PCIE_REG_SYS_CFG1 0x600
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#define PCIE_REG_SYS_CFG1_CLASS_CODE 0x0000000000ffffffull
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#define IODA_TVT0_TTA_MASK 0x000fffffffff0000ull
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#define IODA_TVT0_TTA_SHIFT 4
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#define IODA_TVT0_BUSNUM_VALID_MASK 0x000000000000e000ull
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#define IODA_TVT0_TCE_TABLE_SIZE_MASK 0x0000000000001f00ull
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#define IODA_TVT0_TCE_TABLE_SIZE_SHIFT 8
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#define IODA_TVT0_BUSNUM_VALUE_MASK 0x00000000000000ffull
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#define IODA_TVT0_BUSNUM_VALID_SHIFT 0
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#define IODA_TVT1_DEVNUM_VALID 0x2000000000000000ull
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#define IODA_TVT1_DEVNUM_VALUE_MASK 0x1f00000000000000ull
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#define IODA_TVT1_DEVNUM_VALUE_SHIFT 56
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#define IODA_TVT1_FUNCNUM_VALID 0x0008000000000000ull
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#define IODA_TVT1_FUNCNUM_VALUE_MASK 0x0007000000000000ull
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#define IODA_TVT1_FUNCNUM_VALUE_SHIFT 48
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#define IODA_TVT1_IO_PAGE_SIZE_MASK 0x00001f0000000000ull
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#define IODA_TVT1_IO_PAGE_SIZE_SHIFT 40
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#define IODA_TVT1_PE_NUMBER_MASK 0x000000000000003full
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#define IODA_TVT1_PE_NUMBER_SHIFT 0
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#define IODA_TVT_COUNT 64
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/* UTL Core registers */
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#define PCIE_UTL_SYS_BUS_CONTROL 0x400
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#define PCIE_UTL_STATUS 0x408
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#define PCIE_UTL_SYS_BUS_AGENT_STATUS 0x410
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#define PCIE_UTL_SYS_BUS_AGENT_ERR_SEV 0x418
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#define PCIE_UTL_SYS_BUS_AGENT_IRQ_EN 0x420
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#define PCIE_UTL_SYS_BUS_BURST_SZ_CONF 0x440
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#define PCIE_UTL_REVISION_ID 0x448
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#define PCIE_UTL_OUT_POST_HDR_BUF_ALLOC 0x4c0
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#define PCIE_UTL_OUT_POST_DAT_BUF_ALLOC 0x4d0
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#define PCIE_UTL_IN_POST_HDR_BUF_ALLOC 0x4e0
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#define PCIE_UTL_IN_POST_DAT_BUF_ALLOC 0x4f0
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#define PCIE_UTL_OUT_NP_BUF_ALLOC 0x500
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#define PCIE_UTL_IN_NP_BUF_ALLOC 0x510
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#define PCIE_UTL_PCIE_TAGS_ALLOC 0x520
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#define PCIE_UTL_GBIF_READ_TAGS_ALLOC 0x530
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#define PCIE_UTL_PCIE_PORT_CONTROL 0x540
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#define PCIE_UTL_PCIE_PORT_STATUS 0x548
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#define PCIE_UTL_PCIE_PORT_ERROR_SEV 0x550
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#define PCIE_UTL_PCIE_PORT_IRQ_EN 0x558
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#define PCIE_UTL_RC_STATUS 0x560
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#define PCIE_UTL_RC_ERR_SEVERITY 0x568
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#define PCIE_UTL_RC_IRQ_EN 0x570
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#define PCIE_UTL_EP_STATUS 0x578
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#define PCIE_UTL_EP_ERR_SEVERITY 0x580
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#define PCIE_UTL_EP_ERR_IRQ_EN 0x588
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#define PCIE_UTL_PCI_PM_CTRL1 0x590
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#define PCIE_UTL_PCI_PM_CTRL2 0x598
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/* PCIe stack registers */
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#define PCIE_REG_SYSTEM_CONFIG1 0x600
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#define PCIE_REG_SYSTEM_CONFIG2 0x608
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#define PCIE_REG_EP_SYSTEM_CONFIG 0x618
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#define PCIE_REG_EP_FLR 0x620
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#define PCIE_REG_EP_BAR_CONFIG 0x628
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#define PCIE_REG_LINK_CONFIG 0x630
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#define PCIE_REG_PM_CONFIG 0x640
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#define PCIE_REG_DLP_CONTROL 0x650
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#define PCIE_REG_DLP_STATUS 0x658
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#define PCIE_REG_ERR_REPORT_CONTROL 0x660
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#define PCIE_REG_SLOT_CONTROL1 0x670
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#define PCIE_REG_SLOT_CONTROL2 0x678
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#define PCIE_REG_UTL_CONFIG 0x680
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#define PCIE_REG_BUFFERS_CONFIG 0x690
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#define PCIE_REG_ERROR_INJECT 0x698
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#define PCIE_REG_SRIOV_CONFIG 0x6a0
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#define PCIE_REG_PF0_SRIOV_STATUS 0x6a8
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#define PCIE_REG_PF1_SRIOV_STATUS 0x6b0
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#define PCIE_REG_PORT_NUMBER 0x700
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#define PCIE_REG_POR_SYSTEM_CONFIG 0x708
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/* PHB internal logic registers */
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#define PCIE_REG_PHB_VERSION 0x800
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#define PCIE_REG_RESET 0x808
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#define PCIE_REG_PHB_CONTROL 0x810
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#define PCIE_REG_PHB_TIMEOUT_CONTROL1 0x878
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#define PCIE_REG_PHB_QUIESCE_DMA 0x888
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#define PCIE_REG_PHB_DMA_READ_TAG_ACTV 0x900
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#define PCIE_REG_PHB_TCE_READ_TAG_ACTV 0x908
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/* FIR registers */
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#define PCIE_REG_LEM_FIR_ACCUM 0xc00
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#define PCIE_REG_LEM_FIR_AND_MASK 0xc08
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#define PCIE_REG_LEM_FIR_OR_MASK 0xc10
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#define PCIE_REG_LEM_ACTION0 0xc18
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#define PCIE_REG_LEM_ACTION1 0xc20
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#define PCIE_REG_LEM_ERROR_MASK 0xc30
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#define PCIE_REG_LEM_ERROR_AND_MASK 0xc38
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#define PCIE_REG_LEM_ERROR_OR_MASK 0xc40
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/* PHB Error registers */
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#define PCIE_REG_PHB_ERR_STATUS 0xc80
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#define PCIE_REG_PHB_ERR1_STATUS 0xc88
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#define PCIE_REG_PHB_ERR_INJECT 0xc90
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#define PCIE_REG_PHB_ERR_LEM_ENABLE 0xc98
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#define PCIE_REG_PHB_ERR_IRQ_ENABLE 0xca0
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#define PCIE_REG_PHB_ERR_FREEZE_ENABLE 0xca8
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#define PCIE_REG_PHB_ERR_SIDE_ENABLE 0xcb8
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#define PCIE_REG_PHB_ERR_LOG_0 0xcc0
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#define PCIE_REG_PHB_ERR_LOG_1 0xcc8
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#define PCIE_REG_PHB_ERR_STATUS_MASK 0xcd0
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#define PCIE_REG_PHB_ERR1_STATUS_MASK 0xcd8
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#define PCIE_REG_MMIO_ERR_STATUS 0xd00
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#define PCIE_REG_MMIO_ERR1_STATUS 0xd08
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#define PCIE_REG_MMIO_ERR_INJECT 0xd10
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#define PCIE_REG_MMIO_ERR_LEM_ENABLE 0xd18
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#define PCIE_REG_MMIO_ERR_IRQ_ENABLE 0xd20
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#define PCIE_REG_MMIO_ERR_FREEZE_ENABLE 0xd28
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#define PCIE_REG_MMIO_ERR_SIDE_ENABLE 0xd38
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#define PCIE_REG_MMIO_ERR_LOG_0 0xd40
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#define PCIE_REG_MMIO_ERR_LOG_1 0xd48
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#define PCIE_REG_MMIO_ERR_STATUS_MASK 0xd50
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#define PCIE_REG_MMIO_ERR1_STATUS_MASK 0xd58
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#define PCIE_REG_DMA_ERR_STATUS 0xd80
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#define PCIE_REG_DMA_ERR1_STATUS 0xd88
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#define PCIE_REG_DMA_ERR_INJECT 0xd90
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#define PCIE_REG_DMA_ERR_LEM_ENABLE 0xd98
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#define PCIE_REG_DMA_ERR_IRQ_ENABLE 0xda0
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#define PCIE_REG_DMA_ERR_FREEZE_ENABLE 0xda8
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#define PCIE_REG_DMA_ERR_SIDE_ENABLE 0xdb8
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#define PCIE_REG_DMA_ERR_LOG_0 0xdc0
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#define PCIE_REG_DMA_ERR_LOG_1 0xdc8
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#define PCIE_REG_DMA_ERR_STATUS_MASK 0xdd0
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#define PCIE_REG_DMA_ERR1_STATUS_MASK 0xdd8
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/* Shortcuts for access to the above using the PHB definitions
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* with an offset
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*/
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#define PCIE_REG_ERR_PHB_OFFSET 0x0
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#define PCIE_REG_ERR_MMIO_OFFSET 0x80
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#define PCIE_REG_ERR_DMA_OFFSET 0x100
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/* Debug and Trace registers */
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#define PCIE_REG_PHB_DEBUG_CONTROL0 0xe00
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#define PCIE_REG_PHB_DEBUG_STATUS0 0xe08
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#define PCIE_REG_PHB_DEBUG_CONTROL1 0xe10
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#define PCIE_REG_PHB_DEBUG_STATUS1 0xe18
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#define PCIE_REG_PHB_DEBUG_CONTROL2 0xe20
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#define PCIE_REG_PHB_DEBUG_STATUS2 0xe28
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#define PCIE_REG_PHB_DEBUG_CONTROL3 0xe30
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#define PCIE_REG_PHB_DEBUG_STATUS3 0xe38
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#define PCIE_REG_PHB_DEBUG_CONTROL4 0xe40
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#define PCIE_REG_PHB_DEBUG_STATUS4 0xe48
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#define PCIE_REG_PHB_DEBUG_CONTROL5 0xe50
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#define PCIE_REG_PHB_DEBUG_STATUS5 0xe58
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#define PCIE_REG_PHB_DEBUG_CONTROL6 0xe60
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#define PCIE_REG_PHB_DEBUG_STATUS6 0xe68
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/* Definition for PCIe errors */
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struct wsp_pcie_err_log_data {
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__u64 phb_err;
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__u64 phb_err1;
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__u64 phb_log0;
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__u64 phb_log1;
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__u64 mmio_err;
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__u64 mmio_err1;
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__u64 mmio_log0;
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__u64 mmio_log1;
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__u64 dma_err;
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__u64 dma_err1;
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__u64 dma_log0;
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__u64 dma_log1;
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__u64 utl_sys_err;
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__u64 utl_port_err;
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__u64 utl_rc_err;
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__u64 unused;
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};
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#endif /* __WSP_PCI_H */
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