395 lines
9.5 KiB
C
395 lines
9.5 KiB
C
/*
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* Format of an instruction in memory.
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*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*
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* Copyright (C) 1996, 2000 by Ralf Baechle
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* Copyright (C) 2006 by Thiemo Seufer
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*/
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#ifndef _ASM_INST_H
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#define _ASM_INST_H
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/*
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* Major opcodes; before MIPS IV cop1x was called cop3.
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*/
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enum major_op {
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spec_op, bcond_op, j_op, jal_op,
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beq_op, bne_op, blez_op, bgtz_op,
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addi_op, addiu_op, slti_op, sltiu_op,
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andi_op, ori_op, xori_op, lui_op,
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cop0_op, cop1_op, cop2_op, cop1x_op,
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beql_op, bnel_op, blezl_op, bgtzl_op,
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daddi_op, daddiu_op, ldl_op, ldr_op,
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spec2_op, jalx_op, mdmx_op, spec3_op,
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lb_op, lh_op, lwl_op, lw_op,
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lbu_op, lhu_op, lwr_op, lwu_op,
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sb_op, sh_op, swl_op, sw_op,
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sdl_op, sdr_op, swr_op, cache_op,
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ll_op, lwc1_op, lwc2_op, pref_op,
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lld_op, ldc1_op, ldc2_op, ld_op,
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sc_op, swc1_op, swc2_op, major_3b_op,
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scd_op, sdc1_op, sdc2_op, sd_op
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};
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/*
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* func field of spec opcode.
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*/
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enum spec_op {
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sll_op, movc_op, srl_op, sra_op,
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sllv_op, pmon_op, srlv_op, srav_op,
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jr_op, jalr_op, movz_op, movn_op,
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syscall_op, break_op, spim_op, sync_op,
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mfhi_op, mthi_op, mflo_op, mtlo_op,
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dsllv_op, spec2_unused_op, dsrlv_op, dsrav_op,
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mult_op, multu_op, div_op, divu_op,
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dmult_op, dmultu_op, ddiv_op, ddivu_op,
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add_op, addu_op, sub_op, subu_op,
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and_op, or_op, xor_op, nor_op,
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spec3_unused_op, spec4_unused_op, slt_op, sltu_op,
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dadd_op, daddu_op, dsub_op, dsubu_op,
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tge_op, tgeu_op, tlt_op, tltu_op,
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teq_op, spec5_unused_op, tne_op, spec6_unused_op,
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dsll_op, spec7_unused_op, dsrl_op, dsra_op,
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dsll32_op, spec8_unused_op, dsrl32_op, dsra32_op
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};
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/*
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* func field of spec2 opcode.
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*/
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enum spec2_op {
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madd_op, maddu_op, mul_op, spec2_3_unused_op,
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msub_op, msubu_op, /* more unused ops */
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clz_op = 0x20, clo_op,
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dclz_op = 0x24, dclo_op,
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sdbpp_op = 0x3f
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};
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/*
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* func field of spec3 opcode.
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*/
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enum spec3_op {
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ext_op, dextm_op, dextu_op, dext_op,
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ins_op, dinsm_op, dinsu_op, dins_op,
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bshfl_op = 0x20,
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dbshfl_op = 0x24,
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rdhwr_op = 0x3b
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};
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/*
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* rt field of bcond opcodes.
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*/
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enum rt_op {
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bltz_op, bgez_op, bltzl_op, bgezl_op,
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spimi_op, unused_rt_op_0x05, unused_rt_op_0x06, unused_rt_op_0x07,
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tgei_op, tgeiu_op, tlti_op, tltiu_op,
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teqi_op, unused_0x0d_rt_op, tnei_op, unused_0x0f_rt_op,
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bltzal_op, bgezal_op, bltzall_op, bgezall_op,
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rt_op_0x14, rt_op_0x15, rt_op_0x16, rt_op_0x17,
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rt_op_0x18, rt_op_0x19, rt_op_0x1a, rt_op_0x1b,
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bposge32_op, rt_op_0x1d, rt_op_0x1e, rt_op_0x1f
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};
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/*
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* rs field of cop opcodes.
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*/
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enum cop_op {
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mfc_op = 0x00, dmfc_op = 0x01,
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cfc_op = 0x02, mtc_op = 0x04,
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dmtc_op = 0x05, ctc_op = 0x06,
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bc_op = 0x08, cop_op = 0x10,
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copm_op = 0x18
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};
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/*
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* rt field of cop.bc_op opcodes
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*/
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enum bcop_op {
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bcf_op, bct_op, bcfl_op, bctl_op
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};
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/*
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* func field of cop0 coi opcodes.
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*/
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enum cop0_coi_func {
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tlbr_op = 0x01, tlbwi_op = 0x02,
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tlbwr_op = 0x06, tlbp_op = 0x08,
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rfe_op = 0x10, eret_op = 0x18
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};
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/*
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* func field of cop0 com opcodes.
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*/
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enum cop0_com_func {
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tlbr1_op = 0x01, tlbw_op = 0x02,
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tlbp1_op = 0x08, dctr_op = 0x09,
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dctw_op = 0x0a
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};
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/*
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* fmt field of cop1 opcodes.
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*/
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enum cop1_fmt {
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s_fmt, d_fmt, e_fmt, q_fmt,
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w_fmt, l_fmt
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};
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/*
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* func field of cop1 instructions using d, s or w format.
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*/
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enum cop1_sdw_func {
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fadd_op = 0x00, fsub_op = 0x01,
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fmul_op = 0x02, fdiv_op = 0x03,
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fsqrt_op = 0x04, fabs_op = 0x05,
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fmov_op = 0x06, fneg_op = 0x07,
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froundl_op = 0x08, ftruncl_op = 0x09,
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fceill_op = 0x0a, ffloorl_op = 0x0b,
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fround_op = 0x0c, ftrunc_op = 0x0d,
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fceil_op = 0x0e, ffloor_op = 0x0f,
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fmovc_op = 0x11, fmovz_op = 0x12,
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fmovn_op = 0x13, frecip_op = 0x15,
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frsqrt_op = 0x16, fcvts_op = 0x20,
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fcvtd_op = 0x21, fcvte_op = 0x22,
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fcvtw_op = 0x24, fcvtl_op = 0x25,
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fcmp_op = 0x30
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};
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/*
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* func field of cop1x opcodes (MIPS IV).
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*/
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enum cop1x_func {
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lwxc1_op = 0x00, ldxc1_op = 0x01,
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pfetch_op = 0x07, swxc1_op = 0x08,
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sdxc1_op = 0x09, madd_s_op = 0x20,
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madd_d_op = 0x21, madd_e_op = 0x22,
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msub_s_op = 0x28, msub_d_op = 0x29,
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msub_e_op = 0x2a, nmadd_s_op = 0x30,
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nmadd_d_op = 0x31, nmadd_e_op = 0x32,
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nmsub_s_op = 0x38, nmsub_d_op = 0x39,
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nmsub_e_op = 0x3a
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};
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/*
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* func field for mad opcodes (MIPS IV).
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*/
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enum mad_func {
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madd_fp_op = 0x08, msub_fp_op = 0x0a,
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nmadd_fp_op = 0x0c, nmsub_fp_op = 0x0e
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};
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/*
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* Damn ... bitfields depend from byteorder :-(
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*/
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#ifdef __MIPSEB__
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struct j_format { /* Jump format */
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unsigned int opcode : 6;
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unsigned int target : 26;
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};
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struct i_format { /* Immediate format (addi, lw, ...) */
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unsigned int opcode : 6;
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unsigned int rs : 5;
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unsigned int rt : 5;
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signed int simmediate : 16;
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};
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struct u_format { /* Unsigned immediate format (ori, xori, ...) */
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unsigned int opcode : 6;
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unsigned int rs : 5;
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unsigned int rt : 5;
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unsigned int uimmediate : 16;
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};
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struct c_format { /* Cache (>= R6000) format */
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unsigned int opcode : 6;
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unsigned int rs : 5;
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unsigned int c_op : 3;
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unsigned int cache : 2;
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unsigned int simmediate : 16;
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};
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struct r_format { /* Register format */
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unsigned int opcode : 6;
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unsigned int rs : 5;
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unsigned int rt : 5;
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unsigned int rd : 5;
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unsigned int re : 5;
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unsigned int func : 6;
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};
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struct p_format { /* Performance counter format (R10000) */
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unsigned int opcode : 6;
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unsigned int rs : 5;
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unsigned int rt : 5;
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unsigned int rd : 5;
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unsigned int re : 5;
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unsigned int func : 6;
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};
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struct f_format { /* FPU register format */
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unsigned int opcode : 6;
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unsigned int : 1;
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unsigned int fmt : 4;
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unsigned int rt : 5;
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unsigned int rd : 5;
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unsigned int re : 5;
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unsigned int func : 6;
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};
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struct ma_format { /* FPU multipy and add format (MIPS IV) */
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unsigned int opcode : 6;
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unsigned int fr : 5;
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unsigned int ft : 5;
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unsigned int fs : 5;
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unsigned int fd : 5;
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unsigned int func : 4;
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unsigned int fmt : 2;
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};
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#elif defined(__MIPSEL__)
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struct j_format { /* Jump format */
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unsigned int target : 26;
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unsigned int opcode : 6;
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};
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struct i_format { /* Immediate format */
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signed int simmediate : 16;
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unsigned int rt : 5;
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unsigned int rs : 5;
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unsigned int opcode : 6;
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};
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struct u_format { /* Unsigned immediate format */
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unsigned int uimmediate : 16;
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unsigned int rt : 5;
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unsigned int rs : 5;
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unsigned int opcode : 6;
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};
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struct c_format { /* Cache (>= R6000) format */
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unsigned int simmediate : 16;
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unsigned int cache : 2;
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unsigned int c_op : 3;
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unsigned int rs : 5;
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unsigned int opcode : 6;
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};
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struct r_format { /* Register format */
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unsigned int func : 6;
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unsigned int re : 5;
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unsigned int rd : 5;
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unsigned int rt : 5;
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unsigned int rs : 5;
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unsigned int opcode : 6;
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};
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struct p_format { /* Performance counter format (R10000) */
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unsigned int func : 6;
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unsigned int re : 5;
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unsigned int rd : 5;
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unsigned int rt : 5;
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unsigned int rs : 5;
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unsigned int opcode : 6;
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};
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struct f_format { /* FPU register format */
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unsigned int func : 6;
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unsigned int re : 5;
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unsigned int rd : 5;
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unsigned int rt : 5;
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unsigned int fmt : 4;
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unsigned int : 1;
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unsigned int opcode : 6;
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};
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struct ma_format { /* FPU multipy and add format (MIPS IV) */
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unsigned int fmt : 2;
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unsigned int func : 4;
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unsigned int fd : 5;
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unsigned int fs : 5;
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unsigned int ft : 5;
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unsigned int fr : 5;
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unsigned int opcode : 6;
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};
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#else /* !defined (__MIPSEB__) && !defined (__MIPSEL__) */
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#error "MIPS but neither __MIPSEL__ nor __MIPSEB__?"
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#endif
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union mips_instruction {
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unsigned int word;
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unsigned short halfword[2];
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unsigned char byte[4];
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struct j_format j_format;
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struct i_format i_format;
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struct u_format u_format;
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struct c_format c_format;
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struct r_format r_format;
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struct f_format f_format;
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struct ma_format ma_format;
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};
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/* HACHACHAHCAHC ... */
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/* In case some other massaging is needed, keep MIPSInst as wrapper */
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#define MIPSInst(x) x
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#define I_OPCODE_SFT 26
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#define MIPSInst_OPCODE(x) (MIPSInst(x) >> I_OPCODE_SFT)
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#define I_JTARGET_SFT 0
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#define MIPSInst_JTARGET(x) (MIPSInst(x) & 0x03ffffff)
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#define I_RS_SFT 21
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#define MIPSInst_RS(x) ((MIPSInst(x) & 0x03e00000) >> I_RS_SFT)
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#define I_RT_SFT 16
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#define MIPSInst_RT(x) ((MIPSInst(x) & 0x001f0000) >> I_RT_SFT)
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#define I_IMM_SFT 0
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#define MIPSInst_SIMM(x) ((int)((short)(MIPSInst(x) & 0xffff)))
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#define MIPSInst_UIMM(x) (MIPSInst(x) & 0xffff)
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#define I_CACHEOP_SFT 18
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#define MIPSInst_CACHEOP(x) ((MIPSInst(x) & 0x001c0000) >> I_CACHEOP_SFT)
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#define I_CACHESEL_SFT 16
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#define MIPSInst_CACHESEL(x) ((MIPSInst(x) & 0x00030000) >> I_CACHESEL_SFT)
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#define I_RD_SFT 11
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#define MIPSInst_RD(x) ((MIPSInst(x) & 0x0000f800) >> I_RD_SFT)
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#define I_RE_SFT 6
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#define MIPSInst_RE(x) ((MIPSInst(x) & 0x000007c0) >> I_RE_SFT)
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#define I_FUNC_SFT 0
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#define MIPSInst_FUNC(x) (MIPSInst(x) & 0x0000003f)
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#define I_FFMT_SFT 21
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#define MIPSInst_FFMT(x) ((MIPSInst(x) & 0x01e00000) >> I_FFMT_SFT)
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#define I_FT_SFT 16
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#define MIPSInst_FT(x) ((MIPSInst(x) & 0x001f0000) >> I_FT_SFT)
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#define I_FS_SFT 11
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#define MIPSInst_FS(x) ((MIPSInst(x) & 0x0000f800) >> I_FS_SFT)
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#define I_FD_SFT 6
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#define MIPSInst_FD(x) ((MIPSInst(x) & 0x000007c0) >> I_FD_SFT)
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#define I_FR_SFT 21
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#define MIPSInst_FR(x) ((MIPSInst(x) & 0x03e00000) >> I_FR_SFT)
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#define I_FMA_FUNC_SFT 2
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#define MIPSInst_FMA_FUNC(x) ((MIPSInst(x) & 0x0000003c) >> I_FMA_FUNC_SFT)
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#define I_FMA_FFMT_SFT 0
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#define MIPSInst_FMA_FFMT(x) (MIPSInst(x) & 0x00000003)
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typedef unsigned int mips_instruction;
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#endif /* _ASM_INST_H */
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