309 lines
10 KiB
C
309 lines
10 KiB
C
#ifndef LINUX_MSI_H
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#define LINUX_MSI_H
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#include <linux/kobject.h>
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#include <linux/list.h>
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struct msi_msg {
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u32 address_lo; /* low 32 bits of msi message address */
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u32 address_hi; /* high 32 bits of msi message address */
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u32 data; /* 16 bits of msi message data */
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};
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extern int pci_msi_ignore_mask;
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/* Helper functions */
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struct irq_data;
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struct msi_desc;
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struct pci_dev;
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struct platform_msi_priv_data;
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void __get_cached_msi_msg(struct msi_desc *entry, struct msi_msg *msg);
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void get_cached_msi_msg(unsigned int irq, struct msi_msg *msg);
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typedef void (*irq_write_msi_msg_t)(struct msi_desc *desc,
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struct msi_msg *msg);
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/**
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* platform_msi_desc - Platform device specific msi descriptor data
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* @msi_priv_data: Pointer to platform private data
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* @msi_index: The index of the MSI descriptor for multi MSI
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*/
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struct platform_msi_desc {
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struct platform_msi_priv_data *msi_priv_data;
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u16 msi_index;
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};
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/**
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* struct msi_desc - Descriptor structure for MSI based interrupts
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* @list: List head for management
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* @irq: The base interrupt number
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* @nvec_used: The number of vectors used
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* @dev: Pointer to the device which uses this descriptor
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* @msg: The last set MSI message cached for reuse
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*
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* @masked: [PCI MSI/X] Mask bits
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* @is_msix: [PCI MSI/X] True if MSI-X
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* @multiple: [PCI MSI/X] log2 num of messages allocated
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* @multi_cap: [PCI MSI/X] log2 num of messages supported
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* @maskbit: [PCI MSI/X] Mask-Pending bit supported?
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* @is_64: [PCI MSI/X] Address size: 0=32bit 1=64bit
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* @entry_nr: [PCI MSI/X] Entry which is described by this descriptor
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* @default_irq:[PCI MSI/X] The default pre-assigned non-MSI irq
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* @mask_pos: [PCI MSI] Mask register position
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* @mask_base: [PCI MSI-X] Mask register base address
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* @platform: [platform] Platform device specific msi descriptor data
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*/
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struct msi_desc {
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/* Shared device/bus type independent data */
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struct list_head list;
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unsigned int irq;
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unsigned int nvec_used;
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struct device *dev;
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struct msi_msg msg;
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union {
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/* PCI MSI/X specific data */
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struct {
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u32 masked;
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struct {
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__u8 is_msix : 1;
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__u8 multiple : 3;
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__u8 multi_cap : 3;
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__u8 maskbit : 1;
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__u8 is_64 : 1;
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__u16 entry_nr;
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unsigned default_irq;
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} msi_attrib;
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union {
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u8 mask_pos;
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void __iomem *mask_base;
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};
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};
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/*
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* Non PCI variants add their data structure here. New
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* entries need to use a named structure. We want
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* proper name spaces for this. The PCI part is
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* anonymous for now as it would require an immediate
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* tree wide cleanup.
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*/
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struct platform_msi_desc platform;
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};
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};
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/* Helpers to hide struct msi_desc implementation details */
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#define msi_desc_to_dev(desc) ((desc)->dev)
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#define dev_to_msi_list(dev) (&(dev)->msi_list)
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#define first_msi_entry(dev) \
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list_first_entry(dev_to_msi_list((dev)), struct msi_desc, list)
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#define for_each_msi_entry(desc, dev) \
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list_for_each_entry((desc), dev_to_msi_list((dev)), list)
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#ifdef CONFIG_PCI_MSI
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#define first_pci_msi_entry(pdev) first_msi_entry(&(pdev)->dev)
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#define for_each_pci_msi_entry(desc, pdev) \
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for_each_msi_entry((desc), &(pdev)->dev)
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struct pci_dev *msi_desc_to_pci_dev(struct msi_desc *desc);
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void *msi_desc_to_pci_sysdata(struct msi_desc *desc);
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#else /* CONFIG_PCI_MSI */
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static inline void *msi_desc_to_pci_sysdata(struct msi_desc *desc)
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{
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return NULL;
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}
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#endif /* CONFIG_PCI_MSI */
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struct msi_desc *alloc_msi_entry(struct device *dev);
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void free_msi_entry(struct msi_desc *entry);
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void __pci_read_msi_msg(struct msi_desc *entry, struct msi_msg *msg);
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void __pci_write_msi_msg(struct msi_desc *entry, struct msi_msg *msg);
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void pci_write_msi_msg(unsigned int irq, struct msi_msg *msg);
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u32 __pci_msix_desc_mask_irq(struct msi_desc *desc, u32 flag);
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u32 __pci_msi_desc_mask_irq(struct msi_desc *desc, u32 mask, u32 flag);
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void pci_msi_mask_irq(struct irq_data *data);
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void pci_msi_unmask_irq(struct irq_data *data);
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/* Conversion helpers. Should be removed after merging */
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static inline void __write_msi_msg(struct msi_desc *entry, struct msi_msg *msg)
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{
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__pci_write_msi_msg(entry, msg);
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}
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static inline void write_msi_msg(int irq, struct msi_msg *msg)
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{
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pci_write_msi_msg(irq, msg);
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}
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static inline void mask_msi_irq(struct irq_data *data)
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{
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pci_msi_mask_irq(data);
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}
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static inline void unmask_msi_irq(struct irq_data *data)
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{
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pci_msi_unmask_irq(data);
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}
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/*
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* The arch hooks to setup up msi irqs. Those functions are
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* implemented as weak symbols so that they /can/ be overriden by
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* architecture specific code if needed.
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*/
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int arch_setup_msi_irq(struct pci_dev *dev, struct msi_desc *desc);
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void arch_teardown_msi_irq(unsigned int irq);
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int arch_setup_msi_irqs(struct pci_dev *dev, int nvec, int type);
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void arch_teardown_msi_irqs(struct pci_dev *dev);
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void arch_restore_msi_irqs(struct pci_dev *dev);
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void default_teardown_msi_irqs(struct pci_dev *dev);
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void default_restore_msi_irqs(struct pci_dev *dev);
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struct msi_controller {
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struct module *owner;
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struct device *dev;
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struct device_node *of_node;
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struct list_head list;
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int (*setup_irq)(struct msi_controller *chip, struct pci_dev *dev,
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struct msi_desc *desc);
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int (*setup_irqs)(struct msi_controller *chip, struct pci_dev *dev,
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int nvec, int type);
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void (*teardown_irq)(struct msi_controller *chip, unsigned int irq);
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};
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#ifdef CONFIG_GENERIC_MSI_IRQ_DOMAIN
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#include <linux/irqhandler.h>
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#include <asm/msi.h>
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struct irq_domain;
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struct irq_chip;
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struct device_node;
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struct fwnode_handle;
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struct msi_domain_info;
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/**
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* struct msi_domain_ops - MSI interrupt domain callbacks
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* @get_hwirq: Retrieve the resulting hw irq number
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* @msi_init: Domain specific init function for MSI interrupts
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* @msi_free: Domain specific function to free a MSI interrupts
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* @msi_check: Callback for verification of the domain/info/dev data
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* @msi_prepare: Prepare the allocation of the interrupts in the domain
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* @msi_finish: Optional callbacl to finalize the allocation
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* @set_desc: Set the msi descriptor for an interrupt
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* @handle_error: Optional error handler if the allocation fails
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*
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* @get_hwirq, @msi_init and @msi_free are callbacks used by
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* msi_create_irq_domain() and related interfaces
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*
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* @msi_check, @msi_prepare, @msi_finish, @set_desc and @handle_error
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* are callbacks used by msi_irq_domain_alloc_irqs() and related
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* interfaces which are based on msi_desc.
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*/
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struct msi_domain_ops {
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irq_hw_number_t (*get_hwirq)(struct msi_domain_info *info,
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msi_alloc_info_t *arg);
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int (*msi_init)(struct irq_domain *domain,
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struct msi_domain_info *info,
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unsigned int virq, irq_hw_number_t hwirq,
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msi_alloc_info_t *arg);
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void (*msi_free)(struct irq_domain *domain,
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struct msi_domain_info *info,
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unsigned int virq);
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int (*msi_check)(struct irq_domain *domain,
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struct msi_domain_info *info,
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struct device *dev);
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int (*msi_prepare)(struct irq_domain *domain,
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struct device *dev, int nvec,
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msi_alloc_info_t *arg);
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void (*msi_finish)(msi_alloc_info_t *arg, int retval);
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void (*set_desc)(msi_alloc_info_t *arg,
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struct msi_desc *desc);
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int (*handle_error)(struct irq_domain *domain,
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struct msi_desc *desc, int error);
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};
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/**
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* struct msi_domain_info - MSI interrupt domain data
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* @flags: Flags to decribe features and capabilities
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* @ops: The callback data structure
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* @chip: Optional: associated interrupt chip
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* @chip_data: Optional: associated interrupt chip data
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* @handler: Optional: associated interrupt flow handler
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* @handler_data: Optional: associated interrupt flow handler data
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* @handler_name: Optional: associated interrupt flow handler name
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* @data: Optional: domain specific data
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*/
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struct msi_domain_info {
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u32 flags;
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struct msi_domain_ops *ops;
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struct irq_chip *chip;
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void *chip_data;
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irq_flow_handler_t handler;
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void *handler_data;
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const char *handler_name;
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void *data;
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};
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/* Flags for msi_domain_info */
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enum {
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/*
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* Init non implemented ops callbacks with default MSI domain
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* callbacks.
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*/
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MSI_FLAG_USE_DEF_DOM_OPS = (1 << 0),
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/*
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* Init non implemented chip callbacks with default MSI chip
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* callbacks.
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*/
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MSI_FLAG_USE_DEF_CHIP_OPS = (1 << 1),
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/* Build identity map between hwirq and irq */
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MSI_FLAG_IDENTITY_MAP = (1 << 2),
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/* Support multiple PCI MSI interrupts */
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MSI_FLAG_MULTI_PCI_MSI = (1 << 3),
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/* Support PCI MSIX interrupts */
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MSI_FLAG_PCI_MSIX = (1 << 4),
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};
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int msi_domain_set_affinity(struct irq_data *data, const struct cpumask *mask,
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bool force);
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struct irq_domain *msi_create_irq_domain(struct fwnode_handle *fwnode,
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struct msi_domain_info *info,
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struct irq_domain *parent);
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int msi_domain_alloc_irqs(struct irq_domain *domain, struct device *dev,
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int nvec);
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void msi_domain_free_irqs(struct irq_domain *domain, struct device *dev);
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struct msi_domain_info *msi_get_domain_info(struct irq_domain *domain);
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struct irq_domain *platform_msi_create_irq_domain(struct fwnode_handle *fwnode,
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struct msi_domain_info *info,
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struct irq_domain *parent);
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int platform_msi_domain_alloc_irqs(struct device *dev, unsigned int nvec,
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irq_write_msi_msg_t write_msi_msg);
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void platform_msi_domain_free_irqs(struct device *dev);
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#endif /* CONFIG_GENERIC_MSI_IRQ_DOMAIN */
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#ifdef CONFIG_PCI_MSI_IRQ_DOMAIN
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void pci_msi_domain_write_msg(struct irq_data *irq_data, struct msi_msg *msg);
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struct irq_domain *pci_msi_create_irq_domain(struct fwnode_handle *fwnode,
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struct msi_domain_info *info,
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struct irq_domain *parent);
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int pci_msi_domain_alloc_irqs(struct irq_domain *domain, struct pci_dev *dev,
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int nvec, int type);
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void pci_msi_domain_free_irqs(struct irq_domain *domain, struct pci_dev *dev);
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struct irq_domain *pci_msi_create_default_irq_domain(struct fwnode_handle *fwnode,
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struct msi_domain_info *info, struct irq_domain *parent);
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irq_hw_number_t pci_msi_domain_calc_hwirq(struct pci_dev *dev,
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struct msi_desc *desc);
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int pci_msi_domain_check_cap(struct irq_domain *domain,
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struct msi_domain_info *info, struct device *dev);
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u32 pci_msi_domain_get_msi_rid(struct irq_domain *domain, struct pci_dev *pdev);
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struct irq_domain *pci_msi_get_device_domain(struct pci_dev *pdev);
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#else
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static inline struct irq_domain *pci_msi_get_device_domain(struct pci_dev *pdev)
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{
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return NULL;
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}
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#endif /* CONFIG_PCI_MSI_IRQ_DOMAIN */
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#endif /* LINUX_MSI_H */
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