404 lines
12 KiB
C
404 lines
12 KiB
C
/*
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* drivers/mtd/nand/ppchameleonevb.c
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*
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* Copyright (C) 2003 DAVE Srl (info@wawnet.biz)
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*
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* Derived from drivers/mtd/nand/edb7312.c
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*
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* Overview:
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* This is a device driver for the NAND flash devices found on the
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* PPChameleon/PPChameleonEVB system.
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* PPChameleon options (autodetected):
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* - BA model: no NAND
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* - ME model: 32MB (Samsung K9F5608U0B)
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* - HI model: 128MB (Samsung K9F1G08UOM)
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* PPChameleonEVB options:
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* - 32MB (Samsung K9F5608U0B)
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*/
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#include <linux/init.h>
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#include <linux/slab.h>
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#include <linux/module.h>
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#include <linux/mtd/mtd.h>
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#include <linux/mtd/nand.h>
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#include <linux/mtd/partitions.h>
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#include <asm/io.h>
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#include <platforms/PPChameleonEVB.h>
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#undef USE_READY_BUSY_PIN
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#define USE_READY_BUSY_PIN
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/* see datasheets (tR) */
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#define NAND_BIG_DELAY_US 25
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#define NAND_SMALL_DELAY_US 10
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/* handy sizes */
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#define SZ_4M 0x00400000
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#define NAND_SMALL_SIZE 0x02000000
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#define NAND_MTD_NAME "ppchameleon-nand"
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#define NAND_EVB_MTD_NAME "ppchameleonevb-nand"
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/* GPIO pins used to drive NAND chip mounted on processor module */
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#define NAND_nCE_GPIO_PIN (0x80000000 >> 1)
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#define NAND_CLE_GPIO_PIN (0x80000000 >> 2)
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#define NAND_ALE_GPIO_PIN (0x80000000 >> 3)
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#define NAND_RB_GPIO_PIN (0x80000000 >> 4)
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/* GPIO pins used to drive NAND chip mounted on EVB */
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#define NAND_EVB_nCE_GPIO_PIN (0x80000000 >> 14)
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#define NAND_EVB_CLE_GPIO_PIN (0x80000000 >> 15)
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#define NAND_EVB_ALE_GPIO_PIN (0x80000000 >> 16)
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#define NAND_EVB_RB_GPIO_PIN (0x80000000 >> 31)
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/*
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* MTD structure for PPChameleonEVB board
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*/
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static struct mtd_info *ppchameleon_mtd = NULL;
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static struct mtd_info *ppchameleonevb_mtd = NULL;
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/*
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* Module stuff
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*/
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static unsigned long ppchameleon_fio_pbase = CFG_NAND0_PADDR;
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static unsigned long ppchameleonevb_fio_pbase = CFG_NAND1_PADDR;
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#ifdef MODULE
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module_param(ppchameleon_fio_pbase, ulong, 0);
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module_param(ppchameleonevb_fio_pbase, ulong, 0);
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#else
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__setup("ppchameleon_fio_pbase=", ppchameleon_fio_pbase);
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__setup("ppchameleonevb_fio_pbase=", ppchameleonevb_fio_pbase);
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#endif
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/*
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* Define static partitions for flash devices
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*/
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static struct mtd_partition partition_info_hi[] = {
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{ .name = "PPChameleon HI Nand Flash",
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.offset = 0,
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.size = 128 * 1024 * 1024
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}
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};
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static struct mtd_partition partition_info_me[] = {
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{ .name = "PPChameleon ME Nand Flash",
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.offset = 0,
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.size = 32 * 1024 * 1024
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}
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};
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static struct mtd_partition partition_info_evb[] = {
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{ .name = "PPChameleonEVB Nand Flash",
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.offset = 0,
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.size = 32 * 1024 * 1024
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}
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};
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#define NUM_PARTITIONS 1
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/*
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* hardware specific access to control-lines
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*/
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static void ppchameleon_hwcontrol(struct mtd_info *mtdinfo, int cmd,
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unsigned int ctrl)
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{
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struct nand_chip *chip = mtd->priv;
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if (ctrl & NAND_CTRL_CHANGE) {
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#error Missing headerfiles. No way to fix this. -tglx
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switch (cmd) {
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case NAND_CTL_SETCLE:
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MACRO_NAND_CTL_SETCLE((unsigned long)CFG_NAND0_PADDR);
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break;
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case NAND_CTL_CLRCLE:
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MACRO_NAND_CTL_CLRCLE((unsigned long)CFG_NAND0_PADDR);
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break;
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case NAND_CTL_SETALE:
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MACRO_NAND_CTL_SETALE((unsigned long)CFG_NAND0_PADDR);
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break;
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case NAND_CTL_CLRALE:
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MACRO_NAND_CTL_CLRALE((unsigned long)CFG_NAND0_PADDR);
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break;
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case NAND_CTL_SETNCE:
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MACRO_NAND_ENABLE_CE((unsigned long)CFG_NAND0_PADDR);
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break;
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case NAND_CTL_CLRNCE:
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MACRO_NAND_DISABLE_CE((unsigned long)CFG_NAND0_PADDR);
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break;
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}
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}
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if (cmd != NAND_CMD_NONE)
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writeb(cmd, chip->IO_ADDR_W);
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}
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static void ppchameleonevb_hwcontrol(struct mtd_info *mtdinfo, int cmd,
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unsigned int ctrl)
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{
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struct nand_chip *chip = mtd->priv;
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if (ctrl & NAND_CTRL_CHANGE) {
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#error Missing headerfiles. No way to fix this. -tglx
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switch (cmd) {
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case NAND_CTL_SETCLE:
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MACRO_NAND_CTL_SETCLE((unsigned long)CFG_NAND1_PADDR);
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break;
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case NAND_CTL_CLRCLE:
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MACRO_NAND_CTL_CLRCLE((unsigned long)CFG_NAND1_PADDR);
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break;
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case NAND_CTL_SETALE:
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MACRO_NAND_CTL_SETALE((unsigned long)CFG_NAND1_PADDR);
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break;
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case NAND_CTL_CLRALE:
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MACRO_NAND_CTL_CLRALE((unsigned long)CFG_NAND1_PADDR);
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break;
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case NAND_CTL_SETNCE:
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MACRO_NAND_ENABLE_CE((unsigned long)CFG_NAND1_PADDR);
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break;
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case NAND_CTL_CLRNCE:
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MACRO_NAND_DISABLE_CE((unsigned long)CFG_NAND1_PADDR);
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break;
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}
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}
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if (cmd != NAND_CMD_NONE)
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writeb(cmd, chip->IO_ADDR_W);
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}
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#ifdef USE_READY_BUSY_PIN
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/*
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* read device ready pin
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*/
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static int ppchameleon_device_ready(struct mtd_info *minfo)
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{
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if (in_be32((volatile unsigned *)GPIO0_IR) & NAND_RB_GPIO_PIN)
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return 1;
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return 0;
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}
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static int ppchameleonevb_device_ready(struct mtd_info *minfo)
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{
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if (in_be32((volatile unsigned *)GPIO0_IR) & NAND_EVB_RB_GPIO_PIN)
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return 1;
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return 0;
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}
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#endif
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/*
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* Main initialization routine
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*/
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static int __init ppchameleonevb_init(void)
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{
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struct nand_chip *this;
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void __iomem *ppchameleon_fio_base;
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void __iomem *ppchameleonevb_fio_base;
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/*********************************
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* Processor module NAND (if any) *
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*********************************/
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/* Allocate memory for MTD device structure and private data */
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ppchameleon_mtd = kmalloc(sizeof(struct mtd_info) + sizeof(struct nand_chip), GFP_KERNEL);
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if (!ppchameleon_mtd) {
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printk("Unable to allocate PPChameleon NAND MTD device structure.\n");
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return -ENOMEM;
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}
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/* map physical address */
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ppchameleon_fio_base = ioremap(ppchameleon_fio_pbase, SZ_4M);
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if (!ppchameleon_fio_base) {
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printk("ioremap PPChameleon NAND flash failed\n");
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kfree(ppchameleon_mtd);
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return -EIO;
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}
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/* Get pointer to private data */
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this = (struct nand_chip *)(&ppchameleon_mtd[1]);
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/* Initialize structures */
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memset(ppchameleon_mtd, 0, sizeof(struct mtd_info));
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memset(this, 0, sizeof(struct nand_chip));
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/* Link the private data with the MTD structure */
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ppchameleon_mtd->priv = this;
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ppchameleon_mtd->owner = THIS_MODULE;
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/* Initialize GPIOs */
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/* Pin mapping for NAND chip */
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/*
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CE GPIO_01
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CLE GPIO_02
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ALE GPIO_03
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R/B GPIO_04
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*/
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/* output select */
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out_be32((volatile unsigned *)GPIO0_OSRH, in_be32((volatile unsigned *)GPIO0_OSRH) & 0xC0FFFFFF);
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/* three-state select */
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out_be32((volatile unsigned *)GPIO0_TSRH, in_be32((volatile unsigned *)GPIO0_TSRH) & 0xC0FFFFFF);
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/* enable output driver */
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out_be32((volatile unsigned *)GPIO0_TCR,
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in_be32((volatile unsigned *)GPIO0_TCR) | NAND_nCE_GPIO_PIN | NAND_CLE_GPIO_PIN | NAND_ALE_GPIO_PIN);
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#ifdef USE_READY_BUSY_PIN
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/* three-state select */
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out_be32((volatile unsigned *)GPIO0_TSRH, in_be32((volatile unsigned *)GPIO0_TSRH) & 0xFF3FFFFF);
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/* high-impedecence */
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out_be32((volatile unsigned *)GPIO0_TCR, in_be32((volatile unsigned *)GPIO0_TCR) & (~NAND_RB_GPIO_PIN));
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/* input select */
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out_be32((volatile unsigned *)GPIO0_ISR1H,
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(in_be32((volatile unsigned *)GPIO0_ISR1H) & 0xFF3FFFFF) | 0x00400000);
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#endif
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/* insert callbacks */
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this->IO_ADDR_R = ppchameleon_fio_base;
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this->IO_ADDR_W = ppchameleon_fio_base;
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this->cmd_ctrl = ppchameleon_hwcontrol;
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#ifdef USE_READY_BUSY_PIN
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this->dev_ready = ppchameleon_device_ready;
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#endif
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this->chip_delay = NAND_BIG_DELAY_US;
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/* ECC mode */
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this->ecc.mode = NAND_ECC_SOFT;
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/* Scan to find existence of the device (it could not be mounted) */
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if (nand_scan(ppchameleon_mtd, 1)) {
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iounmap((void *)ppchameleon_fio_base);
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ppchameleon_fio_base = NULL;
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kfree(ppchameleon_mtd);
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goto nand_evb_init;
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}
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#ifndef USE_READY_BUSY_PIN
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/* Adjust delay if necessary */
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if (ppchameleon_mtd->size == NAND_SMALL_SIZE)
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this->chip_delay = NAND_SMALL_DELAY_US;
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#endif
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ppchameleon_mtd->name = "ppchameleon-nand";
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/* Register the partitions */
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mtd_device_parse_register(ppchameleon_mtd, NULL, NULL,
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ppchameleon_mtd->size == NAND_SMALL_SIZE ?
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partition_info_me : partition_info_hi,
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NUM_PARTITIONS);
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nand_evb_init:
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/****************************
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* EVB NAND (always present) *
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****************************/
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/* Allocate memory for MTD device structure and private data */
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ppchameleonevb_mtd = kmalloc(sizeof(struct mtd_info) + sizeof(struct nand_chip), GFP_KERNEL);
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if (!ppchameleonevb_mtd) {
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printk("Unable to allocate PPChameleonEVB NAND MTD device structure.\n");
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if (ppchameleon_fio_base)
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iounmap(ppchameleon_fio_base);
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return -ENOMEM;
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}
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/* map physical address */
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ppchameleonevb_fio_base = ioremap(ppchameleonevb_fio_pbase, SZ_4M);
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if (!ppchameleonevb_fio_base) {
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printk("ioremap PPChameleonEVB NAND flash failed\n");
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kfree(ppchameleonevb_mtd);
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if (ppchameleon_fio_base)
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iounmap(ppchameleon_fio_base);
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return -EIO;
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}
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/* Get pointer to private data */
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this = (struct nand_chip *)(&ppchameleonevb_mtd[1]);
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/* Initialize structures */
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memset(ppchameleonevb_mtd, 0, sizeof(struct mtd_info));
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memset(this, 0, sizeof(struct nand_chip));
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/* Link the private data with the MTD structure */
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ppchameleonevb_mtd->priv = this;
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/* Initialize GPIOs */
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/* Pin mapping for NAND chip */
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/*
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CE GPIO_14
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CLE GPIO_15
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ALE GPIO_16
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R/B GPIO_31
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*/
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/* output select */
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out_be32((volatile unsigned *)GPIO0_OSRH, in_be32((volatile unsigned *)GPIO0_OSRH) & 0xFFFFFFF0);
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out_be32((volatile unsigned *)GPIO0_OSRL, in_be32((volatile unsigned *)GPIO0_OSRL) & 0x3FFFFFFF);
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/* three-state select */
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out_be32((volatile unsigned *)GPIO0_TSRH, in_be32((volatile unsigned *)GPIO0_TSRH) & 0xFFFFFFF0);
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out_be32((volatile unsigned *)GPIO0_TSRL, in_be32((volatile unsigned *)GPIO0_TSRL) & 0x3FFFFFFF);
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/* enable output driver */
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out_be32((volatile unsigned *)GPIO0_TCR, in_be32((volatile unsigned *)GPIO0_TCR) | NAND_EVB_nCE_GPIO_PIN |
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NAND_EVB_CLE_GPIO_PIN | NAND_EVB_ALE_GPIO_PIN);
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#ifdef USE_READY_BUSY_PIN
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/* three-state select */
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out_be32((volatile unsigned *)GPIO0_TSRL, in_be32((volatile unsigned *)GPIO0_TSRL) & 0xFFFFFFFC);
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/* high-impedecence */
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out_be32((volatile unsigned *)GPIO0_TCR, in_be32((volatile unsigned *)GPIO0_TCR) & (~NAND_EVB_RB_GPIO_PIN));
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/* input select */
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out_be32((volatile unsigned *)GPIO0_ISR1L,
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(in_be32((volatile unsigned *)GPIO0_ISR1L) & 0xFFFFFFFC) | 0x00000001);
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#endif
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/* insert callbacks */
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this->IO_ADDR_R = ppchameleonevb_fio_base;
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this->IO_ADDR_W = ppchameleonevb_fio_base;
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this->cmd_ctrl = ppchameleonevb_hwcontrol;
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#ifdef USE_READY_BUSY_PIN
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this->dev_ready = ppchameleonevb_device_ready;
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#endif
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this->chip_delay = NAND_SMALL_DELAY_US;
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/* ECC mode */
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this->ecc.mode = NAND_ECC_SOFT;
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/* Scan to find existence of the device */
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if (nand_scan(ppchameleonevb_mtd, 1)) {
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iounmap((void *)ppchameleonevb_fio_base);
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kfree(ppchameleonevb_mtd);
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if (ppchameleon_fio_base)
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iounmap(ppchameleon_fio_base);
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return -ENXIO;
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}
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ppchameleonevb_mtd->name = NAND_EVB_MTD_NAME;
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/* Register the partitions */
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mtd_device_parse_register(ppchameleonevb_mtd, NULL, NULL,
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ppchameleon_mtd->size == NAND_SMALL_SIZE ?
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partition_info_me : partition_info_hi,
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NUM_PARTITIONS);
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/* Return happy */
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return 0;
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}
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module_init(ppchameleonevb_init);
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/*
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* Clean up routine
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*/
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static void __exit ppchameleonevb_cleanup(void)
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{
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struct nand_chip *this;
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/* Release resources, unregister device(s) */
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nand_release(ppchameleon_mtd);
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nand_release(ppchameleonevb_mtd);
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/* Release iomaps */
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this = (struct nand_chip *) &ppchameleon_mtd[1];
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iounmap((void *) this->IO_ADDR_R);
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this = (struct nand_chip *) &ppchameleonevb_mtd[1];
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iounmap((void *) this->IO_ADDR_R);
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/* Free the MTD device structure */
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kfree (ppchameleon_mtd);
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kfree (ppchameleonevb_mtd);
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}
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module_exit(ppchameleonevb_cleanup);
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MODULE_LICENSE("GPL");
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MODULE_AUTHOR("DAVE Srl <support-ppchameleon@dave-tech.it>");
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MODULE_DESCRIPTION("MTD map driver for DAVE Srl PPChameleonEVB board");
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