161 lines
3.9 KiB
C
161 lines
3.9 KiB
C
/*
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* Allwinner A1X SoCs timer handling.
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*
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* Copyright (C) 2012 Maxime Ripard
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*
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* Maxime Ripard <maxime.ripard@free-electrons.com>
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*
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* Based on code from
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* Allwinner Technology Co., Ltd. <www.allwinnertech.com>
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* Benn Huang <benn@allwinnertech.com>
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*
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* This file is licensed under the terms of the GNU General Public
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* License version 2. This program is licensed "as is" without any
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* warranty of any kind, whether express or implied.
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*/
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#include <linux/clk.h>
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#include <linux/clockchips.h>
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#include <linux/interrupt.h>
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#include <linux/irq.h>
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#include <linux/irqreturn.h>
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#include <linux/of.h>
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#include <linux/of_address.h>
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#include <linux/of_irq.h>
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#include <linux/sunxi_timer.h>
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#include <linux/clk-provider.h>
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#define TIMER_CTL_REG 0x00
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#define TIMER_CTL_ENABLE (1 << 0)
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#define TIMER_IRQ_ST_REG 0x04
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#define TIMER0_CTL_REG 0x10
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#define TIMER0_CTL_ENABLE (1 << 0)
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#define TIMER0_CTL_AUTORELOAD (1 << 1)
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#define TIMER0_CTL_ONESHOT (1 << 7)
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#define TIMER0_INTVAL_REG 0x14
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#define TIMER0_CNTVAL_REG 0x18
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#define TIMER_SCAL 16
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static void __iomem *timer_base;
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static void sunxi_clkevt_mode(enum clock_event_mode mode,
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struct clock_event_device *clk)
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{
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u32 u = readl(timer_base + TIMER0_CTL_REG);
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switch (mode) {
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case CLOCK_EVT_MODE_PERIODIC:
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u &= ~(TIMER0_CTL_ONESHOT);
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writel(u | TIMER0_CTL_ENABLE, timer_base + TIMER0_CTL_REG);
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break;
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case CLOCK_EVT_MODE_ONESHOT:
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writel(u | TIMER0_CTL_ONESHOT, timer_base + TIMER0_CTL_REG);
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break;
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case CLOCK_EVT_MODE_UNUSED:
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case CLOCK_EVT_MODE_SHUTDOWN:
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default:
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writel(u & ~(TIMER0_CTL_ENABLE), timer_base + TIMER0_CTL_REG);
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break;
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}
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}
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static int sunxi_clkevt_next_event(unsigned long evt,
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struct clock_event_device *unused)
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{
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u32 u = readl(timer_base + TIMER0_CTL_REG);
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writel(evt, timer_base + TIMER0_CNTVAL_REG);
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writel(u | TIMER0_CTL_ENABLE | TIMER0_CTL_AUTORELOAD,
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timer_base + TIMER0_CTL_REG);
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return 0;
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}
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static struct clock_event_device sunxi_clockevent = {
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.name = "sunxi_tick",
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.rating = 300,
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.features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT,
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.set_mode = sunxi_clkevt_mode,
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.set_next_event = sunxi_clkevt_next_event,
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};
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static irqreturn_t sunxi_timer_interrupt(int irq, void *dev_id)
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{
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struct clock_event_device *evt = (struct clock_event_device *)dev_id;
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writel(0x1, timer_base + TIMER_IRQ_ST_REG);
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evt->event_handler(evt);
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return IRQ_HANDLED;
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}
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static struct irqaction sunxi_timer_irq = {
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.name = "sunxi_timer0",
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.flags = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL,
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.handler = sunxi_timer_interrupt,
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.dev_id = &sunxi_clockevent,
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};
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static struct of_device_id sunxi_timer_dt_ids[] = {
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{ .compatible = "allwinner,sunxi-timer" },
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{ }
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};
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void __init sunxi_timer_init(void)
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{
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struct device_node *node;
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unsigned long rate = 0;
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struct clk *clk;
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int ret, irq;
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u32 val;
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node = of_find_matching_node(NULL, sunxi_timer_dt_ids);
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if (!node)
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panic("No sunxi timer node");
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timer_base = of_iomap(node, 0);
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if (!timer_base)
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panic("Can't map registers");
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irq = irq_of_parse_and_map(node, 0);
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if (irq <= 0)
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panic("Can't parse IRQ");
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of_clk_init(NULL);
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clk = of_clk_get(node, 0);
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if (IS_ERR(clk))
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panic("Can't get timer clock");
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rate = clk_get_rate(clk);
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writel(rate / (TIMER_SCAL * HZ),
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timer_base + TIMER0_INTVAL_REG);
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/* set clock source to HOSC, 16 pre-division */
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val = readl(timer_base + TIMER0_CTL_REG);
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val &= ~(0x07 << 4);
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val &= ~(0x03 << 2);
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val |= (4 << 4) | (1 << 2);
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writel(val, timer_base + TIMER0_CTL_REG);
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/* set mode to auto reload */
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val = readl(timer_base + TIMER0_CTL_REG);
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writel(val | TIMER0_CTL_AUTORELOAD, timer_base + TIMER0_CTL_REG);
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ret = setup_irq(irq, &sunxi_timer_irq);
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if (ret)
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pr_warn("failed to setup irq %d\n", irq);
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/* Enable timer0 interrupt */
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val = readl(timer_base + TIMER_CTL_REG);
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writel(val | TIMER_CTL_ENABLE, timer_base + TIMER_CTL_REG);
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sunxi_clockevent.cpumask = cpumask_of(0);
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clockevents_config_and_register(&sunxi_clockevent, rate / TIMER_SCAL,
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0x1, 0xff);
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}
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