98 lines
4.1 KiB
Plaintext
98 lines
4.1 KiB
Plaintext
Memory Layout on AArch64 Linux
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==============================
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Author: Catalin Marinas <catalin.marinas@arm.com>
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This document describes the virtual memory layout used by the AArch64
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Linux kernel. The architecture allows up to 4 levels of translation
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tables with a 4KB page size and up to 3 levels with a 64KB page size.
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AArch64 Linux uses either 3 levels or 4 levels of translation tables
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with the 4KB page configuration, allowing 39-bit (512GB) or 48-bit
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(256TB) virtual addresses, respectively, for both user and kernel. With
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64KB pages, only 2 levels of translation tables, allowing 42-bit (4TB)
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virtual address, are used but the memory layout is the same.
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User addresses have bits 63:48 set to 0 while the kernel addresses have
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the same bits set to 1. TTBRx selection is given by bit 63 of the
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virtual address. The swapper_pg_dir contains only kernel (global)
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mappings while the user pgd contains only user (non-global) mappings.
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The swapper_pg_dir address is written to TTBR1 and never written to
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TTBR0.
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AArch64 Linux memory layout with 4KB pages + 3 levels:
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Start End Size Use
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-----------------------------------------------------------------------
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0000000000000000 0000007fffffffff 512GB user
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ffffff8000000000 ffffffffffffffff 512GB kernel
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AArch64 Linux memory layout with 4KB pages + 4 levels:
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Start End Size Use
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-----------------------------------------------------------------------
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0000000000000000 0000ffffffffffff 256TB user
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ffff000000000000 ffffffffffffffff 256TB kernel
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AArch64 Linux memory layout with 64KB pages + 2 levels:
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Start End Size Use
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-----------------------------------------------------------------------
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0000000000000000 000003ffffffffff 4TB user
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fffffc0000000000 ffffffffffffffff 4TB kernel
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AArch64 Linux memory layout with 64KB pages + 3 levels:
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Start End Size Use
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-----------------------------------------------------------------------
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0000000000000000 0000ffffffffffff 256TB user
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ffff000000000000 ffffffffffffffff 256TB kernel
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For details of the virtual kernel memory layout please see the kernel
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booting log.
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Translation table lookup with 4KB pages:
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+--------+--------+--------+--------+--------+--------+--------+--------+
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|63 56|55 48|47 40|39 32|31 24|23 16|15 8|7 0|
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+--------+--------+--------+--------+--------+--------+--------+--------+
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| | | | | |
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| | | | | v
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| | | | | [11:0] in-page offset
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| | | | +-> [20:12] L3 index
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| | | +-----------> [29:21] L2 index
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| | +---------------------> [38:30] L1 index
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| +-------------------------------> [47:39] L0 index
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+-------------------------------------------------> [63] TTBR0/1
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Translation table lookup with 64KB pages:
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+--------+--------+--------+--------+--------+--------+--------+--------+
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|63 56|55 48|47 40|39 32|31 24|23 16|15 8|7 0|
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+--------+--------+--------+--------+--------+--------+--------+--------+
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| | | | |
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| | | | v
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| | | | [15:0] in-page offset
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| | | +----------> [28:16] L3 index
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| | +--------------------------> [41:29] L2 index
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| +-------------------------------> [47:42] L1 index
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+-------------------------------------------------> [63] TTBR0/1
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When using KVM without the Virtualization Host Extensions, the
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hypervisor maps kernel pages in EL2 at a fixed (and potentially
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random) offset from the linear mapping. See the kern_hyp_va macro and
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kvm_update_va_mask function for more details. MMIO devices such as
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GICv2 gets mapped next to the HYP idmap page, as do vectors when
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ARM64_HARDEN_EL2_VECTORS is selected for particular CPUs.
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When using KVM with the Virtualization Host Extensions, no additional
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mappings are created, since the host kernel runs directly in EL2.
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