334 lines
9.8 KiB
ArmAsm
334 lines
9.8 KiB
ArmAsm
/*
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* linux/arch/arm/mach-omap2/sram.S
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*
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* Omap2 specific functions that need to be run in internal SRAM
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*
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* (C) Copyright 2004
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* Texas Instruments, <www.ti.com>
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* Richard Woodruff <r-woodruff2@ti.com>
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR /PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <linux/config.h>
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#include <linux/linkage.h>
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#include <asm/assembler.h>
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#include <asm/arch/io.h>
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#include <asm/hardware.h>
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#include "prcm-regs.h"
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#define TIMER_32KSYNCT_CR_V IO_ADDRESS(OMAP24XX_32KSYNCT_BASE + 0x010)
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#define CM_CLKSEL2_PLL_V IO_ADDRESS(OMAP24XX_PRCM_BASE + 0x544)
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#define PRCM_VOLTCTRL_V IO_ADDRESS(OMAP24XX_PRCM_BASE + 0x050)
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#define PRCM_CLKCFG_CTRL_V IO_ADDRESS(OMAP24XX_PRCM_BASE + 0x080)
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#define CM_CLKEN_PLL_V IO_ADDRESS(OMAP24XX_PRCM_BASE + 0x500)
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#define CM_IDLEST_CKGEN_V IO_ADDRESS(OMAP24XX_PRCM_BASE + 0x520)
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#define CM_CLKSEL1_PLL_V IO_ADDRESS(OMAP24XX_PRCM_BASE + 0x540)
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#define SDRC_DLLA_CTRL_V IO_ADDRESS(OMAP24XX_SDRC_BASE + 0x060)
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#define SDRC_RFR_CTRL_V IO_ADDRESS(OMAP24XX_SDRC_BASE + 0x0a4)
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.text
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ENTRY(sram_ddr_init)
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stmfd sp!, {r0 - r12, lr} @ save registers on stack
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mov r12, r2 @ capture CS1 vs CS0
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mov r8, r3 @ capture force parameter
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/* frequency shift down */
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ldr r2, cm_clksel2_pll @ get address of dpllout reg
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mov r3, #0x1 @ value for 1x operation
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str r3, [r2] @ go to L1-freq operation
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/* voltage shift down */
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mov r9, #0x1 @ set up for L1 voltage call
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bl voltage_shift @ go drop voltage
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/* dll lock mode */
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ldr r11, sdrc_dlla_ctrl @ addr of dlla ctrl
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ldr r10, [r11] @ get current val
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cmp r12, #0x1 @ cs1 base (2422 es2.05/1)
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addeq r11, r11, #0x8 @ if cs1 base, move to DLLB
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mvn r9, #0x4 @ mask to get clear bit2
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and r10, r10, r9 @ clear bit2 for lock mode.
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orr r10, r10, #0x8 @ make sure DLL on (es2 bit pos)
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orr r10, r10, #0x2 @ 90 degree phase for all below 133Mhz
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str r10, [r11] @ commit to DLLA_CTRL
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bl i_dll_wait @ wait for dll to lock
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/* get dll value */
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add r11, r11, #0x4 @ get addr of status reg
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ldr r10, [r11] @ get locked value
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/* voltage shift up */
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mov r9, #0x0 @ shift back to L0-voltage
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bl voltage_shift @ go raise voltage
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/* frequency shift up */
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mov r3, #0x2 @ value for 2x operation
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str r3, [r2] @ go to L0-freq operation
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/* reset entry mode for dllctrl */
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sub r11, r11, #0x4 @ move from status to ctrl
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cmp r12, #0x1 @ normalize if cs1 based
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subeq r11, r11, #0x8 @ possibly back to DLLA
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cmp r8, #0x1 @ if forced unlock exit
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orreq r1, r1, #0x4 @ make sure exit with unlocked value
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str r1, [r11] @ restore DLLA_CTRL high value
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add r11, r11, #0x8 @ move to DLLB_CTRL addr
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str r1, [r11] @ set value DLLB_CTRL
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bl i_dll_wait @ wait for possible lock
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/* set up for return, DDR should be good */
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str r10, [r0] @ write dll_status and return counter
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ldmfd sp!, {r0 - r12, pc} @ restore regs and return
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/* ensure the DLL has relocked */
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i_dll_wait:
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mov r4, #0x800 @ delay DLL relock, min 0x400 L3 clocks
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i_dll_delay:
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subs r4, r4, #0x1
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bne i_dll_delay
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mov pc, lr
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/*
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* shift up or down voltage, use R9 as input to tell level.
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* wait for it to finish, use 32k sync counter, 1tick=31uS.
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*/
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voltage_shift:
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ldr r4, prcm_voltctrl @ get addr of volt ctrl.
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ldr r5, [r4] @ get value.
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ldr r6, prcm_mask_val @ get value of mask
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and r5, r5, r6 @ apply mask to clear bits
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orr r5, r5, r9 @ bulld value for L0/L1-volt operation.
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str r5, [r4] @ set up for change.
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mov r3, #0x4000 @ get val for force
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orr r5, r5, r3 @ build value for force
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str r5, [r4] @ Force transition to L1
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ldr r3, timer_32ksynct_cr @ get addr of counter
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ldr r5, [r3] @ get value
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add r5, r5, #0x3 @ give it at most 93uS
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volt_delay:
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ldr r7, [r3] @ get timer value
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cmp r5, r7 @ time up?
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bhi volt_delay @ not yet->branch
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mov pc, lr @ back to caller.
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/* relative load constants */
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cm_clksel2_pll:
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.word CM_CLKSEL2_PLL_V
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sdrc_dlla_ctrl:
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.word SDRC_DLLA_CTRL_V
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prcm_voltctrl:
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.word PRCM_VOLTCTRL_V
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prcm_mask_val:
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.word 0xFFFF3FFC
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timer_32ksynct_cr:
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.word TIMER_32KSYNCT_CR_V
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ENTRY(sram_ddr_init_sz)
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.word . - sram_ddr_init
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/*
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* Reprograms memory timings.
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* r0 = [PRCM_FULL | PRCM_HALF] r1 = SDRC_DLLA_CTRL value r2 = [DDR | SDR]
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* PRCM_FULL = 2, PRCM_HALF = 1, DDR = 1, SDR = 0
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*/
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ENTRY(sram_reprogram_sdrc)
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stmfd sp!, {r0 - r10, lr} @ save registers on stack
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mov r3, #0x0 @ clear for mrc call
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mcr p15, 0, r3, c7, c10, 4 @ memory barrier, finish ARM SDR/DDR
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nop
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nop
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ldr r6, ddr_sdrc_rfr_ctrl @ get addr of refresh reg
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ldr r5, [r6] @ get value
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mov r5, r5, lsr #8 @ isolate rfr field and drop burst
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cmp r0, #0x1 @ going to half speed?
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movne r9, #0x0 @ if up set flag up for pre up, hi volt
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blne voltage_shift_c @ adjust voltage
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cmp r0, #0x1 @ going to half speed (post branch link)
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moveq r5, r5, lsr #1 @ divide by 2 if to half
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movne r5, r5, lsl #1 @ mult by 2 if to full
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mov r5, r5, lsl #8 @ put rfr field back into place
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add r5, r5, #0x1 @ turn on burst of 1
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ldr r4, ddr_cm_clksel2_pll @ get address of out reg
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ldr r3, [r4] @ get curr value
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orr r3, r3, #0x3
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bic r3, r3, #0x3 @ clear lower bits
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orr r3, r3, r0 @ new state value
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str r3, [r4] @ set new state (pll/x, x=1 or 2)
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nop
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nop
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moveq r9, #0x1 @ if speed down, post down, drop volt
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bleq voltage_shift_c
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mcr p15, 0, r3, c7, c10, 4 @ memory barrier
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str r5, [r6] @ set new RFR_1 value
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add r6, r6, #0x30 @ get RFR_2 addr
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str r5, [r6] @ set RFR_2
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nop
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cmp r2, #0x1 @ (SDR or DDR) do we need to adjust DLL
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bne freq_out @ leave if SDR, no DLL function
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/* With DDR, we need to take care of the DLL for the frequency change */
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ldr r2, ddr_sdrc_dlla_ctrl @ addr of dlla ctrl
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str r1, [r2] @ write out new SDRC_DLLA_CTRL
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add r2, r2, #0x8 @ addr to SDRC_DLLB_CTRL
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str r1, [r2] @ commit to SDRC_DLLB_CTRL
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mov r1, #0x2000 @ wait DLL relock, min 0x400 L3 clocks
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dll_wait:
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subs r1, r1, #0x1
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bne dll_wait
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freq_out:
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ldmfd sp!, {r0 - r10, pc} @ restore regs and return
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/*
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* shift up or down voltage, use R9 as input to tell level.
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* wait for it to finish, use 32k sync counter, 1tick=31uS.
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*/
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voltage_shift_c:
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ldr r10, ddr_prcm_voltctrl @ get addr of volt ctrl
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ldr r8, [r10] @ get value
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ldr r7, ddr_prcm_mask_val @ get value of mask
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and r8, r8, r7 @ apply mask to clear bits
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orr r8, r8, r9 @ bulld value for L0/L1-volt operation.
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str r8, [r10] @ set up for change.
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mov r7, #0x4000 @ get val for force
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orr r8, r8, r7 @ build value for force
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str r8, [r10] @ Force transition to L1
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ldr r10, ddr_timer_32ksynct @ get addr of counter
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ldr r8, [r10] @ get value
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add r8, r8, #0x2 @ give it at most 62uS (min 31+)
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volt_delay_c:
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ldr r7, [r10] @ get timer value
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cmp r8, r7 @ time up?
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bhi volt_delay_c @ not yet->branch
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mov pc, lr @ back to caller
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ddr_cm_clksel2_pll:
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.word CM_CLKSEL2_PLL_V
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ddr_sdrc_dlla_ctrl:
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.word SDRC_DLLA_CTRL_V
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ddr_sdrc_rfr_ctrl:
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.word SDRC_RFR_CTRL_V
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ddr_prcm_voltctrl:
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.word PRCM_VOLTCTRL_V
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ddr_prcm_mask_val:
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.word 0xFFFF3FFC
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ddr_timer_32ksynct:
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.word TIMER_32KSYNCT_CR_V
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ENTRY(sram_reprogram_sdrc_sz)
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.word . - sram_reprogram_sdrc
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/*
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* Set dividers and pll. Also recalculate DLL value for DDR and unlock mode.
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*/
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ENTRY(sram_set_prcm)
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stmfd sp!, {r0-r12, lr} @ regs to stack
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adr r4, pbegin @ addr of preload start
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adr r8, pend @ addr of preload end
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mcrr p15, 1, r8, r4, c12 @ preload into icache
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pbegin:
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/* move into fast relock bypass */
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ldr r8, pll_ctl @ get addr
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ldr r5, [r8] @ get val
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mvn r6, #0x3 @ clear mask
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and r5, r5, r6 @ clear field
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orr r7, r5, #0x2 @ fast relock val
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str r7, [r8] @ go to fast relock
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ldr r4, pll_stat @ addr of stat
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block:
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/* wait for bypass */
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ldr r8, [r4] @ stat value
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and r8, r8, #0x3 @ mask for stat
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cmp r8, #0x1 @ there yet
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bne block @ loop if not
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/* set new dpll dividers _after_ in bypass */
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ldr r4, pll_div @ get addr
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str r0, [r4] @ set dpll ctrl val
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ldr r4, set_config @ get addr
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mov r8, #1 @ valid cfg msk
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str r8, [r4] @ make dividers take
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mov r4, #100 @ dead spin a bit
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wait_a_bit:
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subs r4, r4, #1 @ dec loop
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bne wait_a_bit @ delay done?
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/* check if staying in bypass */
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cmp r2, #0x1 @ stay in bypass?
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beq pend @ jump over dpll relock
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/* relock DPLL with new vals */
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ldr r5, pll_stat @ get addr
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ldr r4, pll_ctl @ get addr
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orr r8, r7, #0x3 @ val for lock dpll
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str r8, [r4] @ set val
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mov r0, #1000 @ dead spin a bit
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wait_more:
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subs r0, r0, #1 @ dec loop
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bne wait_more @ delay done?
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wait_lock:
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ldr r8, [r5] @ get lock val
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and r8, r8, #3 @ isolate field
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cmp r8, #2 @ locked?
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bne wait_lock @ wait if not
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pend:
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/* update memory timings & briefly lock dll */
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ldr r4, sdrc_rfr @ get addr
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str r1, [r4] @ update refresh timing
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ldr r11, dlla_ctrl @ get addr of DLLA ctrl
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ldr r10, [r11] @ get current val
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mvn r9, #0x4 @ mask to get clear bit2
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and r10, r10, r9 @ clear bit2 for lock mode
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orr r10, r10, #0x8 @ make sure DLL on (es2 bit pos)
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str r10, [r11] @ commit to DLLA_CTRL
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add r11, r11, #0x8 @ move to dllb
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str r10, [r11] @ hit DLLB also
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mov r4, #0x800 @ relock time (min 0x400 L3 clocks)
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wait_dll_lock:
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subs r4, r4, #0x1
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bne wait_dll_lock
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nop
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ldmfd sp!, {r0-r12, pc} @ restore regs and return
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set_config:
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.word PRCM_CLKCFG_CTRL_V
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pll_ctl:
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.word CM_CLKEN_PLL_V
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pll_stat:
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.word CM_IDLEST_CKGEN_V
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pll_div:
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.word CM_CLKSEL1_PLL_V
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sdrc_rfr:
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.word SDRC_RFR_CTRL_V
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dlla_ctrl:
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.word SDRC_DLLA_CTRL_V
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ENTRY(sram_set_prcm_sz)
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.word . - sram_set_prcm
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