830 lines
23 KiB
C
830 lines
23 KiB
C
/*
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* core.c - DesignWare HS OTG Controller common routines
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*
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* Copyright (C) 2004-2013 Synopsys, Inc.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions, and the following disclaimer,
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* without modification.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. The names of the above-listed copyright holders may not be used
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* to endorse or promote products derived from this software without
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* specific prior written permission.
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*
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* ALTERNATIVELY, this software may be distributed under the terms of the
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* GNU General Public License ("GPL") as published by the Free Software
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* Foundation; either version 2 of the License, or (at your option) any
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* later version.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
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* IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
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* THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
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* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
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* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
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* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
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* PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
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* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
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* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
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* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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/*
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* The Core code provides basic services for accessing and managing the
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* DWC_otg hardware. These services are used by both the Host Controller
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* Driver and the Peripheral Controller Driver.
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*/
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/moduleparam.h>
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#include <linux/spinlock.h>
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#include <linux/interrupt.h>
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#include <linux/dma-mapping.h>
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#include <linux/delay.h>
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#include <linux/io.h>
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#include <linux/slab.h>
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#include <linux/usb.h>
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#include <linux/usb/hcd.h>
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#include <linux/usb/ch11.h>
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#include "core.h"
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#include "hcd.h"
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/**
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* dwc2_backup_global_registers() - Backup global controller registers.
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* When suspending usb bus, registers needs to be backuped
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* if controller power is disabled once suspended.
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*
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* @hsotg: Programming view of the DWC_otg controller
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*/
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static int dwc2_backup_global_registers(struct dwc2_hsotg *hsotg)
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{
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struct dwc2_gregs_backup *gr;
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int i;
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/* Backup global regs */
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gr = &hsotg->gr_backup;
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gr->gotgctl = dwc2_readl(hsotg->regs + GOTGCTL);
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gr->gintmsk = dwc2_readl(hsotg->regs + GINTMSK);
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gr->gahbcfg = dwc2_readl(hsotg->regs + GAHBCFG);
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gr->gusbcfg = dwc2_readl(hsotg->regs + GUSBCFG);
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gr->grxfsiz = dwc2_readl(hsotg->regs + GRXFSIZ);
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gr->gnptxfsiz = dwc2_readl(hsotg->regs + GNPTXFSIZ);
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gr->hptxfsiz = dwc2_readl(hsotg->regs + HPTXFSIZ);
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gr->gdfifocfg = dwc2_readl(hsotg->regs + GDFIFOCFG);
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for (i = 0; i < MAX_EPS_CHANNELS; i++)
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gr->dtxfsiz[i] = dwc2_readl(hsotg->regs + DPTXFSIZN(i));
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gr->valid = true;
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return 0;
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}
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/**
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* dwc2_restore_global_registers() - Restore controller global registers.
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* When resuming usb bus, device registers needs to be restored
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* if controller power were disabled.
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*
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* @hsotg: Programming view of the DWC_otg controller
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*/
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static int dwc2_restore_global_registers(struct dwc2_hsotg *hsotg)
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{
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struct dwc2_gregs_backup *gr;
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int i;
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dev_dbg(hsotg->dev, "%s\n", __func__);
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/* Restore global regs */
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gr = &hsotg->gr_backup;
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if (!gr->valid) {
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dev_err(hsotg->dev, "%s: no global registers to restore\n",
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__func__);
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return -EINVAL;
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}
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gr->valid = false;
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dwc2_writel(0xffffffff, hsotg->regs + GINTSTS);
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dwc2_writel(gr->gotgctl, hsotg->regs + GOTGCTL);
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dwc2_writel(gr->gintmsk, hsotg->regs + GINTMSK);
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dwc2_writel(gr->gusbcfg, hsotg->regs + GUSBCFG);
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dwc2_writel(gr->gahbcfg, hsotg->regs + GAHBCFG);
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dwc2_writel(gr->grxfsiz, hsotg->regs + GRXFSIZ);
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dwc2_writel(gr->gnptxfsiz, hsotg->regs + GNPTXFSIZ);
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dwc2_writel(gr->hptxfsiz, hsotg->regs + HPTXFSIZ);
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dwc2_writel(gr->gdfifocfg, hsotg->regs + GDFIFOCFG);
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for (i = 0; i < MAX_EPS_CHANNELS; i++)
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dwc2_writel(gr->dtxfsiz[i], hsotg->regs + DPTXFSIZN(i));
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return 0;
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}
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/**
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* dwc2_exit_hibernation() - Exit controller from Partial Power Down.
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*
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* @hsotg: Programming view of the DWC_otg controller
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* @restore: Controller registers need to be restored
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*/
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int dwc2_exit_hibernation(struct dwc2_hsotg *hsotg, bool restore)
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{
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u32 pcgcctl;
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int ret = 0;
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if (!hsotg->params.hibernation)
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return -ENOTSUPP;
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pcgcctl = dwc2_readl(hsotg->regs + PCGCTL);
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pcgcctl &= ~PCGCTL_STOPPCLK;
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dwc2_writel(pcgcctl, hsotg->regs + PCGCTL);
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pcgcctl = dwc2_readl(hsotg->regs + PCGCTL);
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pcgcctl &= ~PCGCTL_PWRCLMP;
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dwc2_writel(pcgcctl, hsotg->regs + PCGCTL);
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pcgcctl = dwc2_readl(hsotg->regs + PCGCTL);
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pcgcctl &= ~PCGCTL_RSTPDWNMODULE;
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dwc2_writel(pcgcctl, hsotg->regs + PCGCTL);
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udelay(100);
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if (restore) {
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ret = dwc2_restore_global_registers(hsotg);
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if (ret) {
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dev_err(hsotg->dev, "%s: failed to restore registers\n",
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__func__);
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return ret;
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}
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if (dwc2_is_host_mode(hsotg)) {
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ret = dwc2_restore_host_registers(hsotg);
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if (ret) {
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dev_err(hsotg->dev, "%s: failed to restore host registers\n",
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__func__);
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return ret;
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}
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} else {
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ret = dwc2_restore_device_registers(hsotg);
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if (ret) {
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dev_err(hsotg->dev, "%s: failed to restore device registers\n",
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__func__);
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return ret;
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}
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}
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}
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return ret;
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}
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/**
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* dwc2_enter_hibernation() - Put controller in Partial Power Down.
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*
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* @hsotg: Programming view of the DWC_otg controller
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*/
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int dwc2_enter_hibernation(struct dwc2_hsotg *hsotg)
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{
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u32 pcgcctl;
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int ret = 0;
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if (!hsotg->params.hibernation)
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return -ENOTSUPP;
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/* Backup all registers */
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ret = dwc2_backup_global_registers(hsotg);
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if (ret) {
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dev_err(hsotg->dev, "%s: failed to backup global registers\n",
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__func__);
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return ret;
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}
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if (dwc2_is_host_mode(hsotg)) {
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ret = dwc2_backup_host_registers(hsotg);
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if (ret) {
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dev_err(hsotg->dev, "%s: failed to backup host registers\n",
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__func__);
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return ret;
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}
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} else {
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ret = dwc2_backup_device_registers(hsotg);
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if (ret) {
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dev_err(hsotg->dev, "%s: failed to backup device registers\n",
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__func__);
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return ret;
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}
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}
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/*
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* Clear any pending interrupts since dwc2 will not be able to
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* clear them after entering hibernation.
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*/
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dwc2_writel(0xffffffff, hsotg->regs + GINTSTS);
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/* Put the controller in low power state */
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pcgcctl = dwc2_readl(hsotg->regs + PCGCTL);
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pcgcctl |= PCGCTL_PWRCLMP;
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dwc2_writel(pcgcctl, hsotg->regs + PCGCTL);
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ndelay(20);
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pcgcctl |= PCGCTL_RSTPDWNMODULE;
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dwc2_writel(pcgcctl, hsotg->regs + PCGCTL);
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ndelay(20);
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pcgcctl |= PCGCTL_STOPPCLK;
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dwc2_writel(pcgcctl, hsotg->regs + PCGCTL);
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return ret;
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}
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/**
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* dwc2_wait_for_mode() - Waits for the controller mode.
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* @hsotg: Programming view of the DWC_otg controller.
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* @host_mode: If true, waits for host mode, otherwise device mode.
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*/
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static void dwc2_wait_for_mode(struct dwc2_hsotg *hsotg,
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bool host_mode)
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{
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ktime_t start;
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ktime_t end;
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unsigned int timeout = 110;
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dev_vdbg(hsotg->dev, "Waiting for %s mode\n",
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host_mode ? "host" : "device");
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start = ktime_get();
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while (1) {
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s64 ms;
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if (dwc2_is_host_mode(hsotg) == host_mode) {
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dev_vdbg(hsotg->dev, "%s mode set\n",
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host_mode ? "Host" : "Device");
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break;
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}
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end = ktime_get();
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ms = ktime_to_ms(ktime_sub(end, start));
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if (ms >= (s64)timeout) {
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dev_warn(hsotg->dev, "%s: Couldn't set %s mode\n",
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__func__, host_mode ? "host" : "device");
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break;
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}
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usleep_range(1000, 2000);
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}
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}
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/**
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* dwc2_iddig_filter_enabled() - Returns true if the IDDIG debounce
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* filter is enabled.
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*/
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static bool dwc2_iddig_filter_enabled(struct dwc2_hsotg *hsotg)
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{
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u32 gsnpsid;
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u32 ghwcfg4;
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if (!dwc2_hw_is_otg(hsotg))
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return false;
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/* Check if core configuration includes the IDDIG filter. */
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ghwcfg4 = dwc2_readl(hsotg->regs + GHWCFG4);
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if (!(ghwcfg4 & GHWCFG4_IDDIG_FILT_EN))
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return false;
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/*
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* Check if the IDDIG debounce filter is bypassed. Available
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* in core version >= 3.10a.
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*/
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gsnpsid = dwc2_readl(hsotg->regs + GSNPSID);
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if (gsnpsid >= DWC2_CORE_REV_3_10a) {
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u32 gotgctl = dwc2_readl(hsotg->regs + GOTGCTL);
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if (gotgctl & GOTGCTL_DBNCE_FLTR_BYPASS)
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return false;
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}
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return true;
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}
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/*
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* Do core a soft reset of the core. Be careful with this because it
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* resets all the internal state machines of the core.
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*/
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int dwc2_core_reset(struct dwc2_hsotg *hsotg, bool skip_wait)
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{
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u32 greset;
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int count = 0;
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bool wait_for_host_mode = false;
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dev_vdbg(hsotg->dev, "%s()\n", __func__);
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/*
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* If the current mode is host, either due to the force mode
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* bit being set (which persists after core reset) or the
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* connector id pin, a core soft reset will temporarily reset
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* the mode to device. A delay from the IDDIG debounce filter
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* will occur before going back to host mode.
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*
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* Determine whether we will go back into host mode after a
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* reset and account for this delay after the reset.
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*/
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if (dwc2_iddig_filter_enabled(hsotg)) {
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u32 gotgctl = dwc2_readl(hsotg->regs + GOTGCTL);
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u32 gusbcfg = dwc2_readl(hsotg->regs + GUSBCFG);
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if (!(gotgctl & GOTGCTL_CONID_B) ||
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(gusbcfg & GUSBCFG_FORCEHOSTMODE)) {
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wait_for_host_mode = true;
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}
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}
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/* Core Soft Reset */
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greset = dwc2_readl(hsotg->regs + GRSTCTL);
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greset |= GRSTCTL_CSFTRST;
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dwc2_writel(greset, hsotg->regs + GRSTCTL);
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do {
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udelay(1);
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greset = dwc2_readl(hsotg->regs + GRSTCTL);
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if (++count > 50) {
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dev_warn(hsotg->dev,
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"%s() HANG! Soft Reset GRSTCTL=%0x\n",
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__func__, greset);
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return -EBUSY;
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}
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} while (greset & GRSTCTL_CSFTRST);
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/* Wait for AHB master IDLE state */
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count = 0;
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do {
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udelay(1);
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greset = dwc2_readl(hsotg->regs + GRSTCTL);
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if (++count > 50) {
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dev_warn(hsotg->dev,
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"%s() HANG! AHB Idle GRSTCTL=%0x\n",
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__func__, greset);
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return -EBUSY;
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}
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} while (!(greset & GRSTCTL_AHBIDLE));
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if (wait_for_host_mode && !skip_wait)
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dwc2_wait_for_mode(hsotg, true);
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return 0;
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}
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/*
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* Force the mode of the controller.
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*
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* Forcing the mode is needed for two cases:
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*
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* 1) If the dr_mode is set to either HOST or PERIPHERAL we force the
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* controller to stay in a particular mode regardless of ID pin
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* changes. We do this usually after a core reset.
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*
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* 2) During probe we want to read reset values of the hw
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* configuration registers that are only available in either host or
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* device mode. We may need to force the mode if the current mode does
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* not allow us to access the register in the mode that we want.
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*
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* In either case it only makes sense to force the mode if the
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* controller hardware is OTG capable.
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*
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* Checks are done in this function to determine whether doing a force
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* would be valid or not.
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*
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* If a force is done, it requires a IDDIG debounce filter delay if
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* the filter is configured and enabled. We poll the current mode of
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* the controller to account for this delay.
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*/
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static bool dwc2_force_mode(struct dwc2_hsotg *hsotg, bool host)
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{
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u32 gusbcfg;
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u32 set;
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u32 clear;
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dev_dbg(hsotg->dev, "Forcing mode to %s\n", host ? "host" : "device");
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/*
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* Force mode has no effect if the hardware is not OTG.
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*/
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if (!dwc2_hw_is_otg(hsotg))
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return false;
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/*
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* If dr_mode is either peripheral or host only, there is no
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* need to ever force the mode to the opposite mode.
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*/
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if (WARN_ON(host && hsotg->dr_mode == USB_DR_MODE_PERIPHERAL))
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return false;
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if (WARN_ON(!host && hsotg->dr_mode == USB_DR_MODE_HOST))
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return false;
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gusbcfg = dwc2_readl(hsotg->regs + GUSBCFG);
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set = host ? GUSBCFG_FORCEHOSTMODE : GUSBCFG_FORCEDEVMODE;
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clear = host ? GUSBCFG_FORCEDEVMODE : GUSBCFG_FORCEHOSTMODE;
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gusbcfg &= ~clear;
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gusbcfg |= set;
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dwc2_writel(gusbcfg, hsotg->regs + GUSBCFG);
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dwc2_wait_for_mode(hsotg, host);
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return true;
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}
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/**
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* dwc2_clear_force_mode() - Clears the force mode bits.
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*
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* After clearing the bits, wait up to 100 ms to account for any
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* potential IDDIG filter delay. We can't know if we expect this delay
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* or not because the value of the connector ID status is affected by
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* the force mode. We only need to call this once during probe if
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* dr_mode == OTG.
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*/
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void dwc2_clear_force_mode(struct dwc2_hsotg *hsotg)
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{
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u32 gusbcfg;
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gusbcfg = dwc2_readl(hsotg->regs + GUSBCFG);
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gusbcfg &= ~GUSBCFG_FORCEHOSTMODE;
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gusbcfg &= ~GUSBCFG_FORCEDEVMODE;
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dwc2_writel(gusbcfg, hsotg->regs + GUSBCFG);
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if (dwc2_iddig_filter_enabled(hsotg))
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msleep(100);
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}
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/*
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* Sets or clears force mode based on the dr_mode parameter.
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*/
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void dwc2_force_dr_mode(struct dwc2_hsotg *hsotg)
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{
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bool ret;
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switch (hsotg->dr_mode) {
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case USB_DR_MODE_HOST:
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ret = dwc2_force_mode(hsotg, true);
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/*
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* NOTE: This is required for some rockchip soc based
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* platforms on their host-only dwc2.
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*/
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if (!ret)
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msleep(50);
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break;
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case USB_DR_MODE_PERIPHERAL:
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dwc2_force_mode(hsotg, false);
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break;
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case USB_DR_MODE_OTG:
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dwc2_clear_force_mode(hsotg);
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break;
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default:
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dev_warn(hsotg->dev, "%s() Invalid dr_mode=%d\n",
|
|
__func__, hsotg->dr_mode);
|
|
break;
|
|
}
|
|
}
|
|
|
|
/*
|
|
* Do core a soft reset of the core. Be careful with this because it
|
|
* resets all the internal state machines of the core.
|
|
*
|
|
* Additionally this will apply force mode as per the hsotg->dr_mode
|
|
* parameter.
|
|
*/
|
|
int dwc2_core_reset_and_force_dr_mode(struct dwc2_hsotg *hsotg)
|
|
{
|
|
int retval;
|
|
|
|
retval = dwc2_core_reset(hsotg, false);
|
|
if (retval)
|
|
return retval;
|
|
|
|
dwc2_force_dr_mode(hsotg);
|
|
return 0;
|
|
}
|
|
|
|
/**
|
|
* dwc2_dump_host_registers() - Prints the host registers
|
|
*
|
|
* @hsotg: Programming view of DWC_otg controller
|
|
*
|
|
* NOTE: This function will be removed once the peripheral controller code
|
|
* is integrated and the driver is stable
|
|
*/
|
|
void dwc2_dump_host_registers(struct dwc2_hsotg *hsotg)
|
|
{
|
|
#ifdef DEBUG
|
|
u32 __iomem *addr;
|
|
int i;
|
|
|
|
dev_dbg(hsotg->dev, "Host Global Registers\n");
|
|
addr = hsotg->regs + HCFG;
|
|
dev_dbg(hsotg->dev, "HCFG @0x%08lX : 0x%08X\n",
|
|
(unsigned long)addr, dwc2_readl(addr));
|
|
addr = hsotg->regs + HFIR;
|
|
dev_dbg(hsotg->dev, "HFIR @0x%08lX : 0x%08X\n",
|
|
(unsigned long)addr, dwc2_readl(addr));
|
|
addr = hsotg->regs + HFNUM;
|
|
dev_dbg(hsotg->dev, "HFNUM @0x%08lX : 0x%08X\n",
|
|
(unsigned long)addr, dwc2_readl(addr));
|
|
addr = hsotg->regs + HPTXSTS;
|
|
dev_dbg(hsotg->dev, "HPTXSTS @0x%08lX : 0x%08X\n",
|
|
(unsigned long)addr, dwc2_readl(addr));
|
|
addr = hsotg->regs + HAINT;
|
|
dev_dbg(hsotg->dev, "HAINT @0x%08lX : 0x%08X\n",
|
|
(unsigned long)addr, dwc2_readl(addr));
|
|
addr = hsotg->regs + HAINTMSK;
|
|
dev_dbg(hsotg->dev, "HAINTMSK @0x%08lX : 0x%08X\n",
|
|
(unsigned long)addr, dwc2_readl(addr));
|
|
if (hsotg->params.dma_desc_enable) {
|
|
addr = hsotg->regs + HFLBADDR;
|
|
dev_dbg(hsotg->dev, "HFLBADDR @0x%08lX : 0x%08X\n",
|
|
(unsigned long)addr, dwc2_readl(addr));
|
|
}
|
|
|
|
addr = hsotg->regs + HPRT0;
|
|
dev_dbg(hsotg->dev, "HPRT0 @0x%08lX : 0x%08X\n",
|
|
(unsigned long)addr, dwc2_readl(addr));
|
|
|
|
for (i = 0; i < hsotg->params.host_channels; i++) {
|
|
dev_dbg(hsotg->dev, "Host Channel %d Specific Registers\n", i);
|
|
addr = hsotg->regs + HCCHAR(i);
|
|
dev_dbg(hsotg->dev, "HCCHAR @0x%08lX : 0x%08X\n",
|
|
(unsigned long)addr, dwc2_readl(addr));
|
|
addr = hsotg->regs + HCSPLT(i);
|
|
dev_dbg(hsotg->dev, "HCSPLT @0x%08lX : 0x%08X\n",
|
|
(unsigned long)addr, dwc2_readl(addr));
|
|
addr = hsotg->regs + HCINT(i);
|
|
dev_dbg(hsotg->dev, "HCINT @0x%08lX : 0x%08X\n",
|
|
(unsigned long)addr, dwc2_readl(addr));
|
|
addr = hsotg->regs + HCINTMSK(i);
|
|
dev_dbg(hsotg->dev, "HCINTMSK @0x%08lX : 0x%08X\n",
|
|
(unsigned long)addr, dwc2_readl(addr));
|
|
addr = hsotg->regs + HCTSIZ(i);
|
|
dev_dbg(hsotg->dev, "HCTSIZ @0x%08lX : 0x%08X\n",
|
|
(unsigned long)addr, dwc2_readl(addr));
|
|
addr = hsotg->regs + HCDMA(i);
|
|
dev_dbg(hsotg->dev, "HCDMA @0x%08lX : 0x%08X\n",
|
|
(unsigned long)addr, dwc2_readl(addr));
|
|
if (hsotg->params.dma_desc_enable) {
|
|
addr = hsotg->regs + HCDMAB(i);
|
|
dev_dbg(hsotg->dev, "HCDMAB @0x%08lX : 0x%08X\n",
|
|
(unsigned long)addr, dwc2_readl(addr));
|
|
}
|
|
}
|
|
#endif
|
|
}
|
|
|
|
/**
|
|
* dwc2_dump_global_registers() - Prints the core global registers
|
|
*
|
|
* @hsotg: Programming view of DWC_otg controller
|
|
*
|
|
* NOTE: This function will be removed once the peripheral controller code
|
|
* is integrated and the driver is stable
|
|
*/
|
|
void dwc2_dump_global_registers(struct dwc2_hsotg *hsotg)
|
|
{
|
|
#ifdef DEBUG
|
|
u32 __iomem *addr;
|
|
|
|
dev_dbg(hsotg->dev, "Core Global Registers\n");
|
|
addr = hsotg->regs + GOTGCTL;
|
|
dev_dbg(hsotg->dev, "GOTGCTL @0x%08lX : 0x%08X\n",
|
|
(unsigned long)addr, dwc2_readl(addr));
|
|
addr = hsotg->regs + GOTGINT;
|
|
dev_dbg(hsotg->dev, "GOTGINT @0x%08lX : 0x%08X\n",
|
|
(unsigned long)addr, dwc2_readl(addr));
|
|
addr = hsotg->regs + GAHBCFG;
|
|
dev_dbg(hsotg->dev, "GAHBCFG @0x%08lX : 0x%08X\n",
|
|
(unsigned long)addr, dwc2_readl(addr));
|
|
addr = hsotg->regs + GUSBCFG;
|
|
dev_dbg(hsotg->dev, "GUSBCFG @0x%08lX : 0x%08X\n",
|
|
(unsigned long)addr, dwc2_readl(addr));
|
|
addr = hsotg->regs + GRSTCTL;
|
|
dev_dbg(hsotg->dev, "GRSTCTL @0x%08lX : 0x%08X\n",
|
|
(unsigned long)addr, dwc2_readl(addr));
|
|
addr = hsotg->regs + GINTSTS;
|
|
dev_dbg(hsotg->dev, "GINTSTS @0x%08lX : 0x%08X\n",
|
|
(unsigned long)addr, dwc2_readl(addr));
|
|
addr = hsotg->regs + GINTMSK;
|
|
dev_dbg(hsotg->dev, "GINTMSK @0x%08lX : 0x%08X\n",
|
|
(unsigned long)addr, dwc2_readl(addr));
|
|
addr = hsotg->regs + GRXSTSR;
|
|
dev_dbg(hsotg->dev, "GRXSTSR @0x%08lX : 0x%08X\n",
|
|
(unsigned long)addr, dwc2_readl(addr));
|
|
addr = hsotg->regs + GRXFSIZ;
|
|
dev_dbg(hsotg->dev, "GRXFSIZ @0x%08lX : 0x%08X\n",
|
|
(unsigned long)addr, dwc2_readl(addr));
|
|
addr = hsotg->regs + GNPTXFSIZ;
|
|
dev_dbg(hsotg->dev, "GNPTXFSIZ @0x%08lX : 0x%08X\n",
|
|
(unsigned long)addr, dwc2_readl(addr));
|
|
addr = hsotg->regs + GNPTXSTS;
|
|
dev_dbg(hsotg->dev, "GNPTXSTS @0x%08lX : 0x%08X\n",
|
|
(unsigned long)addr, dwc2_readl(addr));
|
|
addr = hsotg->regs + GI2CCTL;
|
|
dev_dbg(hsotg->dev, "GI2CCTL @0x%08lX : 0x%08X\n",
|
|
(unsigned long)addr, dwc2_readl(addr));
|
|
addr = hsotg->regs + GPVNDCTL;
|
|
dev_dbg(hsotg->dev, "GPVNDCTL @0x%08lX : 0x%08X\n",
|
|
(unsigned long)addr, dwc2_readl(addr));
|
|
addr = hsotg->regs + GGPIO;
|
|
dev_dbg(hsotg->dev, "GGPIO @0x%08lX : 0x%08X\n",
|
|
(unsigned long)addr, dwc2_readl(addr));
|
|
addr = hsotg->regs + GUID;
|
|
dev_dbg(hsotg->dev, "GUID @0x%08lX : 0x%08X\n",
|
|
(unsigned long)addr, dwc2_readl(addr));
|
|
addr = hsotg->regs + GSNPSID;
|
|
dev_dbg(hsotg->dev, "GSNPSID @0x%08lX : 0x%08X\n",
|
|
(unsigned long)addr, dwc2_readl(addr));
|
|
addr = hsotg->regs + GHWCFG1;
|
|
dev_dbg(hsotg->dev, "GHWCFG1 @0x%08lX : 0x%08X\n",
|
|
(unsigned long)addr, dwc2_readl(addr));
|
|
addr = hsotg->regs + GHWCFG2;
|
|
dev_dbg(hsotg->dev, "GHWCFG2 @0x%08lX : 0x%08X\n",
|
|
(unsigned long)addr, dwc2_readl(addr));
|
|
addr = hsotg->regs + GHWCFG3;
|
|
dev_dbg(hsotg->dev, "GHWCFG3 @0x%08lX : 0x%08X\n",
|
|
(unsigned long)addr, dwc2_readl(addr));
|
|
addr = hsotg->regs + GHWCFG4;
|
|
dev_dbg(hsotg->dev, "GHWCFG4 @0x%08lX : 0x%08X\n",
|
|
(unsigned long)addr, dwc2_readl(addr));
|
|
addr = hsotg->regs + GLPMCFG;
|
|
dev_dbg(hsotg->dev, "GLPMCFG @0x%08lX : 0x%08X\n",
|
|
(unsigned long)addr, dwc2_readl(addr));
|
|
addr = hsotg->regs + GPWRDN;
|
|
dev_dbg(hsotg->dev, "GPWRDN @0x%08lX : 0x%08X\n",
|
|
(unsigned long)addr, dwc2_readl(addr));
|
|
addr = hsotg->regs + GDFIFOCFG;
|
|
dev_dbg(hsotg->dev, "GDFIFOCFG @0x%08lX : 0x%08X\n",
|
|
(unsigned long)addr, dwc2_readl(addr));
|
|
addr = hsotg->regs + HPTXFSIZ;
|
|
dev_dbg(hsotg->dev, "HPTXFSIZ @0x%08lX : 0x%08X\n",
|
|
(unsigned long)addr, dwc2_readl(addr));
|
|
|
|
addr = hsotg->regs + PCGCTL;
|
|
dev_dbg(hsotg->dev, "PCGCTL @0x%08lX : 0x%08X\n",
|
|
(unsigned long)addr, dwc2_readl(addr));
|
|
#endif
|
|
}
|
|
|
|
/**
|
|
* dwc2_flush_tx_fifo() - Flushes a Tx FIFO
|
|
*
|
|
* @hsotg: Programming view of DWC_otg controller
|
|
* @num: Tx FIFO to flush
|
|
*/
|
|
void dwc2_flush_tx_fifo(struct dwc2_hsotg *hsotg, const int num)
|
|
{
|
|
u32 greset;
|
|
int count = 0;
|
|
|
|
dev_vdbg(hsotg->dev, "Flush Tx FIFO %d\n", num);
|
|
|
|
greset = GRSTCTL_TXFFLSH;
|
|
greset |= num << GRSTCTL_TXFNUM_SHIFT & GRSTCTL_TXFNUM_MASK;
|
|
dwc2_writel(greset, hsotg->regs + GRSTCTL);
|
|
|
|
do {
|
|
greset = dwc2_readl(hsotg->regs + GRSTCTL);
|
|
if (++count > 10000) {
|
|
dev_warn(hsotg->dev,
|
|
"%s() HANG! GRSTCTL=%0x GNPTXSTS=0x%08x\n",
|
|
__func__, greset,
|
|
dwc2_readl(hsotg->regs + GNPTXSTS));
|
|
break;
|
|
}
|
|
udelay(1);
|
|
} while (greset & GRSTCTL_TXFFLSH);
|
|
|
|
/* Wait for at least 3 PHY Clocks */
|
|
udelay(1);
|
|
}
|
|
|
|
/**
|
|
* dwc2_flush_rx_fifo() - Flushes the Rx FIFO
|
|
*
|
|
* @hsotg: Programming view of DWC_otg controller
|
|
*/
|
|
void dwc2_flush_rx_fifo(struct dwc2_hsotg *hsotg)
|
|
{
|
|
u32 greset;
|
|
int count = 0;
|
|
|
|
dev_vdbg(hsotg->dev, "%s()\n", __func__);
|
|
|
|
greset = GRSTCTL_RXFFLSH;
|
|
dwc2_writel(greset, hsotg->regs + GRSTCTL);
|
|
|
|
do {
|
|
greset = dwc2_readl(hsotg->regs + GRSTCTL);
|
|
if (++count > 10000) {
|
|
dev_warn(hsotg->dev, "%s() HANG! GRSTCTL=%0x\n",
|
|
__func__, greset);
|
|
break;
|
|
}
|
|
udelay(1);
|
|
} while (greset & GRSTCTL_RXFFLSH);
|
|
|
|
/* Wait for at least 3 PHY Clocks */
|
|
udelay(1);
|
|
}
|
|
|
|
/*
|
|
* Forces either host or device mode if the controller is not
|
|
* currently in that mode.
|
|
*
|
|
* Returns true if the mode was forced.
|
|
*/
|
|
bool dwc2_force_mode_if_needed(struct dwc2_hsotg *hsotg, bool host)
|
|
{
|
|
if (host && dwc2_is_host_mode(hsotg))
|
|
return false;
|
|
else if (!host && dwc2_is_device_mode(hsotg))
|
|
return false;
|
|
|
|
return dwc2_force_mode(hsotg, host);
|
|
}
|
|
|
|
bool dwc2_is_controller_alive(struct dwc2_hsotg *hsotg)
|
|
{
|
|
if (dwc2_readl(hsotg->regs + GSNPSID) == 0xffffffff)
|
|
return false;
|
|
else
|
|
return true;
|
|
}
|
|
|
|
/**
|
|
* dwc2_enable_global_interrupts() - Enables the controller's Global
|
|
* Interrupt in the AHB Config register
|
|
*
|
|
* @hsotg: Programming view of DWC_otg controller
|
|
*/
|
|
void dwc2_enable_global_interrupts(struct dwc2_hsotg *hsotg)
|
|
{
|
|
u32 ahbcfg = dwc2_readl(hsotg->regs + GAHBCFG);
|
|
|
|
ahbcfg |= GAHBCFG_GLBL_INTR_EN;
|
|
dwc2_writel(ahbcfg, hsotg->regs + GAHBCFG);
|
|
}
|
|
|
|
/**
|
|
* dwc2_disable_global_interrupts() - Disables the controller's Global
|
|
* Interrupt in the AHB Config register
|
|
*
|
|
* @hsotg: Programming view of DWC_otg controller
|
|
*/
|
|
void dwc2_disable_global_interrupts(struct dwc2_hsotg *hsotg)
|
|
{
|
|
u32 ahbcfg = dwc2_readl(hsotg->regs + GAHBCFG);
|
|
|
|
ahbcfg &= ~GAHBCFG_GLBL_INTR_EN;
|
|
dwc2_writel(ahbcfg, hsotg->regs + GAHBCFG);
|
|
}
|
|
|
|
/* Returns the controller's GHWCFG2.OTG_MODE. */
|
|
unsigned int dwc2_op_mode(struct dwc2_hsotg *hsotg)
|
|
{
|
|
u32 ghwcfg2 = dwc2_readl(hsotg->regs + GHWCFG2);
|
|
|
|
return (ghwcfg2 & GHWCFG2_OP_MODE_MASK) >>
|
|
GHWCFG2_OP_MODE_SHIFT;
|
|
}
|
|
|
|
/* Returns true if the controller is capable of DRD. */
|
|
bool dwc2_hw_is_otg(struct dwc2_hsotg *hsotg)
|
|
{
|
|
unsigned int op_mode = dwc2_op_mode(hsotg);
|
|
|
|
return (op_mode == GHWCFG2_OP_MODE_HNP_SRP_CAPABLE) ||
|
|
(op_mode == GHWCFG2_OP_MODE_SRP_ONLY_CAPABLE) ||
|
|
(op_mode == GHWCFG2_OP_MODE_NO_HNP_SRP_CAPABLE);
|
|
}
|
|
|
|
/* Returns true if the controller is host-only. */
|
|
bool dwc2_hw_is_host(struct dwc2_hsotg *hsotg)
|
|
{
|
|
unsigned int op_mode = dwc2_op_mode(hsotg);
|
|
|
|
return (op_mode == GHWCFG2_OP_MODE_SRP_CAPABLE_HOST) ||
|
|
(op_mode == GHWCFG2_OP_MODE_NO_SRP_CAPABLE_HOST);
|
|
}
|
|
|
|
/* Returns true if the controller is device-only. */
|
|
bool dwc2_hw_is_device(struct dwc2_hsotg *hsotg)
|
|
{
|
|
unsigned int op_mode = dwc2_op_mode(hsotg);
|
|
|
|
return (op_mode == GHWCFG2_OP_MODE_SRP_CAPABLE_DEVICE) ||
|
|
(op_mode == GHWCFG2_OP_MODE_NO_SRP_CAPABLE_DEVICE);
|
|
}
|
|
|
|
MODULE_DESCRIPTION("DESIGNWARE HS OTG Core");
|
|
MODULE_AUTHOR("Synopsys, Inc.");
|
|
MODULE_LICENSE("Dual BSD/GPL");
|