595 lines
14 KiB
C
595 lines
14 KiB
C
/* linux/arch/arm/mach-s5p64x0/clock-s5p6440.c
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*
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* Copyright (c) 2009-2010 Samsung Electronics Co., Ltd.
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* http://www.samsung.com
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*
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* S5P6440 - Clock support
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#include <linux/init.h>
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#include <linux/module.h>
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#include <linux/kernel.h>
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#include <linux/list.h>
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#include <linux/errno.h>
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#include <linux/err.h>
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#include <linux/clk.h>
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#include <linux/sysdev.h>
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#include <linux/io.h>
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#include <mach/hardware.h>
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#include <mach/map.h>
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#include <mach/regs-clock.h>
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#include <mach/s5p64x0-clock.h>
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#include <plat/cpu-freq.h>
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#include <plat/clock.h>
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#include <plat/cpu.h>
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#include <plat/pll.h>
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#include <plat/s5p-clock.h>
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#include <plat/clock-clksrc.h>
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#include "common.h"
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static u32 epll_div[][5] = {
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{ 36000000, 0, 48, 1, 4 },
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{ 48000000, 0, 32, 1, 3 },
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{ 60000000, 0, 40, 1, 3 },
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{ 72000000, 0, 48, 1, 3 },
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{ 84000000, 0, 28, 1, 2 },
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{ 96000000, 0, 32, 1, 2 },
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{ 32768000, 45264, 43, 1, 4 },
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{ 45158000, 6903, 30, 1, 3 },
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{ 49152000, 50332, 32, 1, 3 },
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{ 67738000, 10398, 45, 1, 3 },
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{ 73728000, 9961, 49, 1, 3 }
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};
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static int s5p6440_epll_set_rate(struct clk *clk, unsigned long rate)
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{
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unsigned int epll_con, epll_con_k;
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unsigned int i;
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if (clk->rate == rate) /* Return if nothing changed */
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return 0;
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epll_con = __raw_readl(S5P64X0_EPLL_CON);
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epll_con_k = __raw_readl(S5P64X0_EPLL_CON_K);
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epll_con_k &= ~(PLL90XX_KDIV_MASK);
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epll_con &= ~(PLL90XX_MDIV_MASK | PLL90XX_PDIV_MASK | PLL90XX_SDIV_MASK);
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for (i = 0; i < ARRAY_SIZE(epll_div); i++) {
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if (epll_div[i][0] == rate) {
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epll_con_k |= (epll_div[i][1] << PLL90XX_KDIV_SHIFT);
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epll_con |= (epll_div[i][2] << PLL90XX_MDIV_SHIFT) |
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(epll_div[i][3] << PLL90XX_PDIV_SHIFT) |
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(epll_div[i][4] << PLL90XX_SDIV_SHIFT);
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break;
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}
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}
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if (i == ARRAY_SIZE(epll_div)) {
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printk(KERN_ERR "%s: Invalid Clock EPLL Frequency\n", __func__);
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return -EINVAL;
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}
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__raw_writel(epll_con, S5P64X0_EPLL_CON);
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__raw_writel(epll_con_k, S5P64X0_EPLL_CON_K);
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printk(KERN_WARNING "EPLL Rate changes from %lu to %lu\n",
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clk->rate, rate);
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clk->rate = rate;
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return 0;
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}
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static struct clk_ops s5p6440_epll_ops = {
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.get_rate = s5p_epll_get_rate,
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.set_rate = s5p6440_epll_set_rate,
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};
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static struct clksrc_clk clk_hclk = {
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.clk = {
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.name = "clk_hclk",
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.parent = &clk_armclk.clk,
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},
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.reg_div = { .reg = S5P64X0_CLK_DIV0, .shift = 8, .size = 4 },
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};
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static struct clksrc_clk clk_pclk = {
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.clk = {
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.name = "clk_pclk",
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.parent = &clk_hclk.clk,
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},
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.reg_div = { .reg = S5P64X0_CLK_DIV0, .shift = 12, .size = 4 },
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};
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static struct clksrc_clk clk_hclk_low = {
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.clk = {
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.name = "clk_hclk_low",
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},
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.sources = &clkset_hclk_low,
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.reg_src = { .reg = S5P64X0_SYS_OTHERS, .shift = 6, .size = 1 },
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.reg_div = { .reg = S5P64X0_CLK_DIV3, .shift = 8, .size = 4 },
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};
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static struct clksrc_clk clk_pclk_low = {
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.clk = {
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.name = "clk_pclk_low",
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.parent = &clk_hclk_low.clk,
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},
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.reg_div = { .reg = S5P64X0_CLK_DIV3, .shift = 12, .size = 4 },
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};
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/*
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* The following clocks will be disabled during clock initialization. It is
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* recommended to keep the following clocks disabled until the driver requests
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* for enabling the clock.
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*/
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static struct clk init_clocks_off[] = {
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{
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.name = "nand",
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.parent = &clk_hclk.clk,
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.enable = s5p64x0_mem_ctrl,
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.ctrlbit = (1 << 2),
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}, {
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.name = "post",
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.parent = &clk_hclk_low.clk,
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.enable = s5p64x0_hclk0_ctrl,
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.ctrlbit = (1 << 5)
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}, {
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.name = "2d",
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.parent = &clk_hclk.clk,
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.enable = s5p64x0_hclk0_ctrl,
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.ctrlbit = (1 << 8),
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}, {
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.name = "dma",
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.devname = "dma-pl330",
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.parent = &clk_hclk_low.clk,
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.enable = s5p64x0_hclk0_ctrl,
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.ctrlbit = (1 << 12),
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}, {
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.name = "hsmmc",
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.devname = "s3c-sdhci.0",
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.parent = &clk_hclk_low.clk,
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.enable = s5p64x0_hclk0_ctrl,
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.ctrlbit = (1 << 17),
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}, {
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.name = "hsmmc",
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.devname = "s3c-sdhci.1",
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.parent = &clk_hclk_low.clk,
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.enable = s5p64x0_hclk0_ctrl,
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.ctrlbit = (1 << 18),
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}, {
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.name = "hsmmc",
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.devname = "s3c-sdhci.2",
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.parent = &clk_hclk_low.clk,
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.enable = s5p64x0_hclk0_ctrl,
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.ctrlbit = (1 << 19),
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}, {
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.name = "otg",
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.parent = &clk_hclk_low.clk,
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.enable = s5p64x0_hclk0_ctrl,
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.ctrlbit = (1 << 20)
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}, {
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.name = "irom",
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.parent = &clk_hclk.clk,
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.enable = s5p64x0_hclk0_ctrl,
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.ctrlbit = (1 << 25),
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}, {
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.name = "lcd",
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.parent = &clk_hclk_low.clk,
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.enable = s5p64x0_hclk1_ctrl,
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.ctrlbit = (1 << 1),
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}, {
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.name = "hclk_fimgvg",
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.parent = &clk_hclk.clk,
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.enable = s5p64x0_hclk1_ctrl,
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.ctrlbit = (1 << 2),
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}, {
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.name = "tsi",
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.parent = &clk_hclk_low.clk,
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.enable = s5p64x0_hclk1_ctrl,
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.ctrlbit = (1 << 0),
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}, {
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.name = "watchdog",
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.parent = &clk_pclk_low.clk,
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.enable = s5p64x0_pclk_ctrl,
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.ctrlbit = (1 << 5),
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}, {
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.name = "rtc",
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.parent = &clk_pclk_low.clk,
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.enable = s5p64x0_pclk_ctrl,
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.ctrlbit = (1 << 6),
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}, {
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.name = "timers",
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.parent = &clk_pclk_low.clk,
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.enable = s5p64x0_pclk_ctrl,
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.ctrlbit = (1 << 7),
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}, {
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.name = "pcm",
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.parent = &clk_pclk_low.clk,
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.enable = s5p64x0_pclk_ctrl,
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.ctrlbit = (1 << 8),
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}, {
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.name = "adc",
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.parent = &clk_pclk_low.clk,
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.enable = s5p64x0_pclk_ctrl,
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.ctrlbit = (1 << 12),
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}, {
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.name = "i2c",
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.parent = &clk_pclk_low.clk,
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.enable = s5p64x0_pclk_ctrl,
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.ctrlbit = (1 << 17),
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}, {
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.name = "spi",
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.devname = "s3c64xx-spi.0",
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.parent = &clk_pclk_low.clk,
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.enable = s5p64x0_pclk_ctrl,
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.ctrlbit = (1 << 21),
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}, {
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.name = "spi",
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.devname = "s3c64xx-spi.1",
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.parent = &clk_pclk_low.clk,
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.enable = s5p64x0_pclk_ctrl,
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.ctrlbit = (1 << 22),
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}, {
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.name = "gps",
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.parent = &clk_pclk_low.clk,
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.enable = s5p64x0_pclk_ctrl,
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.ctrlbit = (1 << 25),
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}, {
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.name = "iis",
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.devname = "samsung-i2s.0",
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.parent = &clk_pclk_low.clk,
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.enable = s5p64x0_pclk_ctrl,
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.ctrlbit = (1 << 26),
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}, {
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.name = "dsim",
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.parent = &clk_pclk_low.clk,
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.enable = s5p64x0_pclk_ctrl,
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.ctrlbit = (1 << 28),
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}, {
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.name = "etm",
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.parent = &clk_pclk.clk,
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.enable = s5p64x0_pclk_ctrl,
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.ctrlbit = (1 << 29),
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}, {
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.name = "dmc0",
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.parent = &clk_pclk.clk,
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.enable = s5p64x0_pclk_ctrl,
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.ctrlbit = (1 << 30),
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}, {
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.name = "pclk_fimgvg",
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.parent = &clk_pclk.clk,
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.enable = s5p64x0_pclk_ctrl,
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.ctrlbit = (1 << 31),
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}, {
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.name = "sclk_spi_48",
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.devname = "s3c64xx-spi.0",
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.parent = &clk_48m,
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.enable = s5p64x0_sclk_ctrl,
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.ctrlbit = (1 << 22),
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}, {
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.name = "sclk_spi_48",
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.devname = "s3c64xx-spi.1",
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.parent = &clk_48m,
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.enable = s5p64x0_sclk_ctrl,
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.ctrlbit = (1 << 23),
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}, {
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.name = "mmc_48m",
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.devname = "s3c-sdhci.0",
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.parent = &clk_48m,
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.enable = s5p64x0_sclk_ctrl,
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.ctrlbit = (1 << 27),
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}, {
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.name = "mmc_48m",
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.devname = "s3c-sdhci.1",
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.parent = &clk_48m,
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.enable = s5p64x0_sclk_ctrl,
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.ctrlbit = (1 << 28),
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}, {
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.name = "mmc_48m",
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.devname = "s3c-sdhci.2",
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.parent = &clk_48m,
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.enable = s5p64x0_sclk_ctrl,
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.ctrlbit = (1 << 29),
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},
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};
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/*
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* The following clocks will be enabled during clock initialization.
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*/
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static struct clk init_clocks[] = {
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{
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.name = "intc",
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.parent = &clk_hclk.clk,
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.enable = s5p64x0_hclk0_ctrl,
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.ctrlbit = (1 << 1),
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}, {
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.name = "mem",
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.parent = &clk_hclk.clk,
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.enable = s5p64x0_hclk0_ctrl,
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.ctrlbit = (1 << 21),
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}, {
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.name = "uart",
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.devname = "s3c6400-uart.0",
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.parent = &clk_pclk_low.clk,
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.enable = s5p64x0_pclk_ctrl,
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.ctrlbit = (1 << 1),
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}, {
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.name = "uart",
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.devname = "s3c6400-uart.1",
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.parent = &clk_pclk_low.clk,
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.enable = s5p64x0_pclk_ctrl,
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.ctrlbit = (1 << 2),
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}, {
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.name = "uart",
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.devname = "s3c6400-uart.2",
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.parent = &clk_pclk_low.clk,
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.enable = s5p64x0_pclk_ctrl,
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.ctrlbit = (1 << 3),
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}, {
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.name = "uart",
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.devname = "s3c6400-uart.3",
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.parent = &clk_pclk_low.clk,
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.enable = s5p64x0_pclk_ctrl,
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.ctrlbit = (1 << 4),
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}, {
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.name = "gpio",
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.parent = &clk_pclk_low.clk,
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.enable = s5p64x0_pclk_ctrl,
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.ctrlbit = (1 << 18),
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},
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};
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static struct clk clk_iis_cd_v40 = {
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.name = "iis_cdclk_v40",
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};
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static struct clk clk_pcm_cd = {
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.name = "pcm_cdclk",
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};
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static struct clk *clkset_group1_list[] = {
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&clk_mout_epll.clk,
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&clk_dout_mpll.clk,
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&clk_fin_epll,
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};
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static struct clksrc_sources clkset_group1 = {
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.sources = clkset_group1_list,
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.nr_sources = ARRAY_SIZE(clkset_group1_list),
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};
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static struct clk *clkset_uart_list[] = {
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&clk_mout_epll.clk,
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&clk_dout_mpll.clk,
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};
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static struct clksrc_sources clkset_uart = {
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.sources = clkset_uart_list,
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.nr_sources = ARRAY_SIZE(clkset_uart_list),
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};
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static struct clk *clkset_audio_list[] = {
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&clk_mout_epll.clk,
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&clk_dout_mpll.clk,
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&clk_fin_epll,
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&clk_iis_cd_v40,
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&clk_pcm_cd,
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};
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static struct clksrc_sources clkset_audio = {
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.sources = clkset_audio_list,
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.nr_sources = ARRAY_SIZE(clkset_audio_list),
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};
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static struct clksrc_clk clksrcs[] = {
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{
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.clk = {
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.name = "sclk_mmc",
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.devname = "s3c-sdhci.0",
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.ctrlbit = (1 << 24),
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.enable = s5p64x0_sclk_ctrl,
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},
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.sources = &clkset_group1,
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.reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 18, .size = 2 },
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.reg_div = { .reg = S5P64X0_CLK_DIV1, .shift = 0, .size = 4 },
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}, {
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.clk = {
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.name = "sclk_mmc",
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.devname = "s3c-sdhci.1",
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.ctrlbit = (1 << 25),
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.enable = s5p64x0_sclk_ctrl,
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},
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.sources = &clkset_group1,
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.reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 20, .size = 2 },
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.reg_div = { .reg = S5P64X0_CLK_DIV1, .shift = 4, .size = 4 },
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}, {
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.clk = {
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.name = "sclk_mmc",
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.devname = "s3c-sdhci.2",
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.ctrlbit = (1 << 26),
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.enable = s5p64x0_sclk_ctrl,
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},
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.sources = &clkset_group1,
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.reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 22, .size = 2 },
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.reg_div = { .reg = S5P64X0_CLK_DIV1, .shift = 8, .size = 4 },
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}, {
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.clk = {
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.name = "uclk1",
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.ctrlbit = (1 << 5),
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.enable = s5p64x0_sclk_ctrl,
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},
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.sources = &clkset_uart,
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.reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 13, .size = 1 },
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.reg_div = { .reg = S5P64X0_CLK_DIV2, .shift = 16, .size = 4 },
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}, {
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.clk = {
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.name = "sclk_spi",
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.devname = "s3c64xx-spi.0",
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.ctrlbit = (1 << 20),
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.enable = s5p64x0_sclk_ctrl,
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},
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.sources = &clkset_group1,
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.reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 14, .size = 2 },
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.reg_div = { .reg = S5P64X0_CLK_DIV2, .shift = 0, .size = 4 },
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}, {
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.clk = {
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.name = "sclk_spi",
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.devname = "s3c64xx-spi.1",
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.ctrlbit = (1 << 21),
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.enable = s5p64x0_sclk_ctrl,
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},
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.sources = &clkset_group1,
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.reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 16, .size = 2 },
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.reg_div = { .reg = S5P64X0_CLK_DIV2, .shift = 4, .size = 4 },
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}, {
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.clk = {
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.name = "sclk_post",
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.ctrlbit = (1 << 10),
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.enable = s5p64x0_sclk_ctrl,
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},
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.sources = &clkset_group1,
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.reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 26, .size = 2 },
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.reg_div = { .reg = S5P64X0_CLK_DIV1, .shift = 12, .size = 4 },
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}, {
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.clk = {
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.name = "sclk_dispcon",
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.ctrlbit = (1 << 1),
|
|
.enable = s5p64x0_sclk1_ctrl,
|
|
},
|
|
.sources = &clkset_group1,
|
|
.reg_src = { .reg = S5P64X0_CLK_SRC1, .shift = 4, .size = 2 },
|
|
.reg_div = { .reg = S5P64X0_CLK_DIV3, .shift = 0, .size = 4 },
|
|
}, {
|
|
.clk = {
|
|
.name = "sclk_fimgvg",
|
|
.ctrlbit = (1 << 2),
|
|
.enable = s5p64x0_sclk1_ctrl,
|
|
},
|
|
.sources = &clkset_group1,
|
|
.reg_src = { .reg = S5P64X0_CLK_SRC1, .shift = 8, .size = 2 },
|
|
.reg_div = { .reg = S5P64X0_CLK_DIV3, .shift = 4, .size = 4 },
|
|
}, {
|
|
.clk = {
|
|
.name = "sclk_audio2",
|
|
.ctrlbit = (1 << 11),
|
|
.enable = s5p64x0_sclk_ctrl,
|
|
},
|
|
.sources = &clkset_audio,
|
|
.reg_src = { .reg = S5P64X0_CLK_SRC1, .shift = 0, .size = 3 },
|
|
.reg_div = { .reg = S5P64X0_CLK_DIV2, .shift = 24, .size = 4 },
|
|
},
|
|
};
|
|
|
|
/* Clock initialization code */
|
|
static struct clksrc_clk *sysclks[] = {
|
|
&clk_mout_apll,
|
|
&clk_mout_epll,
|
|
&clk_mout_mpll,
|
|
&clk_dout_mpll,
|
|
&clk_armclk,
|
|
&clk_hclk,
|
|
&clk_pclk,
|
|
&clk_hclk_low,
|
|
&clk_pclk_low,
|
|
};
|
|
|
|
static struct clk dummy_apb_pclk = {
|
|
.name = "apb_pclk",
|
|
.id = -1,
|
|
};
|
|
|
|
void __init_or_cpufreq s5p6440_setup_clocks(void)
|
|
{
|
|
struct clk *xtal_clk;
|
|
|
|
unsigned long xtal;
|
|
unsigned long fclk;
|
|
unsigned long hclk;
|
|
unsigned long hclk_low;
|
|
unsigned long pclk;
|
|
unsigned long pclk_low;
|
|
|
|
unsigned long apll;
|
|
unsigned long mpll;
|
|
unsigned long epll;
|
|
unsigned int ptr;
|
|
|
|
/* Set S5P6440 functions for clk_fout_epll */
|
|
|
|
clk_fout_epll.enable = s5p_epll_enable;
|
|
clk_fout_epll.ops = &s5p6440_epll_ops;
|
|
|
|
clk_48m.enable = s5p64x0_clk48m_ctrl;
|
|
|
|
xtal_clk = clk_get(NULL, "ext_xtal");
|
|
BUG_ON(IS_ERR(xtal_clk));
|
|
|
|
xtal = clk_get_rate(xtal_clk);
|
|
clk_put(xtal_clk);
|
|
|
|
apll = s5p_get_pll45xx(xtal, __raw_readl(S5P64X0_APLL_CON), pll_4502);
|
|
mpll = s5p_get_pll45xx(xtal, __raw_readl(S5P64X0_MPLL_CON), pll_4502);
|
|
epll = s5p_get_pll90xx(xtal, __raw_readl(S5P64X0_EPLL_CON),
|
|
__raw_readl(S5P64X0_EPLL_CON_K));
|
|
|
|
clk_fout_apll.rate = apll;
|
|
clk_fout_mpll.rate = mpll;
|
|
clk_fout_epll.rate = epll;
|
|
|
|
printk(KERN_INFO "S5P6440: PLL settings, A=%ld.%ldMHz, M=%ld.%ldMHz," \
|
|
" E=%ld.%ldMHz\n",
|
|
print_mhz(apll), print_mhz(mpll), print_mhz(epll));
|
|
|
|
fclk = clk_get_rate(&clk_armclk.clk);
|
|
hclk = clk_get_rate(&clk_hclk.clk);
|
|
pclk = clk_get_rate(&clk_pclk.clk);
|
|
hclk_low = clk_get_rate(&clk_hclk_low.clk);
|
|
pclk_low = clk_get_rate(&clk_pclk_low.clk);
|
|
|
|
printk(KERN_INFO "S5P6440: HCLK=%ld.%ldMHz, HCLK_LOW=%ld.%ldMHz," \
|
|
" PCLK=%ld.%ldMHz, PCLK_LOW=%ld.%ldMHz\n",
|
|
print_mhz(hclk), print_mhz(hclk_low),
|
|
print_mhz(pclk), print_mhz(pclk_low));
|
|
|
|
clk_f.rate = fclk;
|
|
clk_h.rate = hclk;
|
|
clk_p.rate = pclk;
|
|
|
|
for (ptr = 0; ptr < ARRAY_SIZE(clksrcs); ptr++)
|
|
s3c_set_clksrc(&clksrcs[ptr], true);
|
|
}
|
|
|
|
static struct clk *clks[] __initdata = {
|
|
&clk_ext,
|
|
&clk_iis_cd_v40,
|
|
&clk_pcm_cd,
|
|
};
|
|
|
|
void __init s5p6440_register_clocks(void)
|
|
{
|
|
int ptr;
|
|
|
|
s3c24xx_register_clocks(clks, ARRAY_SIZE(clks));
|
|
|
|
for (ptr = 0; ptr < ARRAY_SIZE(sysclks); ptr++)
|
|
s3c_register_clksrc(sysclks[ptr], 1);
|
|
|
|
s3c_register_clksrc(clksrcs, ARRAY_SIZE(clksrcs));
|
|
s3c_register_clocks(init_clocks, ARRAY_SIZE(init_clocks));
|
|
|
|
s3c_register_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off));
|
|
s3c_disable_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off));
|
|
|
|
s3c24xx_register_clock(&dummy_apb_pclk);
|
|
|
|
s3c_pwmclk_init();
|
|
}
|