764 lines
24 KiB
C
764 lines
24 KiB
C
/*
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* Linux MegaRAID driver for SAS based RAID controllers
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*
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* Copyright (c) 2009-2012 LSI Corporation.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version 2
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* of the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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*
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* FILE: megaraid_sas_fusion.h
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*
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* Authors: LSI Corporation
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* Manoj Jose
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* Sumant Patro
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*
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* Send feedback to: <megaraidlinux@lsi.com>
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*
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* Mail to: LSI Corporation, 1621 Barber Lane, Milpitas, CA 95035
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* ATTN: Linuxraid
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*/
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#ifndef _MEGARAID_SAS_FUSION_H_
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#define _MEGARAID_SAS_FUSION_H_
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/* Fusion defines */
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#define MEGASAS_MAX_SZ_CHAIN_FRAME 1024
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#define MFI_FUSION_ENABLE_INTERRUPT_MASK (0x00000009)
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#define MEGA_MPI2_RAID_DEFAULT_IO_FRAME_SIZE 256
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#define MEGASAS_MPI2_FUNCTION_PASSTHRU_IO_REQUEST 0xF0
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#define MEGASAS_MPI2_FUNCTION_LD_IO_REQUEST 0xF1
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#define MEGASAS_LOAD_BALANCE_FLAG 0x1
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#define MEGASAS_DCMD_MBOX_PEND_FLAG 0x1
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#define HOST_DIAG_WRITE_ENABLE 0x80
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#define HOST_DIAG_RESET_ADAPTER 0x4
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#define MEGASAS_FUSION_MAX_RESET_TRIES 3
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#define MAX_MSIX_QUEUES_FUSION 128
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/* Invader defines */
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#define MPI2_TYPE_CUDA 0x2
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#define MPI25_SAS_DEVICE0_FLAGS_ENABLED_FAST_PATH 0x4000
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#define MR_RL_FLAGS_GRANT_DESTINATION_CPU0 0x00
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#define MR_RL_FLAGS_GRANT_DESTINATION_CPU1 0x10
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#define MR_RL_FLAGS_GRANT_DESTINATION_CUDA 0x80
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#define MR_RL_FLAGS_SEQ_NUM_ENABLE 0x8
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/* T10 PI defines */
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#define MR_PROT_INFO_TYPE_CONTROLLER 0x8
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#define MEGASAS_SCSI_VARIABLE_LENGTH_CMD 0x7f
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#define MEGASAS_SCSI_SERVICE_ACTION_READ32 0x9
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#define MEGASAS_SCSI_SERVICE_ACTION_WRITE32 0xB
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#define MEGASAS_SCSI_ADDL_CDB_LEN 0x18
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#define MEGASAS_RD_WR_PROTECT_CHECK_ALL 0x20
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#define MEGASAS_RD_WR_PROTECT_CHECK_NONE 0x60
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#define MPI2_SUP_REPLY_POST_HOST_INDEX_OFFSET (0x0000030C)
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#define MPI2_REPLY_POST_HOST_INDEX_OFFSET (0x0000006C)
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/*
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* Raid context flags
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*/
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#define MR_RAID_CTX_RAID_FLAGS_IO_SUB_TYPE_SHIFT 0x4
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#define MR_RAID_CTX_RAID_FLAGS_IO_SUB_TYPE_MASK 0x30
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enum MR_RAID_FLAGS_IO_SUB_TYPE {
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MR_RAID_FLAGS_IO_SUB_TYPE_NONE = 0,
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MR_RAID_FLAGS_IO_SUB_TYPE_SYSTEM_PD = 1,
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};
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/*
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* Request descriptor types
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*/
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#define MEGASAS_REQ_DESCRIPT_FLAGS_LD_IO 0x7
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#define MEGASAS_REQ_DESCRIPT_FLAGS_MFA 0x1
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#define MEGASAS_REQ_DESCRIPT_FLAGS_NO_LOCK 0x2
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#define MEGASAS_REQ_DESCRIPT_FLAGS_TYPE_SHIFT 1
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#define MEGASAS_FP_CMD_LEN 16
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#define MEGASAS_FUSION_IN_RESET 0
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/*
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* Raid Context structure which describes MegaRAID specific IO Parameters
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* This resides at offset 0x60 where the SGL normally starts in MPT IO Frames
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*/
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struct RAID_CONTEXT {
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#if defined(__BIG_ENDIAN_BITFIELD)
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u8 nseg:4;
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u8 Type:4;
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#else
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u8 Type:4;
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u8 nseg:4;
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#endif
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u8 resvd0;
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u16 timeoutValue;
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u8 regLockFlags;
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u8 resvd1;
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u16 VirtualDiskTgtId;
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u64 regLockRowLBA;
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u32 regLockLength;
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u16 nextLMId;
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u8 exStatus;
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u8 status;
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u8 RAIDFlags;
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u8 numSGE;
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u16 configSeqNum;
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u8 spanArm;
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u8 resvd2[3];
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};
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#define RAID_CTX_SPANARM_ARM_SHIFT (0)
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#define RAID_CTX_SPANARM_ARM_MASK (0x1f)
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#define RAID_CTX_SPANARM_SPAN_SHIFT (5)
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#define RAID_CTX_SPANARM_SPAN_MASK (0xE0)
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/*
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* define region lock types
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*/
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enum REGION_TYPE {
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REGION_TYPE_UNUSED = 0,
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REGION_TYPE_SHARED_READ = 1,
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REGION_TYPE_SHARED_WRITE = 2,
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REGION_TYPE_EXCLUSIVE = 3,
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};
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/* MPI2 defines */
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#define MPI2_FUNCTION_IOC_INIT (0x02) /* IOC Init */
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#define MPI2_WHOINIT_HOST_DRIVER (0x04)
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#define MPI2_VERSION_MAJOR (0x02)
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#define MPI2_VERSION_MINOR (0x00)
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#define MPI2_VERSION_MAJOR_MASK (0xFF00)
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#define MPI2_VERSION_MAJOR_SHIFT (8)
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#define MPI2_VERSION_MINOR_MASK (0x00FF)
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#define MPI2_VERSION_MINOR_SHIFT (0)
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#define MPI2_VERSION ((MPI2_VERSION_MAJOR << MPI2_VERSION_MAJOR_SHIFT) | \
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MPI2_VERSION_MINOR)
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#define MPI2_HEADER_VERSION_UNIT (0x10)
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#define MPI2_HEADER_VERSION_DEV (0x00)
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#define MPI2_HEADER_VERSION_UNIT_MASK (0xFF00)
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#define MPI2_HEADER_VERSION_UNIT_SHIFT (8)
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#define MPI2_HEADER_VERSION_DEV_MASK (0x00FF)
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#define MPI2_HEADER_VERSION_DEV_SHIFT (0)
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#define MPI2_HEADER_VERSION ((MPI2_HEADER_VERSION_UNIT << 8) | \
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MPI2_HEADER_VERSION_DEV)
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#define MPI2_IEEE_SGE_FLAGS_IOCPLBNTA_ADDR (0x03)
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#define MPI2_SCSIIO_EEDPFLAGS_INC_PRI_REFTAG (0x8000)
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#define MPI2_SCSIIO_EEDPFLAGS_CHECK_REFTAG (0x0400)
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#define MPI2_SCSIIO_EEDPFLAGS_CHECK_REMOVE_OP (0x0003)
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#define MPI2_SCSIIO_EEDPFLAGS_CHECK_APPTAG (0x0200)
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#define MPI2_SCSIIO_EEDPFLAGS_CHECK_GUARD (0x0100)
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#define MPI2_SCSIIO_EEDPFLAGS_INSERT_OP (0x0004)
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#define MPI2_FUNCTION_SCSI_IO_REQUEST (0x00) /* SCSI IO */
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#define MPI2_REQ_DESCRIPT_FLAGS_HIGH_PRIORITY (0x06)
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#define MPI2_REQ_DESCRIPT_FLAGS_SCSI_IO (0x00)
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#define MPI2_SGE_FLAGS_64_BIT_ADDRESSING (0x02)
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#define MPI2_SCSIIO_CONTROL_WRITE (0x01000000)
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#define MPI2_SCSIIO_CONTROL_READ (0x02000000)
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#define MPI2_REQ_DESCRIPT_FLAGS_TYPE_MASK (0x0E)
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#define MPI2_RPY_DESCRIPT_FLAGS_UNUSED (0x0F)
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#define MPI2_RPY_DESCRIPT_FLAGS_SCSI_IO_SUCCESS (0x00)
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#define MPI2_RPY_DESCRIPT_FLAGS_TYPE_MASK (0x0F)
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#define MPI2_WRSEQ_FLUSH_KEY_VALUE (0x0)
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#define MPI2_WRITE_SEQUENCE_OFFSET (0x00000004)
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#define MPI2_WRSEQ_1ST_KEY_VALUE (0xF)
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#define MPI2_WRSEQ_2ND_KEY_VALUE (0x4)
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#define MPI2_WRSEQ_3RD_KEY_VALUE (0xB)
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#define MPI2_WRSEQ_4TH_KEY_VALUE (0x2)
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#define MPI2_WRSEQ_5TH_KEY_VALUE (0x7)
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#define MPI2_WRSEQ_6TH_KEY_VALUE (0xD)
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struct MPI25_IEEE_SGE_CHAIN64 {
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u64 Address;
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u32 Length;
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u16 Reserved1;
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u8 NextChainOffset;
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u8 Flags;
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};
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struct MPI2_SGE_SIMPLE_UNION {
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u32 FlagsLength;
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union {
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u32 Address32;
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u64 Address64;
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} u;
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};
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struct MPI2_SCSI_IO_CDB_EEDP32 {
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u8 CDB[20]; /* 0x00 */
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u32 PrimaryReferenceTag; /* 0x14 */
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u16 PrimaryApplicationTag; /* 0x18 */
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u16 PrimaryApplicationTagMask; /* 0x1A */
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u32 TransferLength; /* 0x1C */
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};
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struct MPI2_SGE_CHAIN_UNION {
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u16 Length;
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u8 NextChainOffset;
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u8 Flags;
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union {
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u32 Address32;
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u64 Address64;
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} u;
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};
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struct MPI2_IEEE_SGE_SIMPLE32 {
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u32 Address;
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u32 FlagsLength;
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};
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struct MPI2_IEEE_SGE_CHAIN32 {
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u32 Address;
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u32 FlagsLength;
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};
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struct MPI2_IEEE_SGE_SIMPLE64 {
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u64 Address;
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u32 Length;
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u16 Reserved1;
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u8 Reserved2;
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u8 Flags;
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};
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struct MPI2_IEEE_SGE_CHAIN64 {
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u64 Address;
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u32 Length;
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u16 Reserved1;
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u8 Reserved2;
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u8 Flags;
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};
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union MPI2_IEEE_SGE_SIMPLE_UNION {
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struct MPI2_IEEE_SGE_SIMPLE32 Simple32;
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struct MPI2_IEEE_SGE_SIMPLE64 Simple64;
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};
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union MPI2_IEEE_SGE_CHAIN_UNION {
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struct MPI2_IEEE_SGE_CHAIN32 Chain32;
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struct MPI2_IEEE_SGE_CHAIN64 Chain64;
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};
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union MPI2_SGE_IO_UNION {
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struct MPI2_SGE_SIMPLE_UNION MpiSimple;
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struct MPI2_SGE_CHAIN_UNION MpiChain;
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union MPI2_IEEE_SGE_SIMPLE_UNION IeeeSimple;
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union MPI2_IEEE_SGE_CHAIN_UNION IeeeChain;
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};
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union MPI2_SCSI_IO_CDB_UNION {
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u8 CDB32[32];
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struct MPI2_SCSI_IO_CDB_EEDP32 EEDP32;
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struct MPI2_SGE_SIMPLE_UNION SGE;
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};
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/*
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* RAID SCSI IO Request Message
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* Total SGE count will be one less than _MPI2_SCSI_IO_REQUEST
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*/
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struct MPI2_RAID_SCSI_IO_REQUEST {
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u16 DevHandle; /* 0x00 */
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u8 ChainOffset; /* 0x02 */
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u8 Function; /* 0x03 */
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u16 Reserved1; /* 0x04 */
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u8 Reserved2; /* 0x06 */
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u8 MsgFlags; /* 0x07 */
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u8 VP_ID; /* 0x08 */
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u8 VF_ID; /* 0x09 */
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u16 Reserved3; /* 0x0A */
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u32 SenseBufferLowAddress; /* 0x0C */
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u16 SGLFlags; /* 0x10 */
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u8 SenseBufferLength; /* 0x12 */
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u8 Reserved4; /* 0x13 */
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u8 SGLOffset0; /* 0x14 */
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u8 SGLOffset1; /* 0x15 */
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u8 SGLOffset2; /* 0x16 */
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u8 SGLOffset3; /* 0x17 */
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u32 SkipCount; /* 0x18 */
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u32 DataLength; /* 0x1C */
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u32 BidirectionalDataLength; /* 0x20 */
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u16 IoFlags; /* 0x24 */
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u16 EEDPFlags; /* 0x26 */
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u32 EEDPBlockSize; /* 0x28 */
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u32 SecondaryReferenceTag; /* 0x2C */
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u16 SecondaryApplicationTag; /* 0x30 */
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u16 ApplicationTagTranslationMask; /* 0x32 */
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u8 LUN[8]; /* 0x34 */
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u32 Control; /* 0x3C */
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union MPI2_SCSI_IO_CDB_UNION CDB; /* 0x40 */
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struct RAID_CONTEXT RaidContext; /* 0x60 */
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union MPI2_SGE_IO_UNION SGL; /* 0x80 */
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};
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/*
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* MPT RAID MFA IO Descriptor.
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*/
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struct MEGASAS_RAID_MFA_IO_REQUEST_DESCRIPTOR {
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#if defined(__BIG_ENDIAN_BITFIELD)
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u32 MessageAddress1:24; /* bits 31:8*/
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u32 RequestFlags:8;
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#else
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u32 RequestFlags:8;
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u32 MessageAddress1:24; /* bits 31:8*/
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#endif
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u32 MessageAddress2; /* bits 61:32 */
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};
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/* Default Request Descriptor */
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struct MPI2_DEFAULT_REQUEST_DESCRIPTOR {
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u8 RequestFlags; /* 0x00 */
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u8 MSIxIndex; /* 0x01 */
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u16 SMID; /* 0x02 */
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u16 LMID; /* 0x04 */
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u16 DescriptorTypeDependent; /* 0x06 */
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};
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/* High Priority Request Descriptor */
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struct MPI2_HIGH_PRIORITY_REQUEST_DESCRIPTOR {
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u8 RequestFlags; /* 0x00 */
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u8 MSIxIndex; /* 0x01 */
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u16 SMID; /* 0x02 */
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u16 LMID; /* 0x04 */
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u16 Reserved1; /* 0x06 */
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};
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/* SCSI IO Request Descriptor */
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struct MPI2_SCSI_IO_REQUEST_DESCRIPTOR {
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u8 RequestFlags; /* 0x00 */
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u8 MSIxIndex; /* 0x01 */
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u16 SMID; /* 0x02 */
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u16 LMID; /* 0x04 */
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u16 DevHandle; /* 0x06 */
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};
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/* SCSI Target Request Descriptor */
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struct MPI2_SCSI_TARGET_REQUEST_DESCRIPTOR {
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u8 RequestFlags; /* 0x00 */
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u8 MSIxIndex; /* 0x01 */
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u16 SMID; /* 0x02 */
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u16 LMID; /* 0x04 */
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u16 IoIndex; /* 0x06 */
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};
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/* RAID Accelerator Request Descriptor */
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struct MPI2_RAID_ACCEL_REQUEST_DESCRIPTOR {
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u8 RequestFlags; /* 0x00 */
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u8 MSIxIndex; /* 0x01 */
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u16 SMID; /* 0x02 */
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u16 LMID; /* 0x04 */
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u16 Reserved; /* 0x06 */
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};
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/* union of Request Descriptors */
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union MEGASAS_REQUEST_DESCRIPTOR_UNION {
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struct MPI2_DEFAULT_REQUEST_DESCRIPTOR Default;
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struct MPI2_HIGH_PRIORITY_REQUEST_DESCRIPTOR HighPriority;
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struct MPI2_SCSI_IO_REQUEST_DESCRIPTOR SCSIIO;
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struct MPI2_SCSI_TARGET_REQUEST_DESCRIPTOR SCSITarget;
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struct MPI2_RAID_ACCEL_REQUEST_DESCRIPTOR RAIDAccelerator;
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struct MEGASAS_RAID_MFA_IO_REQUEST_DESCRIPTOR MFAIo;
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union {
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struct {
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u32 low;
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u32 high;
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} u;
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u64 Words;
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};
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};
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/* Default Reply Descriptor */
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struct MPI2_DEFAULT_REPLY_DESCRIPTOR {
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u8 ReplyFlags; /* 0x00 */
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u8 MSIxIndex; /* 0x01 */
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u16 DescriptorTypeDependent1; /* 0x02 */
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u32 DescriptorTypeDependent2; /* 0x04 */
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};
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/* Address Reply Descriptor */
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struct MPI2_ADDRESS_REPLY_DESCRIPTOR {
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u8 ReplyFlags; /* 0x00 */
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u8 MSIxIndex; /* 0x01 */
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u16 SMID; /* 0x02 */
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u32 ReplyFrameAddress; /* 0x04 */
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};
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/* SCSI IO Success Reply Descriptor */
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struct MPI2_SCSI_IO_SUCCESS_REPLY_DESCRIPTOR {
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u8 ReplyFlags; /* 0x00 */
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u8 MSIxIndex; /* 0x01 */
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u16 SMID; /* 0x02 */
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u16 TaskTag; /* 0x04 */
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u16 Reserved1; /* 0x06 */
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};
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/* TargetAssist Success Reply Descriptor */
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struct MPI2_TARGETASSIST_SUCCESS_REPLY_DESCRIPTOR {
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u8 ReplyFlags; /* 0x00 */
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u8 MSIxIndex; /* 0x01 */
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u16 SMID; /* 0x02 */
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u8 SequenceNumber; /* 0x04 */
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u8 Reserved1; /* 0x05 */
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u16 IoIndex; /* 0x06 */
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};
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/* Target Command Buffer Reply Descriptor */
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struct MPI2_TARGET_COMMAND_BUFFER_REPLY_DESCRIPTOR {
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u8 ReplyFlags; /* 0x00 */
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u8 MSIxIndex; /* 0x01 */
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u8 VP_ID; /* 0x02 */
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u8 Flags; /* 0x03 */
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u16 InitiatorDevHandle; /* 0x04 */
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u16 IoIndex; /* 0x06 */
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};
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|
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/* RAID Accelerator Success Reply Descriptor */
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struct MPI2_RAID_ACCELERATOR_SUCCESS_REPLY_DESCRIPTOR {
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u8 ReplyFlags; /* 0x00 */
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u8 MSIxIndex; /* 0x01 */
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u16 SMID; /* 0x02 */
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u32 Reserved; /* 0x04 */
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};
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/* union of Reply Descriptors */
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union MPI2_REPLY_DESCRIPTORS_UNION {
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struct MPI2_DEFAULT_REPLY_DESCRIPTOR Default;
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struct MPI2_ADDRESS_REPLY_DESCRIPTOR AddressReply;
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struct MPI2_SCSI_IO_SUCCESS_REPLY_DESCRIPTOR SCSIIOSuccess;
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struct MPI2_TARGETASSIST_SUCCESS_REPLY_DESCRIPTOR TargetAssistSuccess;
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struct MPI2_TARGET_COMMAND_BUFFER_REPLY_DESCRIPTOR TargetCommandBuffer;
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struct MPI2_RAID_ACCELERATOR_SUCCESS_REPLY_DESCRIPTOR
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RAIDAcceleratorSuccess;
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u64 Words;
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};
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/* IOCInit Request message */
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struct MPI2_IOC_INIT_REQUEST {
|
|
u8 WhoInit; /* 0x00 */
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u8 Reserved1; /* 0x01 */
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u8 ChainOffset; /* 0x02 */
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u8 Function; /* 0x03 */
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u16 Reserved2; /* 0x04 */
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u8 Reserved3; /* 0x06 */
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u8 MsgFlags; /* 0x07 */
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u8 VP_ID; /* 0x08 */
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u8 VF_ID; /* 0x09 */
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u16 Reserved4; /* 0x0A */
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u16 MsgVersion; /* 0x0C */
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|
u16 HeaderVersion; /* 0x0E */
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|
u32 Reserved5; /* 0x10 */
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|
u16 Reserved6; /* 0x14 */
|
|
u8 Reserved7; /* 0x16 */
|
|
u8 HostMSIxVectors; /* 0x17 */
|
|
u16 Reserved8; /* 0x18 */
|
|
u16 SystemRequestFrameSize; /* 0x1A */
|
|
u16 ReplyDescriptorPostQueueDepth; /* 0x1C */
|
|
u16 ReplyFreeQueueDepth; /* 0x1E */
|
|
u32 SenseBufferAddressHigh; /* 0x20 */
|
|
u32 SystemReplyAddressHigh; /* 0x24 */
|
|
u64 SystemRequestFrameBaseAddress; /* 0x28 */
|
|
u64 ReplyDescriptorPostQueueAddress;/* 0x30 */
|
|
u64 ReplyFreeQueueAddress; /* 0x38 */
|
|
u64 TimeStamp; /* 0x40 */
|
|
};
|
|
|
|
/* mrpriv defines */
|
|
#define MR_PD_INVALID 0xFFFF
|
|
#define MAX_SPAN_DEPTH 8
|
|
#define MAX_QUAD_DEPTH MAX_SPAN_DEPTH
|
|
#define MAX_RAIDMAP_SPAN_DEPTH (MAX_SPAN_DEPTH)
|
|
#define MAX_ROW_SIZE 32
|
|
#define MAX_RAIDMAP_ROW_SIZE (MAX_ROW_SIZE)
|
|
#define MAX_LOGICAL_DRIVES 64
|
|
#define MAX_RAIDMAP_LOGICAL_DRIVES (MAX_LOGICAL_DRIVES)
|
|
#define MAX_RAIDMAP_VIEWS (MAX_LOGICAL_DRIVES)
|
|
#define MAX_ARRAYS 128
|
|
#define MAX_RAIDMAP_ARRAYS (MAX_ARRAYS)
|
|
#define MAX_PHYSICAL_DEVICES 256
|
|
#define MAX_RAIDMAP_PHYSICAL_DEVICES (MAX_PHYSICAL_DEVICES)
|
|
#define MR_DCMD_LD_MAP_GET_INFO 0x0300e101
|
|
|
|
struct MR_DEV_HANDLE_INFO {
|
|
u16 curDevHdl;
|
|
u8 validHandles;
|
|
u8 reserved;
|
|
u16 devHandle[2];
|
|
};
|
|
|
|
struct MR_ARRAY_INFO {
|
|
u16 pd[MAX_RAIDMAP_ROW_SIZE];
|
|
};
|
|
|
|
struct MR_QUAD_ELEMENT {
|
|
u64 logStart;
|
|
u64 logEnd;
|
|
u64 offsetInSpan;
|
|
u32 diff;
|
|
u32 reserved1;
|
|
};
|
|
|
|
struct MR_SPAN_INFO {
|
|
u32 noElements;
|
|
u32 reserved1;
|
|
struct MR_QUAD_ELEMENT quad[MAX_RAIDMAP_SPAN_DEPTH];
|
|
};
|
|
|
|
struct MR_LD_SPAN {
|
|
u64 startBlk;
|
|
u64 numBlks;
|
|
u16 arrayRef;
|
|
u8 spanRowSize;
|
|
u8 spanRowDataSize;
|
|
u8 reserved[4];
|
|
};
|
|
|
|
struct MR_SPAN_BLOCK_INFO {
|
|
u64 num_rows;
|
|
struct MR_LD_SPAN span;
|
|
struct MR_SPAN_INFO block_span_info;
|
|
};
|
|
|
|
struct MR_LD_RAID {
|
|
struct {
|
|
#if defined(__BIG_ENDIAN_BITFIELD)
|
|
u32 reserved4:7;
|
|
u32 fpNonRWCapable:1;
|
|
u32 fpReadAcrossStripe:1;
|
|
u32 fpWriteAcrossStripe:1;
|
|
u32 fpReadCapable:1;
|
|
u32 fpWriteCapable:1;
|
|
u32 encryptionType:8;
|
|
u32 pdPiMode:4;
|
|
u32 ldPiMode:4;
|
|
u32 reserved5:3;
|
|
u32 fpCapable:1;
|
|
#else
|
|
u32 fpCapable:1;
|
|
u32 reserved5:3;
|
|
u32 ldPiMode:4;
|
|
u32 pdPiMode:4;
|
|
u32 encryptionType:8;
|
|
u32 fpWriteCapable:1;
|
|
u32 fpReadCapable:1;
|
|
u32 fpWriteAcrossStripe:1;
|
|
u32 fpReadAcrossStripe:1;
|
|
u32 fpNonRWCapable:1;
|
|
u32 reserved4:7;
|
|
#endif
|
|
} capability;
|
|
u32 reserved6;
|
|
u64 size;
|
|
u8 spanDepth;
|
|
u8 level;
|
|
u8 stripeShift;
|
|
u8 rowSize;
|
|
u8 rowDataSize;
|
|
u8 writeMode;
|
|
u8 PRL;
|
|
u8 SRL;
|
|
u16 targetId;
|
|
u8 ldState;
|
|
u8 regTypeReqOnWrite;
|
|
u8 modFactor;
|
|
u8 regTypeReqOnRead;
|
|
u16 seqNum;
|
|
|
|
struct {
|
|
u32 ldSyncRequired:1;
|
|
u32 reserved:31;
|
|
} flags;
|
|
|
|
u8 LUN[8]; /* 0x24 8 byte LUN field used for SCSI IO's */
|
|
u8 fpIoTimeoutForLd;/*0x2C timeout value used by driver in FP IO*/
|
|
u8 reserved3[0x80-0x2D]; /* 0x2D */
|
|
};
|
|
|
|
struct MR_LD_SPAN_MAP {
|
|
struct MR_LD_RAID ldRaid;
|
|
u8 dataArmMap[MAX_RAIDMAP_ROW_SIZE];
|
|
struct MR_SPAN_BLOCK_INFO spanBlock[MAX_RAIDMAP_SPAN_DEPTH];
|
|
};
|
|
|
|
struct MR_FW_RAID_MAP {
|
|
u32 totalSize;
|
|
union {
|
|
struct {
|
|
u32 maxLd;
|
|
u32 maxSpanDepth;
|
|
u32 maxRowSize;
|
|
u32 maxPdCount;
|
|
u32 maxArrays;
|
|
} validationInfo;
|
|
u32 version[5];
|
|
u32 reserved1[5];
|
|
};
|
|
|
|
u32 ldCount;
|
|
u32 Reserved1;
|
|
u8 ldTgtIdToLd[MAX_RAIDMAP_LOGICAL_DRIVES+
|
|
MAX_RAIDMAP_VIEWS];
|
|
u8 fpPdIoTimeoutSec;
|
|
u8 reserved2[7];
|
|
struct MR_ARRAY_INFO arMapInfo[MAX_RAIDMAP_ARRAYS];
|
|
struct MR_DEV_HANDLE_INFO devHndlInfo[MAX_RAIDMAP_PHYSICAL_DEVICES];
|
|
struct MR_LD_SPAN_MAP ldSpanMap[1];
|
|
};
|
|
|
|
struct IO_REQUEST_INFO {
|
|
u64 ldStartBlock;
|
|
u32 numBlocks;
|
|
u16 ldTgtId;
|
|
u8 isRead;
|
|
u16 devHandle;
|
|
u64 pdBlock;
|
|
u8 fpOkForIo;
|
|
u8 IoforUnevenSpan;
|
|
u8 start_span;
|
|
u8 reserved;
|
|
u64 start_row;
|
|
};
|
|
|
|
struct MR_LD_TARGET_SYNC {
|
|
u8 targetId;
|
|
u8 reserved;
|
|
u16 seqNum;
|
|
};
|
|
|
|
#define IEEE_SGE_FLAGS_ADDR_MASK (0x03)
|
|
#define IEEE_SGE_FLAGS_SYSTEM_ADDR (0x00)
|
|
#define IEEE_SGE_FLAGS_IOCDDR_ADDR (0x01)
|
|
#define IEEE_SGE_FLAGS_IOCPLB_ADDR (0x02)
|
|
#define IEEE_SGE_FLAGS_IOCPLBNTA_ADDR (0x03)
|
|
#define IEEE_SGE_FLAGS_CHAIN_ELEMENT (0x80)
|
|
#define IEEE_SGE_FLAGS_END_OF_LIST (0x40)
|
|
|
|
struct megasas_register_set;
|
|
struct megasas_instance;
|
|
|
|
union desc_word {
|
|
u64 word;
|
|
struct {
|
|
u32 low;
|
|
u32 high;
|
|
} u;
|
|
};
|
|
|
|
struct megasas_cmd_fusion {
|
|
struct MPI2_RAID_SCSI_IO_REQUEST *io_request;
|
|
dma_addr_t io_request_phys_addr;
|
|
|
|
union MPI2_SGE_IO_UNION *sg_frame;
|
|
dma_addr_t sg_frame_phys_addr;
|
|
|
|
u8 *sense;
|
|
dma_addr_t sense_phys_addr;
|
|
|
|
struct list_head list;
|
|
struct scsi_cmnd *scmd;
|
|
struct megasas_instance *instance;
|
|
|
|
u8 retry_for_fw_reset;
|
|
union MEGASAS_REQUEST_DESCRIPTOR_UNION *request_desc;
|
|
|
|
/*
|
|
* Context for a MFI frame.
|
|
* Used to get the mfi cmd from list when a MFI cmd is completed
|
|
*/
|
|
u32 sync_cmd_idx;
|
|
u32 index;
|
|
u8 flags;
|
|
};
|
|
|
|
struct LD_LOAD_BALANCE_INFO {
|
|
u8 loadBalanceFlag;
|
|
u8 reserved1;
|
|
u16 raid1DevHandle[2];
|
|
atomic_t scsi_pending_cmds[2];
|
|
u64 last_accessed_block[2];
|
|
};
|
|
|
|
/* SPAN_SET is info caclulated from span info from Raid map per LD */
|
|
typedef struct _LD_SPAN_SET {
|
|
u64 log_start_lba;
|
|
u64 log_end_lba;
|
|
u64 span_row_start;
|
|
u64 span_row_end;
|
|
u64 data_strip_start;
|
|
u64 data_strip_end;
|
|
u64 data_row_start;
|
|
u64 data_row_end;
|
|
u8 strip_offset[MAX_SPAN_DEPTH];
|
|
u32 span_row_data_width;
|
|
u32 diff;
|
|
u32 reserved[2];
|
|
} LD_SPAN_SET, *PLD_SPAN_SET;
|
|
|
|
typedef struct LOG_BLOCK_SPAN_INFO {
|
|
LD_SPAN_SET span_set[MAX_SPAN_DEPTH];
|
|
} LD_SPAN_INFO, *PLD_SPAN_INFO;
|
|
|
|
struct MR_FW_RAID_MAP_ALL {
|
|
struct MR_FW_RAID_MAP raidMap;
|
|
struct MR_LD_SPAN_MAP ldSpanMap[MAX_LOGICAL_DRIVES - 1];
|
|
} __attribute__ ((packed));
|
|
|
|
struct fusion_context {
|
|
struct megasas_cmd_fusion **cmd_list;
|
|
struct list_head cmd_pool;
|
|
|
|
spinlock_t cmd_pool_lock;
|
|
|
|
dma_addr_t req_frames_desc_phys;
|
|
u8 *req_frames_desc;
|
|
|
|
struct dma_pool *io_request_frames_pool;
|
|
dma_addr_t io_request_frames_phys;
|
|
u8 *io_request_frames;
|
|
|
|
struct dma_pool *sg_dma_pool;
|
|
struct dma_pool *sense_dma_pool;
|
|
|
|
dma_addr_t reply_frames_desc_phys;
|
|
union MPI2_REPLY_DESCRIPTORS_UNION *reply_frames_desc;
|
|
struct dma_pool *reply_frames_desc_pool;
|
|
|
|
u16 last_reply_idx[MAX_MSIX_QUEUES_FUSION];
|
|
|
|
u32 reply_q_depth;
|
|
u32 request_alloc_sz;
|
|
u32 reply_alloc_sz;
|
|
u32 io_frames_alloc_sz;
|
|
|
|
u16 max_sge_in_main_msg;
|
|
u16 max_sge_in_chain;
|
|
|
|
u8 chain_offset_io_request;
|
|
u8 chain_offset_mfi_pthru;
|
|
|
|
struct MR_FW_RAID_MAP_ALL *ld_map[2];
|
|
dma_addr_t ld_map_phys[2];
|
|
|
|
u32 map_sz;
|
|
u8 fast_path_io;
|
|
struct LD_LOAD_BALANCE_INFO load_balance_info[MAX_LOGICAL_DRIVES];
|
|
LD_SPAN_INFO log_to_span[MAX_LOGICAL_DRIVES];
|
|
};
|
|
|
|
union desc_value {
|
|
u64 word;
|
|
struct {
|
|
u32 low;
|
|
u32 high;
|
|
} u;
|
|
};
|
|
|
|
#endif /* _MEGARAID_SAS_FUSION_H_ */
|