150 lines
4.4 KiB
C
150 lines
4.4 KiB
C
/*
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* Copyright(c) 2015 Intel Corporation. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of version 2 of the GNU General Public License as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful, but
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* WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* General Public License for more details.
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*/
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#ifndef __ASM_X86_PMEM_H__
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#define __ASM_X86_PMEM_H__
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#include <linux/uaccess.h>
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#include <asm/cacheflush.h>
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#include <asm/cpufeature.h>
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#include <asm/special_insns.h>
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#ifdef CONFIG_ARCH_HAS_PMEM_API
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/**
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* arch_memcpy_to_pmem - copy data to persistent memory
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* @dst: destination buffer for the copy
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* @src: source buffer for the copy
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* @n: length of the copy in bytes
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*
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* Copy data to persistent memory media via non-temporal stores so that
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* a subsequent arch_wmb_pmem() can flush cpu and memory controller
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* write buffers to guarantee durability.
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*/
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static inline void arch_memcpy_to_pmem(void __pmem *dst, const void *src,
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size_t n)
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{
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int unwritten;
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/*
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* We are copying between two kernel buffers, if
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* __copy_from_user_inatomic_nocache() returns an error (page
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* fault) we would have already reported a general protection fault
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* before the WARN+BUG.
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*/
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unwritten = __copy_from_user_inatomic_nocache((void __force *) dst,
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(void __user *) src, n);
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if (WARN(unwritten, "%s: fault copying %p <- %p unwritten: %d\n",
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__func__, dst, src, unwritten))
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BUG();
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}
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/**
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* arch_wmb_pmem - synchronize writes to persistent memory
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*
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* After a series of arch_memcpy_to_pmem() operations this drains data
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* from cpu write buffers and any platform (memory controller) buffers
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* to ensure that written data is durable on persistent memory media.
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*/
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static inline void arch_wmb_pmem(void)
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{
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/*
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* wmb() to 'sfence' all previous writes such that they are
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* architecturally visible to 'pcommit'. Note, that we've
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* already arranged for pmem writes to avoid the cache via
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* arch_memcpy_to_pmem().
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*/
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wmb();
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pcommit_sfence();
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}
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/**
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* arch_wb_cache_pmem - write back a cache range with CLWB
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* @vaddr: virtual start address
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* @size: number of bytes to write back
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*
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* Write back a cache range using the CLWB (cache line write back)
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* instruction. This function requires explicit ordering with an
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* arch_wmb_pmem() call.
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*/
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static inline void arch_wb_cache_pmem(void __pmem *addr, size_t size)
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{
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u16 x86_clflush_size = boot_cpu_data.x86_clflush_size;
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unsigned long clflush_mask = x86_clflush_size - 1;
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void *vaddr = (void __force *)addr;
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void *vend = vaddr + size;
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void *p;
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for (p = (void *)((unsigned long)vaddr & ~clflush_mask);
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p < vend; p += x86_clflush_size)
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clwb(p);
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}
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/*
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* copy_from_iter_nocache() on x86 only uses non-temporal stores for iovec
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* iterators, so for other types (bvec & kvec) we must do a cache write-back.
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*/
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static inline bool __iter_needs_pmem_wb(struct iov_iter *i)
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{
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return iter_is_iovec(i) == false;
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}
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/**
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* arch_copy_from_iter_pmem - copy data from an iterator to PMEM
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* @addr: PMEM destination address
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* @bytes: number of bytes to copy
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* @i: iterator with source data
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*
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* Copy data from the iterator 'i' to the PMEM buffer starting at 'addr'.
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* This function requires explicit ordering with an arch_wmb_pmem() call.
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*/
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static inline size_t arch_copy_from_iter_pmem(void __pmem *addr, size_t bytes,
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struct iov_iter *i)
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{
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void *vaddr = (void __force *)addr;
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size_t len;
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/* TODO: skip the write-back by always using non-temporal stores */
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len = copy_from_iter_nocache(vaddr, bytes, i);
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if (__iter_needs_pmem_wb(i))
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arch_wb_cache_pmem(addr, bytes);
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return len;
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}
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/**
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* arch_clear_pmem - zero a PMEM memory range
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* @addr: virtual start address
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* @size: number of bytes to zero
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*
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* Write zeros into the memory range starting at 'addr' for 'size' bytes.
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* This function requires explicit ordering with an arch_wmb_pmem() call.
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*/
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static inline void arch_clear_pmem(void __pmem *addr, size_t size)
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{
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void *vaddr = (void __force *)addr;
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memset(vaddr, 0, size);
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arch_wb_cache_pmem(addr, size);
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}
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static inline bool __arch_has_wmb_pmem(void)
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{
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/*
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* We require that wmb() be an 'sfence', that is only guaranteed on
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* 64-bit builds
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*/
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return static_cpu_has(X86_FEATURE_PCOMMIT);
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}
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#endif /* CONFIG_ARCH_HAS_PMEM_API */
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#endif /* __ASM_X86_PMEM_H__ */
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